JPS6327865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an improvement for increasing the reverse surge voltage breakdown strength of a diode device.

Hereinafter, a diode device for configuring a bipolar semiconductor integrated circuit device will be explained as an example.

FIG. 1 is a sectional view showing an example of a conventional diode device for configuring a bipolar semiconductor integrated circuit device.

In the figure, 1 is a p-type silicon (Si) substrate,
This p-type Si substrate 1 constitutes an anode region. 2 is p
A low impurity concentration n ^- type epitaxially grown semiconductor layer (hereinafter referred to as "n ^- type epitaxial layer") epitaxially grown on the main surface of a Si-type substrate 1;
is a part of the surface of the n ^-type epitaxial layer 2.
n ⁺ type cathode region with a high impurity concentration formed by selectively diffusing type impurities to a high concentration, 4
surrounds the n ⁺ type cathode region 3 with a predetermined distance therebetween, and forms the n ^- type epitaxial layer 2.
A layer with a high impurity concentration of about 10 ¹⁸ to 10 ¹⁹ /cm ³ is formed by selectively diffusing p-type impurities at a high concentration so as to reach the p-type Si substrate 1 from the surface.
p ⁺ type element isolation layer (hereinafter referred to as "p ⁺ type isolation layer"), 5 is a p ⁺ type on the surface of n ^- type epitaxial layer 2;
Silicon oxide (SiO ₂ ) formed over the surface of the type separation layer 4 and the surface of the n ⁺ type cathode region 3
6 is an anode electrode connected to the p ⁺ type separation layer 4 through a contact hole provided in the SiO ₂ film 5 on the p ⁺ type separation layer 4, and 7 is on the n ⁺ type cathode region 3.
This is a cathode electrode connected to the n ⁺ type cathode region 3 through a contact hole provided in the SiO ₂ film 5.

In a diode configured in this way,
In order for the p ⁺ type isolation layer 4 to sufficiently electrically isolate the elements, a parasitic npn transistor operation must be performed between the p ⁺ type isolation layer 4 and the n ^- type epitaxial layer 2 in contact with both sides thereof. The impurity concentration of the p ⁺ type separation layer 4 is set to 10 ¹⁸ to 10 ¹⁹ /cm ³ due to the need to prevent the formation of p-type impurities and to diffuse the p ^- type impurity to a thickness greater than the thickness of the n - type epitaxial layer 2. It is necessary to set the impurity concentration to a certain level. Also, for example 200V
In order to have a reverse voltage strength of
The impurity concentration of the n ^- type epitaxial layer 2 is lowered so that the depletion layer [A and B shown in the figure] extending from the p type Si substrate 1 and the p ⁺ type separation layer 4 forms an n ^- type epitaxial layer on the n ⁺ type cathode region 3 side. It is necessary to ensure that it spreads sufficiently into the layer 2. However, the thinner the n ^- type epitaxial layer 2 is, the more advantageous it is from the viewpoint of defects that occur during epitaxial growth and the diffusion time of impurities during the formation of the p ⁺ type separation layer 4. becomes difficult. On the other hand, when the thickness of the n ^- type epitaxial layer 2 is thin, the reverse voltage intensity becomes small as described below. That is, when a high reverse voltage is applied between the anode electrode 6 and the cathode electrode 7, a depletion occurs extending from the p-type Si substrate 1 to the portion in the n ^- type epitaxial layer 2 directly under the n ⁺ type cathode region 3. The layer A reaches the n ⁺ type cathode region 3 earlier than the depletion layer b extending from the p ⁺ type isolation layer 4 into the epitaxial layer 2 along its surface,
Punch-through occurs in the portion within the n ^- type epitaxial layer 2 immediately below. Then, the current flows in a concentrated manner directly under this n ⁺ type cathode region 3, and since there is no high resistance (low impurity concentration) layer to limit this concentrated current, the reverse voltage is caused by a narrow reverse surge. Even if the voltage is low, this reverse surge voltage will cause ice damage.

This invention was made in view of the above-mentioned drawbacks, and a main electrode region with a high impurity concentration is formed in a part of the surface portion, and a semiconductor layer of the same conductivity type as this main electrode region is directly below the main electrode region. A punch-through occurs along the surface portion before the punch-through, and a current limiting resistor is formed on the surface portion to limit the current flowing to the main electrode region due to the punch-through. By doing so, it is an object of the present invention to provide a semiconductor device which has a large reverse surge voltage breakdown strength and does not suffer from ice breakdown due to a narrow reverse surge voltage.

FIGS. 2A and 2B are a cross-sectional view showing one embodiment of the present invention and a perspective view showing a part of its main part in cross-section, respectively.

In the figure, the same reference numerals as those shown in the conventional example of FIG. 1 indicate the same things. 8 is a first distance x between the surface of the n ^- type epitaxial layer 2 sandwiched between the n ⁺ type cathode region 3 and the p ⁺ type separation layer 4 and the p ⁺ type separation layer 4. ₁ and a second distance x ₂ between the n ⁺ type cathode region ³ and the n ⁺ type cathode region 3, and having a width w and having a high impurity concentration. Note that the above distance x ₁ is
It is set to be smaller than the thickness t of the n ^- type epitaxial layer 2 directly under the n ⁺ type cathode region 3 .

Next, the operation of this embodiment will be explained.

When a reverse surge voltage is applied between the anode electrode 6 and the cathode electrode 7, first, the p ⁺ type separation layer 4
A depletion layer extending along the surface of the n ^- type epitaxial layer 2 toward the n ⁺ type cathode region 3 side reaches a part of the n ⁺ type intermediate layer 8, and this part of the n ⁺ type intermediate layer 8 and the p ⁺ Punch-through occurs in the surface portion of the n ^- type epitaxial layer 2 between the type separation layer 4 and the n - type epitaxial layer 2 . Then, due to this punch-through, the current flowing through the surface of the n ^- type epitaxial layer 2 is sandwiched between the n ⁺ type intermediate layer 8 and the n ⁺ type cathode region 3.
n ⁺ type cathode region 3 via n ^- type epitaxial layer 2
flows to Therefore, the part of the n ⁺ type intermediate layer 8 and
The resistance of the n ^- type epitaxial layer 2 sandwiched between the n ⁺ type cathode region 3 acts as a current limiting resistance that limits the current due to the punch-through, and also reduces the energy of the narrow reverse surge voltage. , the reverse surge voltage breakdown strength can be increased. In order to ^make this current limiting resistance a sufficiently large value, increase the distance x ₂ shown in ^FIG . The resistance of the ^{n +} type intermediate layer 8 in the direction along the circumference of the exposed surface exposed on the surface of the - type epitaxial layer 2 (the y direction shown in FIG. 2B) is increased, and this resistance increases the resistance in this y direction. What is necessary is to limit the spread of the current due to the punch-through.

On the other hand, when a forward voltage is applied between the anode electrode 6 and the cathode electrode 7, the n ^- type epitaxial layer 2
The resistance along the surface becomes large due to the above-mentioned current limiting resistance, but since the forward current mainly flows from the n ⁺ type cathode region 3 to the p-type Si substrate 1 directly below it, the voltage drop in the forward direction is It doesn't get bigger.

In this example, the n ⁺ type intermediate layer 8 was formed continuously in the direction (y direction in the figure) along the circumference of the exposed surface of the n ^- type epitaxial layer 2 of the n ⁺ type cathode region 3. However, it is not necessarily necessary to form this continuously, and as in ^other embodiments shown in FIGS. An n ⁺ -shaped intermediate layer 8a having a rectangular cross section or a round cross-section is sequentially spaced at a predetermined interval from each other in the direction along the circumference of the exposed surface exposed on the surface of the n ^- epitaxial layer 2 (the y direction in the figure). The n ⁺ -type intermediate layer 8b may be formed discontinuously. In these other embodiments, it is possible to more effectively restrict the spread of the current due to the punch-through in the y direction.

In the above embodiments, the present invention can also be applied when the n-type region is replaced with a p-type region and the p-type region is replaced with an n-type region.

Although a diode device for configuring a bipolar semiconductor integrated circuit device has been described as an example, the present invention is not limited to this. surrounding the first semiconductor layer with a predetermined distance between the main electrode region of the second conductivity type formed on a part of the surface of the first semiconductor layer, and the main electrode region. As such, the present invention can also be applied to other semiconductor devices including a second semiconductor layer of the first conductivity type provided within the first semiconductor layer and at substantially the same potential as the semiconductor substrate.

As described above, in the semiconductor device of the present invention, the first semiconductor substrate of the second conductivity type with a low impurity concentration is formed on the main surface of the semiconductor substrate of the first conductivity type constituting the first main electrode region. A semiconductor layer, a second main electrode region of the second conductivity type with a high impurity concentration formed on a part of the surface of the first semiconductor layer, and a first main electrode region between the second main electrode region and the second main electrode region. a second semiconductor layer of a first conductivity type provided within the first semiconductor layer so as to surround it at a predetermined distance from the semiconductor substrate and having substantially the same potential as the semiconductor substrate; around the second main electrode on the surface portion of the first semiconductor layer sandwiched between the second main electrode region and the second semiconductor layer; A third semiconductor layer of the second conductivity type is provided with a second predetermined distance between the main electrode region and the second main electrode region, and a third semiconductor layer of the second conductivity type is provided with a second predetermined distance between the second main electrode region and the second main electrode region. Since the thickness of the first semiconductor layer sandwiched between the second main electrode region and the semiconductor substrate is smaller than the thickness of the first semiconductor layer sandwiched between the second main electrode region and the second main electrode region, When a surge voltage is applied, the second semiconductor layer and the first semiconductor layer are separated from each other before the portion of the first semiconductor layer sandwiched between the second main electrode region and the semiconductor substrate. Punch-through can be caused along the surface portion of the first semiconductor layer sandwiched between the third semiconductor layer and the second main electrode region. The resistor of the first semiconductor layer sandwiched between operates as a current limiting resistor that limits the current flowing to the second main electrode region due to the punch-through. Therefore, the reverse surge voltage breakdown strength can be increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an example of a conventional diode device for configuring a bipolar semiconductor integrated circuit device;
Figures 2A and B are a sectional view and a perspective view, respectively, showing an embodiment of the present invention, and a perspective view of a part of the main part thereof, and Figures 3A and B are main views of another embodiment of the invention. It is a perspective view showing a part of the section in cross section. In the figure, 1 is a p-type Si substrate (first conductivity type semiconductor substrate), 2 is an n ^- type epitaxial layer (second conductivity type first semiconductor layer), and 3 is an n ⁺ type cathode region (second conductivity type). 4 is a p ⁺ type separation layer (second conduction type second semiconductor layer), 8 is an n ⁺ type intermediate layer (second conduction type third semiconductor layer) , x ₁ is (second
(the third predetermined distance), _x2 is (the third predetermined distance).
Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first main electrode region formed of a semiconductor substrate of a first conductivity type, and a first semiconductor of a second conductivity type with a low impurity concentration formed on the main surface of the semiconductor substrate. a second main electrode region of a second conductivity type with a high impurity concentration formed on a part of the surface of the first semiconductor layer; and a second semiconductor layer of a first conductivity type provided within the first semiconductor layer so as to reach the semiconductor substrate from the surface of the first semiconductor layer and having substantially the same potential as the semiconductor substrate. In the device, the second main electrode region is provided around the second main electrode region on the surface portion of the first semiconductor layer sandwiched between the second main electrode region and the second semiconductor layer. A third semiconductor layer of a second conductivity type is provided with a first distance between the semiconductor layer and the second main electrode region, and a third semiconductor layer of the second conductivity type with a second distance between the third semiconductor layer and the second main electrode region; is smaller than the thickness of the first semiconductor layer sandwiched between the second main electrode region and the semiconductor substrate, and the thickness of the second semiconductor layer and the third semiconductor layer are
The current flowing to the second main electrode region is limited by the punch-through generated between the second main electrode region and the third semiconductor layer and the resistance between the second main electrode region and the third semiconductor layer. Characteristic semiconductor devices. 2. Claim 1, characterized in that the third semiconductor layer is provided continuously in the direction along the circumference of the exposed surface exposed on the surface of the first semiconductor layer in the second main electrode region. The semiconductor device described. 3. The third semiconductor layer is discontinuously provided at predetermined intervals in the direction along the circumference of the exposed surface of the first semiconductor layer in the second main electrode region. A semiconductor device according to claim 1.