JPH06342903A - Lateral conductivity modulation mosfet - Google Patents

Abstract

PURPOSE:To obtain a lateral conductivity modulation MOSFET, in which a latch-up is difficult to be generated. CONSTITUTION:A p-type base diffusion layer 33 is formed to a high resistance layer 32 section on the drain layer side of a semiconductor substrate wafer with an n- type high resistance layer 32 and a p<+> type drain layer 40 selectively formed onto the surface of the layer 32, and an n'' type source diffusion layer 34 is formed into the base diffusion layer 33. In a lateral type conductivity modulation type MOSFET, a gate electrode 36 is shaped onto a the base diffusion layer 33 as a channel region held by the source diffusion layer 34 and the high resistance layer 32 through a gate insulating film 35, and a source electrode 37 brought into contact with both the source diffusion layer 34 and the base diffusion layer 33 is formed. An opening section exposed onto the wafer surface of the high resistance layer 32 is formed in an insular shape completely surrounded by the base diffusion layer 33, and the drain layer 40 is shaped selectively to the surface of a p<+> type diffusion layer 39 formed on the surface of the high resistance layer 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral conductivity modulation type MOS.
Regarding FET.

[0002]

2. Description of the Related Art A conductivity modulation type MOSFET is a power MOSFET in which a drain region has a conductivity type opposite to that of a source region. Conventional conductivity modulation type MOSFET
The structure of is shown in FIG. 41 is a p ⁺ drain layer, 42 is n
^{It is a −} type high resistance layer, and a p type base diffusion layer 43 is formed on the surface of the high resistance layer 42, and an n ⁺ type source diffusion layer 44 is further formed in the p type base diffusion layer 43. The portion of the p-type base layer 43 sandwiched between the source diffusion layer 44 and the high resistance layer 42 exposed on the surface is formed into the channel region 4.
9, a gate electrode 46 is disposed on the gate insulating film 45, and a source electrode 47 that contacts both the source diffusion layer 44 and the base diffusion layer 43 is formed thereon. A drain electrode 48 is formed on the surface of the drain layer 48.

In this conductivity modulation type MOSFET, when a positive voltage is applied to the gate electrode 46 with respect to the source electrode 47, an inversion layer is formed in the channel region 49, and electrons from the source diffusion layer 44 pass through the channel region 49. Are implanted into the n ⁻ type high resistance layer 42. The injected electrons diffuse through the high resistance layer 42 and escape to the drain electrode 48, but at this time, injection of holes from the drain layer 41 is caused. By the injection of the holes, conductivity modulation occurs in the high resistance layer 42 due to the accumulation of carriers, and the resistance of the high resistance layer 42 decreases.
As a result, a MOSFET having an ON resistance lower than that of a normal power MOSFET can be obtained.

By the way, such a conductive modulation type MOSFET
Then, the p ⁺ type drain layer 41-n ⁻ type high resistance layer 42-p
The four layers of the type base diffusion layer 43-n ⁺ type source diffusion layer 44 form a thyristor. When this parasitic thyristor becomes conductive, the element cannot be turned off even if the voltage between the gate and the source becomes zero, and in many cases, the element is destroyed. The reason why the parasitic thyristor is turned on is that the holes injected from the p ⁺ type drain layer 41 pass through the p type base diffusion layer 43 when passing out to the source electrode 47. That is, when such a hole current flows and the voltage drop due to the resistance directly below the source diffusion layer 44 of the base diffusion layer 43 exceeds the built-in voltage between the base and the source, electron injection from the source layer 44 occurs, and the parasitic thyristor. Turns on.

In order to prevent such a latching phenomenon of the parasitic thyristor, a high concentration p ⁺ -type base diffusion layer 50 is formed in the p-type base diffusion layer 43 as shown in FIG. Is being lowered. However, even with this configuration, the conventional conductivity modulation type MOSFET
However, there is a problem that only a current of about 200 A / cm ² can be turned off at most. As a result of pursuing the fundamental reason, it has been clarified that the conventional conductive modulation type MOSFET uses the same source / gate pattern as the normal power MOSFET. This point will be described in detail below.

FIG. 6 shows a diffusion layer pattern of the conductivity modulation type MOSFET of FIG. As shown in the figure, a plurality of p-type base diffusion layers 43 are formed in a hexagonal shape so as to be diffused, and a channel region 49 is formed in each peripheral portion. In a power MOSFET, such a pattern is
This was effective in increasing the gate area and decreasing the on-resistance. However, there is a demand that the parasitic thyristor should not be turned on.
In the SFET, such a pattern has the following inconveniences.

First, in order to prevent the parasitic thyristor operation, from the channel region 49 to the p ⁺ type base diffusion layer 50.
It is desirable that the resistance to the opening is as small as possible. However, in the pattern of FIG. 6, the contact between the p ⁺ -type base diffusion layer 50 and the source electrode is p-type base diffusion layer 4.
3 has a peripheral length smaller than that of the channel region 49 around the p-type base diffusion layer 43, and its permeation resistance causes the channel region 49 and p
The resistance between the source electrode of the ⁺ type base diffusion layer 50 and the contact cannot be sufficiently reduced.

Secondly, in the pattern of FIG. 6, the thyristor operation is caused when the width L _{G of} the opening portion of the n ⁻ type high resistance layer 42 exposed on the substrate wafer surface, that is, the portion where the gate electrode is arranged is large. It has been clarified by the study of the present inventors that it is easy to do.

The fact that the drain current during latching of the parasitic thyristor is inversely proportional to L _G is shown as follows. Since a current flows substantially uniformly under the gate insulating film and flows into the p-type base layer, the next current I _P flows under the gate insulating film having a unit width of the channel region 49.

I _P = S _G · J _P / T (1) Here, J _P is the hole current density, S _G is the area of the n ⁻ -type high resistance layer opening per unit area, and T is the unit. P per area
The perimeter of the mold base diffusion layer. When this current flows into the base diffusion layer under the source diffusion layer and the voltage drop due to the resistance R _B under the source diffusion layer becomes higher than the built-in voltage Vbi between the base and the source, the parasitic thyristor turns on. Denoting this formula, the _{Vbi = I P · R B /} T = S G · J P · R B / T ... (2). However, R _B is the resistance from the channel of the p-type base layer to the p ⁺ contact per unit perimeter. When this is solved for J _P , J _P = Vbi · T / (S _G · R _B ) ... (3) At turn-off, the channel inversion layer disappears,
Since it becomes almost a hole current, the latching current density J _L
Is J _L = Vbi · T / (S _G · R _B ) ... (4) S _G / T is approximately L _G , and J _L is inversely proportional to L _G. This is also clear from FIG. 8 which is the experimental data of the present inventors. On the other hand, as shown in the perspective view of FIG.
_When the laminated structure of ₁ and the Al film 46 ₂ is used, the Al film 46 ₂
If the width is 30 μm, the width of the polycrystalline silicon film 46 ₁ needs to be 50 to 60 μm. That is, when the conventional pattern as shown in FIG. 6 is used, the width L _G of the opening of the n ⁻ type high resistance layer 42 needs to be 50 to 60 μm. This is the reason why the conventional conductive modulation type MOSFET cannot be effectively prevented from latching up.

[0011]

As described above, the conventional conductive modulation type MOSFET has a problem that it cannot prevent latch-up effectively. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a lateral conductivity modulation type MOSF in which latch-up is unlikely to occur.
To provide ET.

[0012]

In order to achieve the above object, a lateral conductivity modulation type MOSFET of the present invention comprises a high resistance layer of a first conductivity type and a high concentration selectively formed on the surface thereof. A second conductivity type base diffusion layer is selectively formed in the high resistance layer portion on the drain layer side of a semiconductor substrate wafer having a second conductivity type drain layer. A one-conductivity type source diffusion layer is selectively formed, and a gate electrode is formed on the base diffusion layer, which is a channel region sandwiched between the source diffusion layer and the high resistance layer, via a gate insulating film. In a lateral conductivity modulation type MOSFET in which a source electrode 37 that contacts both the source diffusion layer and the base diffusion layer is formed, an opening exposed on the wafer surface of the high resistance layer is completely surrounded by the base diffusion layer. None of the islands, and the high concentration the drain layer which is selectively formed on the surface of the high resistance layer,
It is characterized in that it is selectively formed on the surface of the diffusion layer of the first conductivity type.

[0013]

According to the present invention, contrary to the conventional pattern in which the portion of the high resistance layer exposed on the wafer surface surrounds the base diffusion layer, the island of the high resistance layer exposed on the wafer surface is surrounded by the base diffusion layer. The pattern is arranged in a shape.

If such a pattern is adopted, the area of the base layer resistance below the channel region and the area of the high resistance layer opening below the gate insulating film will be smaller than before, that is,
The value of S _G · R _B becomes smaller than before. On the other hand, T becomes larger than before.

Therefore, the value (current density J _L ) of the formula (4) found by the present inventors becomes larger than that of the conventional one, and the current density at which latch-up occurs becomes high, for example, up to 750 A / cm ² or more. It becomes possible to realize a lateral conductivity modulation type MOSFET which does not latch up.

Further, in the present invention, the drain layer is not directly formed on the surface of the high resistance layer, but is formed on the surface of the high-concentration, first conductivity type diffusion layer selectively formed on the surface of the high resistance layer. Since it is formed, it is possible to effectively suppress the expansion of the depletion layer that occurs in the forward element state, and it is possible to improve the breakdown voltage.

[0017]

Embodiments will be described below with reference to the drawings. FIG. 1 shows a lateral conductivity modulation type MO according to an embodiment of the present invention.
It is sectional drawing of SFET. In the figure, 31 denotes a p ⁺ -type layer, on the p ⁺ -type layer 31 is n ^- type high-resistance layer 32 is formed. The surface of the n ⁻ type high resistance layer 32 has p
The type base diffusion layer 33 is selectively formed, and the n ⁺ type source diffusion layer 3 is formed on the surface of the p type base diffusion layer 33.
4 are selectively formed.

[0018] Here, p-type base diffusion layer 33, n ^- diffusion pattern type high-resistance layer 32, p-type base diffusion layer 33 the n ^- pattern so as to surround the wafer opening type high-resistance layer 32 completely Has become.

On the p-type base diffusion layer 33, which becomes the channel region 38 sandwiched between the n ⁺ -type source diffusion layer 34 and the n ⁻ -type high resistance layer 32, a gate electrode 36 is arranged via a gate insulating film 35. The source electrode 37 is provided and is in contact with both the n ⁺ type source diffusion layer 34 and the p type base diffusion layer 33.

On the surface of the high resistance layer 32, an n-type layer 39 having a higher concentration than that is selectively formed, and a p ⁺ -type drain layer 40 is selectively formed on the surface thereof. The drain electrode 30 is disposed on the p ⁺ type drain layer 40. By providing the n-type layer 39, it is possible to suppress the expansion of the depletion layer that occurs when the lateral conductivity modulation type MOSFET is in the forward blocking state, so that the breakdown voltage is improved and the wafer opening of the high resistance layer 32 is formed. Part width L
_DS can be reduced.

FIG. 2 shows the lateral conductivity modulation type MOSFET of FIG.
An example of a diffusion layer pattern viewed from above is shown. A- in FIG.
The A ′ sectional view is as shown in FIG. As described above, the p-type base diffusion layer 33 has a pattern that completely surrounds the wafer opening of the n ⁻ -type high resistance layer 32, and this is a feature of this embodiment.

[0022] That is, according to this embodiment, in (4), the circumferential length T of the p-type base diffusion layer 33 per unit area, the conventional structure (n shown in FIG. 4 ^- the type high-resistance layer 32 p Pattern that completely surrounds the wafer opening of the mold base diffusion layer 33), while S _G ·
Since the value of R _B becomes smaller than that of the conventional one, the value of the current density J _L becomes larger than that of the conventional one (for example, 750 A / cm ²
that's all). Therefore, according to this embodiment, it is possible to realize a lateral conduction modulation type MOSFET in which latch-up is less likely to occur than in the conventional case.

Further, in this embodiment, the gate insulating film 35 is formed beyond the p-type base diffusion layer 33 below the gate electrode 36 to the n ⁻ -type high resistance layer 32 in the opening. Therefore, the inversion layer is also formed on the surface of the n ⁻ -type high resistance layer 32, and the electron injection efficiency is increased accordingly, and the turn-on characteristic is improved.

Furthermore, according to the present embodiment, the current value at which latch-up occurs can be increased, so that this current value can be made higher than the saturation current value of the element, so that latch-up is substantially achieved. Horizontal conductivity modulation type MO that does not occur
SFET can be realized.

The present invention is not limited to the above embodiment. For example, the p ⁺ -type layer 31 in FIG. 1 can be an N ⁺ -type layer. Further, the p ⁺ -type layer 31 and the electrode provided thereon (the portion shown by the diagonal lines below the p ⁺ -type layer 31 in FIG. 1) are not always necessary.

The above-mentioned electrode of the p ⁺ -type layer 31 may be used as a source electrode or a drain electrode.
Since the depletion layer extending downward from the type base diffusion layer 33 and the depletion layer extending upward from the p ⁺ type layer 31 are formed, the effect of improving the breakdown voltage can be obtained.

The pattern of each diffusion layer may be such that the inner diffusion layer is surrounded by the outer diffusion layer. In addition, p in FIG.
Similar to the ⁺ type base diffusion layer 50, a high concentration and deep base diffusion layer may be formed below the source electrode 37.

In the actual device manufacturing, for example, a high-resistance p-type Si substrate is used as a starting substrate and a wafer on which an n ⁻ -type high resistance layer 32 is epitaxially grown is used. You may perform sequentially. Of course, the n ⁻ type high resistance layer 32 may be used as the starting substrate.

[0029]

As described in detail above, according to the present invention, lateral conductivity modulation type MO in which latch-up is less likely to occur than in the past.
SFET can be realized. Further, according to the present invention, since the current value at which latch-up occurs can be increased, it becomes possible to make this current value larger than the saturation current value of the element, so that the lateral conductivity in which latch-up does not substantially occur. A modulation type MOSFET can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of the lateral conductivity modulation type MOSFET of FIG.

FIG. 2 is a diagram showing an example of a diffusion layer pattern of the lateral conductivity modulation type MOSFET of FIG.

FIG. 3 is a diagram showing a diffusion layer pattern of a conventional lateral conductivity modulation type MOSFET.

FIG. 4 is a sectional view of a conventional conductivity modulation type MOSFET.

FIG. 5 is a sectional view of another conventional conductive modulation type MOSFET.

FIG. 6 is a diagram showing a diffusion layer pattern of a conventional conductivity modulation type MOSFET.

FIG. 7 is a perspective view of a conventional conductivity modulation type MOSFET.

FIG. 8: Experimental data showing latching characteristics

[Explanation of symbols]

30 ... Drain electrode 31 ... P ⁺ type layer 32 ... N ^- type high resistance layer 33 ... P type base diffusion layer 34 ... N ⁺ type source diffusion layer 35 ... Gate insulating film 36 ... Gate electrode 37 ... Source electrode 38 ... Channel region 39 ... High-concentration n-type layer 40 ... p ⁺ -type drain layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiromichi Ohashi No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research Laboratories

Claims (1)

[Claims] 1. A high resistance layer on the side of the drain layer of a semiconductor substrate wafer having a first conductivity type high resistance layer and a high-concentration, second conductivity type drain layer selectively formed on the surface thereof. A second conductive type base diffusion layer is selectively formed in the portion, and a high-concentration, first conductive type source diffusion layer is selectively formed in the base diffusion layer, and the source diffusion layer and the high resistance layer are formed. A lateral conductive modulation in which a gate electrode is formed via a gate insulating film on the base diffusion layer serving as a channel region sandwiched between the source diffusion layer and a source electrode 37 contacting both the source diffusion layer and the base diffusion layer. Type MOSF
In ET, the opening exposed on the wafer surface of the high resistance layer has an island shape that is completely surrounded by the base diffusion layer, and the drain layer is formed on the surface of the high resistance layer by a high-pressure layer. A lateral conductivity modulation type MOSFET characterized by being selectively formed on the surface of a diffusion layer of the first conductivity type in concentration.