JPS584829B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to an electrode structure of a lateral type thyristor or transistor with increased device breakdown voltage.

A lateral type semiconductor device is a pn that constitutes a semiconductor device.
A semiconductor device in which all of the junctions terminate on one main surface of a semiconductor substrate, each electrode is in ohmic contact with this main surface, and the main current flows laterally.

The thyristor is constructed in an n-type conductive trench crystal island region of one of the insulating isolation substrates.

First, p-type impurities are diffused into two regions, PE region, P
Form B area.

Furthermore, an n-type impurity is diffused into the PB region to form an NE region.

If the region where impurities are not diffused is defined as the NB region, then P
A lateral type thyristor is composed of four layers: E-NB-PB-NE.

The PE region has an anode electrode, the P region has a gate electrode, and the N
Each cathode electrode is in ohmic contact with the E region.

When a forward voltage is applied with the anode electrode being positive and the cathode electrode being negative, it is the pn junction J2 formed by the NE region and the PB region that determines the breakdown voltage of the semiconductor element, with the cathode electrode being positive and the anode electrode being negative. When a negative reverse voltage is applied, the PE region and NB determine the breakdown voltage of the semiconductor element.
This is a pn junction J1 formed by the region.

More specifically, it is determined by the space charge regions formed on both sides of both junctions.

In a lateral type semiconductor device, the pn junction has a Brehner structure, so the breakdown voltage is determined by comparing the surface stabilization effect at the junction termination and the electric field concentration relaxation effect inside the semiconductor device, whichever is smaller.

In order to increase the effect of mitigating electric field concentration inside, it is possible to increase the radius of curvature of the pn junction by diffusing the impurity deeply, but in that case, the impurity will also diffuse laterally during the diffusion process, making it unnecessary. However, the disadvantage is that the area of the semiconductor element becomes large.

Therefore, an object of the present invention is to provide a high breakdown voltage semiconductor integrated circuit without deep diffusion.

In order to achieve the above object, in the present invention, an electrode that is in ohmic contact with each region constituting a semiconductor element in which a pn junction adopts a planar structure is placed over a region adjacent to the region where the electrode is provided, via a dielectric film. At the part where the two electrodes extend over the termination of the pn junction which determines the withstand voltage of the semiconductor element, a slight gap between the two electrodes is extended diagonally with respect to the termination part of the pn junction, Moreover, it is characterized in that its width is kept approximately constant.

Hereinafter, the present invention will be explained according to embodiments shown in the drawings.

1 and 2, a dielectric insulating isolation substrate 1 has a structure in which a single crystal semiconductor island region 4 is supported in a polycrystalline semiconductor support region 2 via a dielectric SiO2 film 3.

The reed region 4 has n-type conductivity, and p-type impurities are diffused into two regions, one being a P region 5 and the other being a PB region 6, and the n-type impurity is further diffused into the PB region 6 to form an NE region 7. shall be.

Assuming that the n-type region in which both p- and n-type impurities are not diffused is the NB region 8, each region of PE, NB, PB, and NE 5
~8 constitute a lateral type thyristor.

The pn junctions J1 to J3 formed adjacent to each other by the regions PE and NB, NB and PB, and PB and NB all terminate on the main surface of the island region 4, and have a planar structure.

A dielectric film of Si for surface stabilization is formed on the upper surface of the substrate 1.
02 film 9 is provided.

A window is opened in the Si02 film 9 on each region 5 to 7 of PF, PB, and NE, and from there, each electrode 10 to 12 of anode, gate, and cathode is ohmic (low resistance) to each region 5 to 7.
are in contact.

In FIG. 1, areas in ohmic contact are shown by hatching.

Here, the anode electrode 10 is made of N through the Si02 film 9.
It is provided so as to extend over the B area 8.

Further, the gate electrode 11 is formed to extend over the NB region 8 via the SiO2 film 9, and the cathode electrode 12 is formed as an S
Although it is provided so as to extend over the PR region 6 and NB region 8 via the iO2 film 9, there is a slight gap 13 between the gate electrode 11 and the cathode electrode 12 because it is necessary to electrically insulate them. is provided.

Furthermore, the slight gap 13 between the gate electrode 11 and the cathode electrode 12 on the region near the pn junction J2 in the NB region 6 has a certain inclination and is approximately parallel to the terminating portion of the pn junction J2. It is set up so that

Next, the principle of the present invention will be explained.

Since the thyristor constructed in a semiconductor integrated circuit is too small, by connecting a resistor between the gate and canode electrodes 11 and 12, the anode and cathode electrodes 10
, 12, a displacement current flows through the pn junction J2 due to a steep rising pulse, which suppresses the rate effect of erroneous firing and improves the dv/dt tolerance.

When a voltage is applied between the anode electrode 10 and the cathode electrode 12, the potential of the P region 6 is
The potential is the same as that of the NE region 7 due to the resistor connected between 1 and 12.

As a result, the anode electrode 10 is changed to the positive potential cathode electrode 12.
When a voltage with a negative potential of The area in the NB region 8 extends to the areas where both the gate and cathode electrodes 11 and 12 extend.

Furthermore, when a voltage is applied that makes the anode electrode 10 a negative potential and the cathode electrode 12 a positive potential, the space charge region generated on both sides of the pn junction J1 in the NB region 8 is caused by the electric field effect of the anode electrode 10. Anode electrode 1
It extends to the part where 0 extends.

By expanding the space charge region, the electric field within the space charge region is weakened and the avalanche breakdown voltage is increased.

Therefore, the breakdown voltage of the semiconductor element becomes high. By the way, pn
The entire portion of the junction J1 that terminates on the main surface is covered with the anode electrode 10 extending through the SiO2 film, but a portion of the portion that terminates on the main surface of the p-n junction J2 includes: A slight gap 13 exists.

This is because it is necessary to electrically insulate the gate electrode 11 and cathode electrode 12 from each other from the PB region 6 and N region 7, and in this small gap 13, the space charge region does not expand, and the breakdown voltage of the pn It becomes lower than junction J1.

Therefore, in the present invention, as in the embodiment shown in FIG.
The slight gap 13 on the main surface of region B 6 is provided so that its width is substantially constant and has a constant slope with respect to the portion terminating on the main surface of pn junction J2.

FIG. 3 shows a case in which the slight gap 13 is provided perpendicularly to the portion terminating on the main surface of the p-n junction J2 (FIG. 3a), and a case in which it is provided with a constant inclination as in the embodiment of the present invention. FIG. 3 is an enlarged view showing the spread of the space charge region 14 in the case (FIG. 3b).

In FIG. 3a, the space charge region 14 in the part of the small gap 13
However, in the example of the present invention shown in FIG. It is expanded compared to Figure 3a.

Therefore, according to this embodiment, even if a small gap 13 is provided between the gate electrode 11 and the cathode electrode 12, the space charge region 14 in the small gap 13 is sufficiently extended, and the breakdown voltage of the semiconductor device is sufficiently improved. can be done.

The present invention is applicable not only to the thyristors mentioned in the embodiments but also to transistors and the like.

Furthermore, the insulating separation substrate is not limited to a dielectric separation type, but can also be applied to a pn junction separation type.

As described above, according to the present invention, a semiconductor integrated circuit with high breakdown voltage can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor integrated circuit showing an embodiment of the present invention, FIG. 2 is a longitudinal cross-sectional view taken along the cutting line
FIG. 3 is an enlarged view showing the spread of the space charge region of the embodiment shown in FIG. 1. FIG. 5... PE region, 6... PR region, 7... N region, 8... N region, 9... dielectric film, 10...
Anode electrode, 11... Gate electrode, 12... Cathode electrode, 13... Slight gap, 14... Space charge region.

Claims (1)

[Claims] 1 has a pair of main surfaces, a first region of a first conductivity type exposed on one of the main surfaces, and a first pn junction formed between the first region and the first region. a second region of a second conductivity type formed within the first region so as to terminate on one main surface; a second region formed between the second region and the second region;
a third region of the first conductivity type formed in the second region such that the pn junction terminates on the one main surface; 2
a first electrode formed in low resistance contact with the region and extending at least over the first region via a dielectric film; a second region formed so as to be in low resistance contact with the first region and to extend over the first region beyond the second region via a dielectric film.
one of the first electrode and the second electrode extends over the first pn junction termination portion via a dielectric film so as to substantially surround the other; The first electrode and the second electrode are connected to the first pn in the first region from above the tenth pn junction termination portion to adjacent thereto.
1. A semiconductor integrated circuit, wherein each opposing surface has a certain inclination with the first pn junction termination portion on a region near the junction, and faces the first pn junction terminal portion with a slight gap therebetween.