JPH0332234B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a field effect transistor device for controlling and switching electrical signals, particularly analog signals, and more specifically, the present invention relates to a field effect transistor device for controlling and switching electrical signals, particularly analog signals. It concerns the design geometry and other important characteristics of transistor elements.

Field effect transistors have certain properties that make them attractive for switching analog signals. One of those properties is that no matter what the voltage polarity is, this field effect transistor has the same output characteristics to perform the switching of the alternating current signal; The field effect transistor can be made a bilateral device so that designated source and drain regions of the field effect transistor can be operated at any given point. Second, the source-drain voltage-current characteristic of a field-effect transistor operated with a common source has an offset, similar to the collector voltage-current characteristic of a bipolar transistor operated with a common emitter. There is no voltage.

However, the use of field-effect transistors as analog switches is problematic because the conduction resistance between their drain and source is typically much higher than, for example, the output resistance of a bipolar transistor. . The drain-source resistance, that is, the channel region resistance during such conduction adversely affects the switching operation.
One of its negative effects is that its conduction resistance increases the power consumption that occurs when the transistor is conductive, which is particularly problematic when field effect transistors are used as power devices that conduct a sufficiently large current when conductive. A second adverse effect is that this conduction resistance reduces the switching speed of the field effect transistor and load combination, reducing the usefulness of the switch for controlling rapidly changing analog signals.

In the case of a field effect transistor formed in a semiconductor substrate as shown in FIG. is known to be related to the size of the transistor. The dimensions of the transistor are then particularly related to the effective width and effective length of the field effect transistor in the semiconductor material used. That is, the resistance value of the channel resistance when a field effect transistor is conductive is related to the effective length of the channel between its drain and source, and the effective width of the channel. The following relationship exists between the resistance value R _po of the drain-source resistance when the field effect transistor is conducting, the effective length L of the channel between the drain and the source, and the effective width W. It has been discovered.

R _po ∝L/W where the punch-through voltage and switching time parameters are determined by the channel length;
It is also known that the shorter the length L of the channel, the lower the punch-through voltage and the shorter the switching time. Therefore, the resistance value
While widening the channel width W to the extent necessary to lower _Rpo satisfactorily,
It may be concluded that the channel length L of the strip transistor shown in Figure A should be made as short as practically possible. That is, keeping the channel length as short as possible while following the component placement rules required by the transistor's manufacturing method and maintaining an adequate minimum punch-through voltage for operation in the non-conducting state, and then The width of the channel is widened until the resistance between the drain and source reaches a satisfactory value during conduction. An example of the structure of a field effect transistor made in this manner is shown in FIG. 1B.

In the structure shown in FIGS. 1A and 1B, the source region 10 is located below the flat major surface of the semiconductor body.
It is formed to intersect with its main surface. This major surface supports the insulating layer above it. The source area is symbol S
It is also shown by. A contact to the source 10 is inserted into the hole 11 provided in the insulating layer. This contact is shown in FIG. 1A as being made by an external interconnect element 12.
However, because source region 10 can extend to other regions in the semiconductor body and interconnect itself, no external connector is required. 1st
Diagram B does not show such interconnections;
The source 10 is shown extending indefinitely until it reaches a certain value of W that provides a suitably low conducting channel resistance. 1st B
In the figure, area 11 is for containing external interconnection elements.
is shown between the solid lines.

A drain region 13 is shown in FIGS. 1A and 1B, and is also designated by the symbol D. For example external interconnection element 1
A hole 14 is provided for connecting 5 to the source 13. FIG. 1B also shows the drain region 13 extending indefinitely until a channel width is obtained that yields a sufficiently low R _po .

A gate structure 16 is shown between source region 10 and drain region 13 in FIGS. 1A and 1B. This gate structure section 16 is
In the case of a MOSFET, the gate conductor is separated from the source and drain regions by an insulating layer.
In the case of a JFET, it is part of an interconnect element for electrically connecting to a gate region provided in the JFET.

FIG. 1B therefore illustrates a possible method for increasing the channel width W to the extent necessary to reduce the conduction channel resistance. However, such structures have high resistance due to long gate leads and possibly long source and drain leads.
This results in longer switching times and increased power losses, making field effect transistors of such structure questionable in their effectiveness when used as analog signal switches. Furthermore, when such a structure is fabricated into a monolithic integrated circuit, the structure occupies a large area on the main plane, which is not an optimal use of area.

Using such a large area on the main surface of a monolithic integrated circuit is an expensive practice. The number of operational integrated circuit chips that can be obtained from a given method of making a monolithic integrated circuit is
It is inversely proportional to the area of the major surface occupied by the monolithic integrated circuit. Therefore, the price of a good monolithic integrated circuit chip is inversely proportional to the product of the number of those chips made on a wafer and the yield, so the price of an integrated circuit is proportional to the square of the area occupied by the main surface of the monolithic integrated circuit chip. It will be proportional.

Therefore, when considering the manufacture of monolithic integrated circuits, it is extremely important to minimize the area occupied by the main surface of the chip. When fabricating a field effect transistor on the main surface of a monolithic integrated circuit chip, minimizing the area occupied by the main surface for a given channel resistance when conducting is the same as the channel resistance when conducting and the area occupied by the transistor. It is equivalent to minimizing the product R _po A with the area. This is because the product R _po A ultimately determines the area of the major surface of the monolithic integrated circuit chip required to make the field effect transistor. By minimizing the surface area of the field effect device used for a given conduction channel resistance value, the area of the gate over the channel region is also minimized. Therefore, the resistance value and capacitance value of the gate resistor become small, and the switching speed becomes high.

FIG. 1C shows another method of effectively increasing the width of the channel while keeping the length of the channel as short as possible. That is, instead of having one long source, one long drain, and one long gate, there are multiple sources, multiple drains, and multiple gates repeated in a strip pattern. This is essentially the same as dividing the structure shown in FIG. 1B into several parts and placing the divided parts side by side.

R _po A achieved by the structure shown in Figure 1C
Another geometry for reducing the R _po product above the product reduction value is shown in US Pat. No. 3,783,349. This U.S. patent discloses that a source region and a drain region separated by several surfaces within the main plane of a semiconductor are arranged in a rectangular or square shape, and a gate region is combined with these regions to form a combination of straight lines perpendicular to each other. A lattice-like or rectangular network structure is disclosed having source and drain regions along the intersections or centers of a lattice-like pattern formed by the above. A portion of the pattern disclosed in said US patent is shown in FIG.

In FIG. 2, the source region intersecting the surface of the semiconductor body is designated by the symbol S and the number 10, the drain region on the semiconductor body is designated by the symbol D and the number 13, and the part associated with the gate region is designated by the symbol G. number 1
6. The source and drain regions are surrounded by dashed lines. It is assumed that the device shown in FIG. 2 has an insulating layer coated on a semiconductor substrate. Interconnect elements for the source and drain are not shown. Portions of the source region and the drain region that are electrically connected are indicated by solid line openings 11 and 14.

Another structure for this purpose is described in U.S. Patent No.
No. 4015278. In the structure shown in this US patent, the source is made in a Y shape and the drain is made in a hexagonal shape.

These structures of field effect transistors are the first A
It appears to be much more effective at reducing the R _po A product than the structures shown in Figures and Figure 1B. However, it is highly desirable to further reduce the R _po A product, especially when field effect transistors are fabricated in monolithic integrated circuits.
Moreover, it is most desirable to further reduce the _RpoA product if large currents can be controlled without overheating the monolithic integrated circuit chip.

Another consideration when switching analog signals with field effect transistors is that they must be able to withstand sufficiently high reverse bias voltages. That is, the minimum punch-through voltage and minimum breakdown voltage of this field effect transistor must be sufficient. However, this is difficult to achieve, especially for devices made of monolithic integrated circuits.

According to the present invention, a field effect transistor element that can withstand a sufficiently high reverse bias voltage can be obtained by providing a shield electrode near one or both of the semiconductor source or drain regions. . In this way, the source and drain regions of the semiconductor can become heavily depleted before breaking down when reverse bias is applied, or
Dopant concentrations occur that alter the electric field within this depletion region. Such a shield electrode is connected to the gate electrode of a field effect transistor element in some examples. Also, the portion of this field effect transistor element associated with the gate region serves to separate the triangular regions created within the densely packed matrix structure.
The channel resistance value in the conductive state can be lowered. A method of making a field effect transistor device having both a gate region and a shield region within a field effect transistor is disclosed, providing that the regions are self-aligned at various portions of the source and drain regions.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

The effect of the structure and arrangement of the source and drain regions of the present invention, which is aimed at reducing the R _po A product of field effect transistors compared to conventional structures, is that the possible geometries are generally This can be shown by the mathematical model shown below. By working with the model we can find better geometries. This understanding and treatment of the problem of field effect transistor construction for devices suitable for handling large amounts of power in monolithic integrated circuits or other compact structures has not been done in the prior art and is However, no results have been found in the prior art.

The problem of minimizing the R _po A product of a surface field effect transistor is very similar to the problem of drawing a two-dimensional figure on a plane with high density. The reason is that the surface field effect transistor formed on the main surface of the semiconductor substrate is almost a secondary element element. In other words, the problem is to minimize the area occupied by the field effect transistor geometry in the main plane of the semiconductor body containing the device, given a certain conducting channel resistance value that must not be exceeded. I can say it.

As mentioned above, increasing the switching speed and
In order to make the channel resistance value in the conductive state as low as possible, the effective channel length L must be made as short as possible. Of course, the final value of L selected satisfies the layout design rules for minimum spacing required by the method used to make the field effect device, and is determined when the device is in the non-conducting state. Determined by the structure that satisfies the minimum punch-through voltage. Therefore, the value of L cannot be changed for the purpose of narrowing the area of the device, but the effective channel width W can be changed as described above. In this situation, the element's R _po A
The problem of reducing the product can be rephrased as selecting the effective channel width necessary to obtain a satisfactorily low conducting channel resistance, and then minimizing the area of the resulting field effect transistor element. be able to. Of course, the effective channel width W follows the same construction and layout rules determined by the manufacturing method described for channel length.

The arrangements shown in Figures 1A, 1B, and 1C are based only on the lowest two-dimensional point symmetry group in two-dimensional lattice geometry group theory. The geometry shown in Figure 2 is based on a higher order point symmetry group, namely the four-fold rotational symmetry.
symmetry).

However, from group theory, the solution to the above problem is point group 2,
4mm, 6mm and 2mm (i.e. 1, 2, 3,
It is a geometric figure with 4- and 6-fold rotational symmetry). Since the surface-related field effect transistor elements have a two-fold rotational symmetry themselves, only groups that can be decomposed into two-fold and n-fold rotational axes are practical solutions to this problem. Therefore, 2 for this problem
Not only arrangements with satisfactory solutions for rotational and 4-fold rotational symmetry, but also arrangements with 6-fold rotational symmetry represent solutions for suitable and densely packed element structures. In reality, one layer of metal is 2
Since they always have a rotational symmetry of 1 or less, their arrangement should be rectangular in the case of 4-fold rotational symmetry, as shown for the element part in FIG. 2, and as shown in FIG. 3A. In the case of six-fold rotational symmetry, the structure must be triangular.

The device portion shown in FIG. 3A also has source and drain regions formed across the surface of the semiconductor substrate. Those areas are indicated by dashed lines. The main surface of this semiconductor body supports an insulating layer. By intersecting the source and drain regions with the major surface, densely packed triangular surface portions are provided within the major surface. Although these triangular surface portions are shown as equilateral triangles in FIG. 3A, they do not necessarily have to be equilateral triangles. The small solid triangles are for making electrical connections to the source and drain regions, each electrical connection being made by a source interconnection element and a drain interconnection element.

A long dashed line extending along the separation surface between the source triangular surface portion and the drain triangular surface portion and forming a network in which the mesh is triangular and is associated with the gate is used for each triangle representing the source or drain. Construct a large triangle around the shape surface area. These large triangles include gate meshes associated with source and drain triangular surface portions. Considering these large triangular surface areas in relation to each other, the large triangles (shown here as equilateral triangles) reveal a six-fold rotational symmetry in a densely packed hexagonal matrix structure. . Similarly,
In FIG. 2 as well, long dashed lines are added to form a large quadrilateral (actually a square) within a rectangular or square mesh. Their large square sections reveal a four-fold rotational symmetry in the formation of densely packed square matrix structures.

The above group theoretical solution
R _po A for each configuration to determine the relative merits of various possible configurations within
The product must be evaluated. To this end, it is assumed that each field effect transistor associated with the arrangement being evaluated is operating in the linear region, where the drain-source voltage V _DS is of small value. MOSFET
For example, the well-known formula for finding the conducting channel resistance for R _po = L _eff / W _eff μC _px (V _GS − V _T ) The meaning is as follows.

R _po △ = Channel resistance value in conduction state L△ = Channel length W _eff △ = Effective channel width C _px △ = Capacitance per unit area of gate-oxide capacitor μ△ = Mobility of channel carrier V _GS △ = Gate-source voltage V _T △ = Threshold voltage To continue the analysis, we consider each of the configurations shown in Figures 1C, 2, and 3A, which represent the configuration solutions found within the scope of the group theory described above. By first substituting the value obtained from the unit cell in W _eff in the previous equation, R _po A
Find the product. Each unit cell shown in these three figures represents an elementary cell of the relevant minimum size for each configuration determined by the group theory used. The task of calculating the R _po A product for each arrangement shown in Figures 1C, 2, and 3A is as follows:
Finish by substituting an appropriate value for W _eff and multiplying it by the area of the corresponding unit cell.

The equations below are for the geometries shown in Figures 1C, 2 and 3A.

(R _po A) 1C diagram = L (L + wc + 2d) / μC _px (V _GS −V _T
) (R _po A) 2 diagram = L (L + wc + 2d) ² / μC _px 2 (wc + 2d) (V _GS −V _T
) (R _po A) Figure 3A = 2(3) ^1/2 L {We/2(3)1/2+d+ ^L/ 2} ² /μ
C _px {w _c +2(3) ^1/2 d} (V _GS −V _T ) In these equations, w _c is the electrical charge performed by the interconnect element on each main surface portion of the source and drain regions. The contact width, d, is the minimum required spacing between the edge of the channel and the electrical contact in each major surface portion of the source and drain regions. .

For each arrangement shown in Figures 1C, 2 and 3A.
The meanings of the above three formulas for calculating the R _po A product are:
When a defined parameter representing the effective channel region width per source or drain region w _c +2d is varied with respect to the effective channel length L,
This can be determined by comparing the values of the expressions. In the limit, when the channel width is much larger than the channel length, ie when w _c +2d≫L, the R _po A product represents the vertical centerline grid of FIG. (R _po A) Figure 2 shows w _c , d,
The R _po A product of the repeating band configuration shown in Figure 1C for the same value of L, ie (R _po A) approaches half of Figure 1C. On the other hand, the R _po A product for the triangular network shown in Figure 3A is (R _po A) 3
Figure A shows the improvement achieved by the present invention, and shows a 1/3 of the repeating band arrangement shown in Figure 1C.
It is. In other words, the results shown below are obtained with the desired condition of using the shortest possible channel length.

(R _po A) Figure 2 → 0.50 (R _po A) Figure 1C, w _c +2d≫L (R _po A) Figure 3A → 0.33 (R _po A) Figure 1C, w _c +2d≫L For these same equations Therefore, when w _c +2d is approximately equal to L, the R _po A products for the three configurations shown in Figures 1C, 2, and 3A are approximately equal.
Finally, when w _c +2d is much smaller than L,
It turns out that the arrangement shown in FIG. 1 exhibits the lowest R _po A product.

This relationship is shown in the graph of FIG. This graph shows the R _po A product as a function of channel length L for each of the configurations shown in FIGS. 1C, 2, and 3A. In this graph, R _po A product is the coefficient C _px
(V _GS -V _T ), and it is assumed that w _c =5 microns and d = 6 microns according to the placement rule. These equations give the results shown in Figure 4 that the triangular network structure, i.e., the densely packed hexagonal matrix structure of Figure 3A, becomes smaller when the channel length becomes relatively short. This means that it has a smaller R _po A product, and the one described above is the most desirable. This, of course, depends on the dimensions of the source and drain regions being chosen to be no larger than a reasonable size, sufficient to meet the limitations of manufacturing methods commonly used in the manufacture of monolithic integrated circuits. Then the above situation is achieved.

Of course, since the layout rules for monolithic integrated circuits for minimizing spacing tend to specify the relative minimum dimensions of each unit cell in each layout shown in Figures 1C, 2, and 3A, For a given one of these symmetric group solutions to the problem of minimizing the R _po A product, a practical arrangement may not achieve the possibility of making the R _po product sufficiently small. Therefore, even if the relationship shown in the graph of Figure 4 exists, for example, the R _po A product of the four-fold rotationally symmetric group configuration shown in Figure 2 has a relatively short channel length. It may actually be smaller than the R _po A product of the 6-fold rotationally symmetric group structure shown in FIG. 3A even for . Therefore, before selecting the solution mentioned above, one must always check the relative results of any of these solutions by means of a mock test structure or an actual test structure.

For example, the above analysis of the configurations shown in Figures 1C, 2, and 3A is based on the assumption that interconnect elements for electrically connecting the source and drain regions can be ignored in the analysis. I used to stand there. However, if this is not the case, i.e., if one arrangement, as opposed to another, requires the minimum spacing law to have interconnect elements with relatively thin leads, then a relatively high resistance is required for the interconnect elements. value will be introduced. The relative merits of the two arrangements, such as those shown in Figures 2 and 3A, are then:
The advantages concluded in the analysis conducted above may be completely contrary. However, both in theory and in practice, the triangular mesh arrangement shown in FIG. 3A, for a given conducting channel resistance, It has been found that monolithic integrated circuits have a surface area that is smaller than that of a monolithic integrated circuit. in fact,
The resistance values of the interconnect elements can even be relatively lower in the triangular mesh arrangement shown in FIG. 3A than in the vertical centerline grid arrangement shown in FIG.

It was previously explained that cost is generally proportional to the area occupied by the main surface of a monolithic integrated circuit. FIG. 5 is a graph that takes the repeated strip arrangement shown in FIG. 1C as a standard cost and shows the relative costs of other arrangements using an index. It is noted that the choice of the lowest cost arrangement is clearly related to the length of the channel chosen in relation to a particular arrangement where the values of channel width _w and length d are fixed. sea bream. channel length
At 7.5 microns, the cost of the vertical centerline grid arrangement shown in Figure 2 can be expected to be about 50% of the cost of the repeating band arrangement shown in Figure 1C, and the cost of the triangular mesh arrangement shown in The cost can be expected to be 37% of the arrangement shown in Figure 1C.

Note that the cost analysis used in the formulas shown above does not take into account the layout rule that the resistance value of the interconnection path is actually relatively higher in some layouts than in other layouts. .

Another field-effect transistor made using a hexagonal matrix structure packed with high density is
Shown in Figure B. This device provides a low conduction channel resistance and a low resistance of the metallization extensions of the source and drain interconnect elements. Additionally, the metallization extensions shown in FIG. 3B may have at least some more metallization methods in the pattern shown in FIG. 3B than in the structural pattern shown in FIG. 3A. It can be easily provided by

In the structure shown in FIG. 3B, the triangular surface portion 10 of the source region corresponds to the triangular gate surface portion 1.
6 in a state consistent with that. The reticulated surface portion 13 of the drain region forms a reticulated pattern with triangular openings containing therein the source region surface portion and the drain region surface portion. In this way, the latter regions are closely spaced on the surface of the device shown in FIG. 3B, and they are provided below the passivation layer covering the device.

In FIG. 3B, the smallest solid triangle represents an opening in the insulating layer into which an electrical connection to the source region 10 is made by the source interconnect element. . The parallel solid lines indicate openings provided in the insulating layer in which the electrical connection to the drain region 13 by the drain interconnection elements is made. Another interconnect element layer is also required to interconnect gate region 16. The openings for making the interconnections are not shown in FIG. 3B.

To avoid the need for a separate interconnect element layer to electrically interconnect the separated gate regions shown in FIG. 3B, the structure of FIG. 3C connects the gate region to the source region in the semiconductor. It can be used to connect to the periphery, thereby forming multiple columns of connected gate regions. and,
If those columns are also connected in the semiconductor, there is a possibility to create one continuous gate region in the semiconductor, but if those columns cannot be connected in the semiconductor, the columns are connected to each other. No gate interconnections other than those required are required. Other than the interconnection of gate regions 16 in the semiconductor in FIG. 3C, the structure shown in this figure is substantially the same as the structure shown in FIG. 3B.

The regions shown in FIGS. 3B and 3C as a source region 10 having a triangular surface portion and a drain region 13 having a triangular surface portion, respectively, may be selected as regions 10 and 13 at will. be. That is, a region 13 labeled D and a region 13 labeled S are used so that the drain region 13 forms a triangular surface portion and the source region 10 forms a net-like surface portion surrounding the gate portion and the drain triangular surface portion. It is possible to replace the area 10 that is currently in use.

The structure shown in FIG. 3C will be selected for analysis. In this figure, unit cells of the same nature as the unit cells shown in Figures 1C, 2 and 3C are shown in the same way. The R _po A product for the configuration shown in FIG. 3C is given by:

(R _po A) 3C diagram = L {3L + 3d ₁ + 2d ₂ + (3) ^1/2 /2w _c1 +
w _c2 /μC _px 6 {2(3) ^1/2 L+2(3) ^1/2 d ₁ +w _c1 } (V _GS −
V _T ) × {2(3) ^1/2 L+2(3) ^1/2 d ₁ +w _c1 +4/(3) ^1/2 wd
} In this formula, L is the length across the gate region,
w _d represents the width across the arms of the drain region, w _c1 and w _c2 are the dimensions of the openings provided in the source region 10 and the drain region 13, respectively;
d ₁ and d ₂ each represent the remaining distance of the source and drain regions outside the associated connection opening.

Continuing the analysis of this equation, it can be seen that the performance of the structure shown in FIG. 3C is approximately equal to the performance of the structure shown in FIG. 3A with respect to the performance of the structure shown in FIG. 1C. Therefore, the performance of the densely packed hexagonal matrix structure shown in FIG. 3A is as follows:
The performance is almost equal to that of the structure shown in Figure 3C.

FIG. 6 is a top view of the field transistor device of the present invention (related to FIG. 3A) without a passivation layer provided over the source and drain interconnect elements. Triangular surface areas created by the intersection of several source and drain regions with the main surface of the semiconductor substrate are shown in FIG. shall not be construed as indicating the number of In actual devices, the number of these triangular surface portions is usually several thousand, and often exceeds 50,000.

The source interconnect element 12, which is typically made of aluminum, is designated with the symbol S. The drain interconnect element 15, which is also typically made of aluminum, is marked with the symbol D.

The gate connection opening 17 is marked with the symbol G. The extension extending from the gate connection opening 17 over the gate portion of the field effect transistor is numbered 16 and includes all of the rectangle drawn in dashed lines, but does not include the source region. In a JFET, where the upper portion of the triangular surface portion containing the drain region is substantially excluded, region 16 represents that portion of the semiconductor body of a conductivity type opposite that of the source and drain regions. In this case, such a method is used to minimize the gate resistance value.
A conductor can also be passed over and in contact with the gate region of the JFET.
In a MOSFET, region 16 represents the gate conductive material over the underlying insulating layer. The insulating layer is typically made of silicon dioxide and separates the semiconductor body and the gate conductive layer 16. In this case, region 16 is typically made of polysilicon or metal. Polysilicon is chosen for the most compact structures because it has a much lower risk of shorting the upper metal layer containing the source and drain interconnect elements, allowing tighter placement spacing rules. Ru. However, if metal is used for the gate 16, the resistance value of the lead will be lower, so if high-speed switching is the main purpose, the gate 16
metal is selected.

The triangular surface portion 10 within the main surface of the semiconductor substrate is
Because of the intersecting source regions shown below the silicon dioxide insulating layer, the symbol S that indicated the source regions in FIG. 1A is replaced by the surface portion 1 in FIG.
It is set to 0. Also, the triangular surface part 1
3 is marked with the symbol D used to indicate the drain region in FIG. 1A.

Another passivation layer, usually made of doped silicon dioxide, is provided over the structure shown in FIG. 6, but that layer is not shown in this case for clarity. Not yet.

Some of the elements shown in Figure 6 are MOSFETs.
FIG. 7 shows a case configured as follows. Holes 11, 14 are provided between the source and drain interconnection elements and the semiconductor body by removing the insulating layer for making electrical contacts to the source and drain regions.

FIG. 8 is a sectional view taken along line 18 in FIG. 7.
The structure shown in FIG. 8 is provided with a phosphosilicate glass patency layer 20 which is not present in the structures shown in FIGS. 6 and 7.
A silicon dioxide insulating layer 19 protects the gate and isolates it from the main surface of the semiconductor body.

An n-type drain region associated with the triangular surface portion 13 is provided by doping phosphorus into the semiconductor body 21 by diffusion or ion implantation to a concentration of approximately 10 ¹⁸ atoms/cm ² , and a source region associated with the surface portion 10 is provided. is also set up in the same way. The semiconductor substrate on the outside of these source and drain regions is doped with boron at a concentration of about 2×10 ¹⁵ atoms/cm ² to become p-type. The typical spacing between the source and drain regions is as described above.
It is 7.5 microns. In addition, the semiconductor base portion 21
and the gate is typically 1000 angstroms.

Certain MOS devices can be made in a slightly different manner than that shown in FIG. That is, in that case, the gate region 16 is provided as shown in FIG. 8, but the source region 10 and the drain region 13 are formed by doping polygons on the main surface of the semiconductor body in the immediate vicinity of the gate. Provided by adhering silicon. In this case, highly doped regions functioning as source and drain regions are not provided in the semiconductor body.

Figure 9 shows the JFET corresponding to Figures 6 and 7.
Show the structure. However, in the structure shown in FIG. 9, the semiconductor substrate 21 is formed on a p-type silicon substrate doped with boron at 5×10 ¹⁴ atoms/cm ² .
Represents an n-type silicon epitaxial layer doped with phosphorus to a concentration of 10 ¹⁵ atoms/cm ² . Layer 21 includes source and drain regions forming triangular surface portions on its major surface. The source and drain regions partially surround the gate region 16 such that they are continuous under the gate region 16, ie, the regions contact each other. Gate region 16 is formed by doping boron to a concentration of 10 ¹⁸ atoms/cm ² .

Another metal layer 23 is shown in dashed lines in FIG. 9 as a gate electrical contact deposited on the surface of gate region 16. This metal layer 23, which is in ohmic contact with the surface of the gate region 16, may be used to reduce gate resistance rather than using the gate region as the only gate interconnect element within the semiconductor body. can. If the region in layer 21 that functions as the gate region is eliminated, metal layer 23 in rectifying contact with layer 21 forms the gate region in the Schottky barrier field effect transistor device.

As explained earlier, a desirable field effect transistor device not only has a low channel resistance when conducting, but also has a high resistance between the actual drain and the actual source and between the actual drain and the substrate when non-conducting. It must be able to withstand such sufficiently high voltages, ie punch-through voltage and breakdown voltage. This is especially true in the case of field effect transistors used as switches or control elements in power circuits that handle sufficiently high voltages.

In order to be able to withstand sufficiently high punch-through voltages, the channel length of the device must, of course, be increased. However, in this case, the channel resistance value during conduction increases, the switching speed decreases, and the breakdown voltage of the pn junction between the drain and the substrate hardly increases. This breakdown voltage is influenced by the doping level in the source and drain regions and the geometry of those regions, which determines the contribution of the electric field generated by immobile charges to the breakdown. Regarding the geometry of the source and drain regions, the curvature of those regions can significantly increase the effective electric field for a given potential, thereby accelerating the onset of descent.

Further, by providing a gate region, the punch-through voltage and breakdown voltage may change significantly when the gate region is absent. The causes of such changes are injection of hot carriers into the gate insulating layer, concentration of surface electric lines of force due to the conductive gate,
Such as anamolous surface conduction under the gate.

FIG. 10 shows the structure of a MOS device that alleviates the problems of punch-through voltage and breakdown voltage. The elements shown in FIG. 10 are to be understood as representing cross-sections of individual MOS field effect transistor elements of a field effect transistor with multiple sources and multiple drains. Therefore, FIG.
7 is a somewhat wider variant of the cross-section 18 of FIG. 7 taken from a portion of the figure and associated with FIG. 3A. 1st
A passivation layer 20 is also provided in FIG.

However, in FIG. 10, the triangular surface portions 10, 1
The source and drain regions forming respectively 3 are no longer formed within the semiconductor body, but instead are formed at the surface of the semiconductor by deposition of doped polysilicon. As shown in Figure 10
The channel of MOS field effect transistor element is
The inversion that occurs in the semiconductor 21 below the gate 16 causes it to occur again in that semiconductor. This channel is formed between the source and drain created by depositing doped polysilicon.

The p-type silicon semiconductor substrate 21 is doped with boron atoms at a concentration of approximately 2×10 ¹⁵ atoms/cm ² . The main surface of this semiconductor substrate is usually 2×
A threshold voltage adjustment region 21' may be provided in which boron is added to a concentration of 10 ¹⁶ atoms/cm ² by ion implantation. This region 21' is for adjusting the threshold voltage of this field effect transistor. This threshold voltage adjustment region can also be provided in some of the previously described devices. The polysilicon source and drain regions forming the triangular surface portions 10 and 13, respectively, are
In a multiple source and multiple drain region device in a densely packed hexagonal matrix structure as shown in the figure), the phosphorus concentration is 10 ¹⁸ atoms/cm ²
It is rendered n-type by doping to a concentration of . Gate 16 can be comprised of doped polysilicon or metal. The thickness of the doped polysilicon drain and source regions is typically
0.3-0.4 microns, typically separated by 4 micron intervals. The length of the tapered portion of these regions is at least 1 micron along the surface of semiconductor body 21, but preferably 2 microns. The thickness of the silicon dioxide layer 19 is typically
It is 2000 angstroms. The values of other parameters are likely determined by the criteria described below.

Of course, Fig. 10 shows an independent field effect element,
Alternatively, it can represent either another transistor or a single field effect element included in a monolithic integrated circuit having various transistors. This structure can be used with the arrangements shown in Figures 3A, 6 and 7 as well as with the arrangements of Figures 1, 2, 3B and 3C in monolithic integrated circuits.

When non-conducting, a sufficiently high positive voltage or reverse bias voltage is applied to the drain region 13, so that a depletion region, shown briefly in broken lines in FIG. 10, is formed. When a low reverse bias voltage is applied, a depletion region surrounded by a long dashed line occurs in FIG. 10, and when a high reverse bias voltage is applied, a depletion region surrounded by a long dashed line occurs. In Figure 1,
The structure shown in the figure increases the voltage at which the depletion regions around each of drain region 13 and source region 10 meet, ie, the minimum voltage that will penetrate between those depletion regions. This is because the nature of the boundary or edge of the doped polysilicon drain region 13 changes abruptly at the end of the termination region adjacent to the channel.

The depletion region portion of the semiconductor layer 21 then starts retaining an equal amount of stationary charge on both sides of the metallization junction within the depletion region approximately at this edge.

This retention of an equal amount of charge and the relatively long extent of the relatively heavily doped drain region 13 also means that the expansion of the depletion region that occurs as the reverse bias voltage increases is in the direction perpendicular to the surface of the semiconductor layer 21. This means that most of it occurs in the direction parallel to the surface, and very little occurs in the direction parallel to the surface. That is, since the expansion of the depletion region in the direction perpendicular to the surface of the semiconductor layer 21 includes many charges that balance out the immovable charges added in the depletion region occurring in the drain region, the surface of the layer 21 Further expansion of the depletion region inside layer 21 in the direction parallel to is almost impossible. Additionally, some of the expansion of the depletion region within drain region 13 occurs relatively far from its boundaries. This is because the edges of this drain region are tapered.
Source region 10 is typically of similar construction.

By using the structure shown in FIG. 10, not only the minimum punch-through voltage can be increased, but also the breakdown voltage of the pn junction between the doped polysilicon drain region 13 and the semiconductor body 21 serving as the substrate is increased. . This increase in breakdown voltage is
As shown in FIG. 10, the length and thickness of the tapered edge of drain region 13 are directly related to the taper. If the termination edge of drain region 13 is a planar boundary perpendicular to the surface of semiconductor layer 21, the extent of the depletion region in layer 21 is parallel to that surface, so that the doped polysilicon attachment of drain region 13 There is a relatively sharp angle at the boundary of the depletion region at the point where the surface meets its surface. Such an abrupt change in the shape of the depletion region results in a relatively steep voltage slope across the depletion region at the point of the abrupt change. This means that for a given voltage the electric field at that point will be relatively strong, and therefore the breakdown voltage will be relatively low. On the other hand, in the drain region 13 having a tapered terminal edge, since no acute angle is formed at the boundary of the depletion region, the gradient of the potential does not become very large. Therefore, the breakdown voltage does not differ significantly from the breakdown voltage for planar junctions.

Another advantage of the structure shown in FIG. 10 is that the edges of the depletion region within drain region 13
When a high reverse bias voltage is applied to gate 1
It appears below the actual part of 6. As a result, the breakdown voltage can be increased by eliminating or mitigating some of the problems mentioned above in connection with the discussion of gates that vary the breakdown voltage. Therefore, the doping distribution within the polysilicon attachment of the drain region 13 and the semiconductor layer 21, the extent of the taper of the drain region 13 under the actual portion of the gate conductor 16, and the layer size of the gate insulating layer 19. , the drain depletion region should be selected to extend through those portions of the drain region 13 below the actual portions of the gate conductor 16 to the gate before breakdown occurs.

Since the structure shown in FIG. 10 can use any crystallographic plane as the main surface of the semiconductor 21,
High carrier mobilities are obtained in certain crystallographic directions.

This limits the crystallographic orientations that can be used due to the need to etch the V-groove, resulting in lower carrier mobility and higher conduction resistance, which leads to longer switching times. This is in contrast to a V-MOS device.

The structure shown in FIG. 10 can be fabricated by a simple method that does not require high temperature treatment because it does not involve a diffusion step. That is, the doped polysilicon can be deposited by a vapor deposition method that does not require high temperatures, and can be deposited on an already doped semiconductor substrate 21.
No other doped regions are provided in or on the.

The cross-sectional views shown in Figures 8, 9, and 10, if appropriately chosen, relate to Figures 3B and 3C in much the same way that Figures 6 and 7 relate to Figure 3A. do. That is, even if the geometric configuration shown in FIG. 3A is changed to the geometric configuration shown in FIGS. 3B and 3C, there is no need to significantly change the manufacturing method.

In the structure shown in FIG. 10, doped polysilicon source regions 10 and drain regions 13 extend over the substrate structure (by a distance of 1 micron and preferably 2 microns) with tapered termination edges. It is necessary to have However, this is a structure that is difficult to manufacture using certain manufacturing methods. FIG. 11 shows another MOS field effect device structure that increases the minimum punch-through voltage and minimum breakdown voltage. The structure shown in Fig. 11 consists of individual
It is to be understood that it represents a cross section of a MOS field effect transistor or a part of a MOS field effect element having several source regions and several drain regions. The cross section shown in FIG. 11 is therefore a wide variation of the cross section along line 18 in FIG. 7 and the cross section shown in FIGS. 6 and 3A with the addition of a passivation layer. be. Similarly, FIG.
It can be considered a cross-section of the structure shown in Figure C with the addition of drain and source interconnect elements and passivation layers.

In contrast to the structure shown in FIG. 10, the structure shown in FIG. 11 has a source region 10 and a drain region 13 formed in a semiconductor body 21.
has. However, a high reverse bias voltage is applied to the p-n junction between the drain and the substrate of this MOS field effect transistor (this means that a positive voltage is applied to the drain region 13 with respect to the other part of the substrate or semiconductor body 21). The doping level in regions 10 and 13 is very low so that when rendered non-conducting, drain region 13 is completely free of charge carriers before the drain-substrate p-n junction undergoes avalanche breakdown. be destroyed. As a result, the drain region side of the depletion region around the drain-substrate junction extends into the drain interconnect element 15 when a sufficiently high reverse bias voltage is applied. Similar results can be obtained in the source region 10 as well.

If the source region 10 and drain region 13 each do not contain enough impurity doping to reach the critical electric field before being fully depleted during reverse bias, the breakdown characteristics will be approximately equal to that of the associated metallization junction. It is determined by the depletion regions extending over relatively long paths and by the conditions existing around the electrical contact elements provided in these regions. This largely eliminates the contribution of gate 16 to breakdown and limits the lateral extent of the depletion region on the substrate side of the metallization junction.

To ensure that those conditions exist, the structure shown in FIG.
Use. The provision of regions 10 and 13 followed by the provision of interconnect elements results in a slight diffusion into regions 10 and 13. The area where the diffusion takes place is shown just below the interface between semiconductor body 21 and their interconnect elements.
Since the depth of this diffusion is very shallow, about 0.1 microns or less, it does not significantly affect the behavior of regions 10 and 13 even under reverse bias conditions.

The source and drain interconnect elements 12 and 15 of n-doped polysilicon are 10 ¹⁸
Doped with phosphorus at a concentration of ~10 ¹⁹ atoms/cm ² .
n-type source region 10 and n-type drain region 13
The concentration of phosphorus doped into is approximately 0.1 to 4×
It is about 10 ¹⁶ atoms/cm ² . This doping is performed by the ion implantation method described below using carefully controlled impurities. The high doping level of () the doped polysilicon electrical contact and the low doping level of () the source and drain regions on the electrical contact side of the p-n junction around the source and drain regions. The contact depleted region portions involved will spread into the source and drain interconnect elements very quickly as the reverse bias voltage applied to their pn junctions increases. Semiconductor substrate 21
The doping level of is such as to make it P-type, and is typically obtained by doping boron into the silicon of substrate 21 at a concentration of less than about 5 x ¹⁰¹⁵ atoms/ ^cm2 .

The p-type threshold voltage adjustment region 21' may or may not be provided in close proximity to the main surface of the semiconductor substrate 21. This area is indicated in FIG. 11 by a long dash-dotted line. When this region 21' is provided to adjust the threshold voltage of this MOS field effect transistor, it is formed by implanting boron atoms at a concentration of approximately 2×10 ¹⁸ atoms/cm ^{2 .} It will be done. Semiconductor substrate 2
Threshold voltage adjustment region 2 under the main surface of 1
1' depth is the source region 10 and drain region 13
It can be shallower than, equal to, or deeper than.

The effect of increasing the reverse bias voltage applied to the pn junction between the drain and the substrate is shown by the broken line in FIG. In the device shown in FIG. 11, the reverse bias is such that the drain interconnect element 15 is positive with respect to the substrate. A pair of long dashed lines on either side of the solid line representing the metallized pn junction separating drain region 13 from the remainder of semiconductor body 21 at low reverse bias voltages indicates the limits of the depletion region under this condition. That is, depletion regions occur exclusively within the semiconductor substrate 21.

Since the stationary charges in the depletion region on both sides of the drain-substrate metallization junction must be equal, the depletion region around the curved portion of the p-n junction extends deeper into the drain region 13. It extends shallowly into the semiconductor body 21 . The reason is that when the reverse bias voltage increases and the boundary of the depletion region recedes from the pn junction, the radius of curvature of the boundary of the depletion layer on the semiconductor substrate side of the pn junction becomes smaller than that of the boundary on the drain side of the pn junction. This is because the depletion region on the semiconductor substrate side of the pn junction contains other stationary charges earlier than the depletion region on the drain region 13 side of the pn junction because it is larger than the radius of curvature. Therefore, the depletion region does not extend into the channel region very quickly;
Therefore, the minimum punch-through voltage becomes higher.

If the reverse bias voltage across drain interconnection element 15 is high, the depletion region will be as shown by the short dashed line in FIG. In this case, pn
The depletion region boundary on the drain region 13 side of the junction was back to the doped polysilicon interconnect element 15. Also, the limit of the depletion region extends only slightly into the channel on the substrate side of the pn junction, whereas the depletion region on the substrate side extends deep into the substrate. The reason for this is that drain interconnection element 1
As the reverse bias voltage at 5 is increased, there are almost no charges that do not move in the direction parallel to the main surface of the semiconductor substrate 21 (when completely depleted, there are no charges that do not move in the drain region 13 anymore). ). Therefore, in order to keep the immobile charges in the depletion regions on both sides of the metallization bond equal, as the reverse bias voltage increases, no immobile charges can be found on the substrate side of the channel region along this same direction. do not have.

Therefore, in the MOS field effect transistor device shown in FIG. 11, the length of the channel can be made very short without causing the punch-through phenomenon. By shortening the channel, the channel resistance value during conduction can be lowered, and the area of the main surface of the semiconductor substrate occupied by this element can be reduced.

Also, in the state shown by a pair of short broken lines in FIG. 11, the pn between the drain and the substrate is
Because the depletion region on the drain 13 side of the junction is recessed into the drain interconnect element 15, the minimum breakdown voltage is also significantly higher. In the structural arrangement shown in Figure 11, the electric field is curved to some extent;
Due to the use of a lightly doped drain region, the reverse bias voltage applied to the drain interconnect element 15 is over a significant length of the depletion region with a low concentration of exposed stationary charge. is transmitted to weaken the electric field strength for a particular reverse bias voltage. Due to the boundary of the drain portion of the depletion region in the drain interconnect element, the influence of the gate on breakdown is much smaller.
Thus, the structure shown in FIG. 11 can be used in a manner that does not require the formation of long, thin, tapered doped polysilicon regions that serve as source and drain regions, respectively.
The minimum punch-through voltage and minimum breakdown voltage can be increased.

The structure shown in FIGS. 10 and 11 uses a conventional diffusion process to provide a heavily doped source region and a heavily doped drain region in a semiconductor substrate. This allows for closer spacing between the effective portion of the gate conductor and the source and drain interconnect element contacts. The reason for this is that when forming a MOS field effect element within the main surface of a semiconductor substrate, there is no need to diffuse the source region and the drain region in the lateral direction. That is,
In the structure shown in FIG. 10, the source and drain interconnect elements are provided by doped polysilicon deposition, since no lateral diffusion structures are provided in the semiconductor body 21. be. On the other hand, in the structure shown in FIG. 11, a lightly doped source region and a lightly doped drain region are provided in the semiconductor substrate 21 by ion implantation to self-align with the gate conductor 16. be able to. This thing is
This means that only a relatively small area of the main surface of the semiconductor body needs to be used to form the MOS field effect element. This narrow spacing of the source and drain contacts to the gate allows for a short distance across the device between the source and drain contacts, and because they act as the effective source and drain regions, the effective tend to compensate for the somewhat longer distances between the typical source and drain and between the effective gate portion.

Source region 10 and drain region 13 in FIG.
However, the doping levels in both regions should be appropriate (at least roughly symmetrical) to ensure that they become depleted before the p-n junction separating them from the rest of the substrate breaks down. (desirable performance), the doping of these regions must be relatively precise. Rather than relying solely on the concentration level, the total number of impurity atoms per unit area below the intersection of the source and drain regions of the main surface of the semiconductor substrate should be controlled. That is,
The net impurity dose of the ion implantation, i.e. the integral of the concentration over the implant depth in the semiconductor body, must be controlled and the excess amount of phosphorus atoms in the source region 10 and drain region 13 can be When the threshold adjustment region 21' is not provided, the amount of boron atoms in the substrate 21) should be less than about 1×10 ¹³ atoms/cm ² .

Whether the appropriate doping levels of the source region 10 and drain region 13 shown in FIG. This can be determined by checking the state. To do this, it is necessary to apply a reverse bias of 25 to 35V. On the other hand, in the case of a p-channel device, the pn junction between the drain and the substrate must be completely depleted without breakdown even when a high reverse bias voltage of about 80 to 90 V is applied. In fact, it has been found that the breakdown voltage of a pn junction between the drain and the substrate of a device that satisfies these requirements is approximately 200V or more when the source and substrate are grounded. ing.

When an implantation energy of 150 KV is used, source region 10 and drain region 13 in FIG. 2
separated from the rest of 1. A source region 10 and a drain region 13 are formed under the gate 16.
Separated from each other by ~4 microns. Gate 16 is made of doped polysilicon or metal and is separated from the major surface of semiconductor body 21 by a portion of silicon dioxide insulating layer 19, approximately 2000 Å thick.

Doped polysilicon is not the only material that can be used satisfactorily to make the source and drain interconnect elements of FIG.
An example of a structure made of another material is shown in FIG. In this case, the doped source interconnect element 1
2 and drain interconnect element 15 are made using multi-metal layer contacts. The first of these contacts is platinum, which is connected to the silicon semiconductor substrate 2.
1 (and threshold adjustment region 21', if provided) and ^platinum implanted or diffused into the underside of those interconnect elements. is provided in such a way as to create platinum silicide at the boundary between. In this structure, the region labeled n ⁺ in FIG. 12 is provided by ion implantation to a position shallower than 0.1 micron from the main surface of the semiconductor substrate 21. Various metal layers are then applied over this metal to form interconnect elements in one of the known electrical contact structures for monolithic integrated circuits. Other interconnect element structures may use other materials, such as aluminum contacts to silicon, or other materials that do not create a needle through the n ⁺ region provided below those contacts. Metal structures can be used.

The devices of Figures 11 and 12 increase the breakdown voltage by extending the resultant electric field further when non-conducting, thereby increasing the field strength at any point in the field when the device is in the non-conducting state. The source or drain region withstands reverse voltage. Another way to reduce the strength of the electric field at the source or drain location is to provide other means of supporting this electric field. This is a field plate provided in an insulating material in the vicinity of a source or drain region, including a pn junction surrounding the source or drain region in a semiconductor body, i.e.
This can be achieved by using a shield electrode. Breakdown voltage is improved by using the shield electrode in the insulator the same distance from the electrode material of the semiconductor body as the gate conductor or gate region is separated from the electrode material of the semiconductor body; The improvement is not as great as that provided somewhat further from the semiconductor body.

Figure 13 shows another example of increasing the minimum punch-through voltage and breakdown voltage of the device using a shield electrode.
A first modification of the MOS field effect device is shown.

This structure, which can be modified in various ways as shown in FIG. 13 (and subsequently other variations in FIGS. 14 and 15), can be used to create a cross-sectional view of a separate MOS field effect transistor element or to separate several source and drain regions. It should be understood that FIG. In the end, the cross-sectional view shown in Figure 13 (and Figures 14 and 15)
Although shown somewhat wider in FIG. 3, it is a modification of the cross-section 18 of FIG. 7 if a passivation layer were added, and thus also of FIGS. 6 and 3A. Of course, the region 24 of FIGS. 6 and 7 of the D-MOS device will not be explained here, just as it was not explained in FIGS. 10, 11, and 12. Such items will not be explained here. Figure 13 (and Figures 14 and 15)
The cross-sectional structure of FIG. 2 may be considered to be the cross-section of the device in FIGS. 2, 3B, or 3C if drain and source interconnection means and passivation layers were added to FIGS. 2, 3B, or 3C.

The MOS field effect transistor device of FIG. 13A has a pair of termination regions formed in a semiconductor substrate 21. The MOS field effect transistor device of FIG. These regions, of course, function as termination regions for what appear in FIG. 13A to be channel regions appearing below what are now split gate conductors 16 or split gate regions.
These gate conductor portions are designated 16' and 16''. Termination region 10 serves as source region 10 and termination region 1
3 is a drain region and the explanation will be continued. and,
The device of FIG. 13A is somewhat arbitrarily represented as if it were being used with a DC voltage applied thereto. However, due to the polarity of the applied voltage, region 1
Since it is determined whether either region 0 or region 13 actually acts as a source region or a drain region at any particular time of circuit operation, these termination regions can be considered as either a source region or a drain region on a circuit. actually works. These regions alternate to act as both regions when used in an alternating voltage circuit.

External interconnect means 12 are shown provided in opening 11 of source region 10 , and external interconnect means 15 are shown provided in opening 1 of drain region 13 .
4 is shown. An insulating layer 19 of silicon dioxide is shown around gates 16' and 16'', and a passivation layer 20 covers insulating layer 1.
9 and interconnection means 12 and 15 are shown above.

Further, a silicon dioxide insulating layer 19 is shown provided around a pair of shield electrodes 28 and 29. A shield electrode 28 completely surrounds the external interconnection means 12 and is located within the insulating layer 19 directly opposite the pn junction that occurs between the source region 10 and the rest of the semiconductor body 21.
This pn junction intersects the main surface of the substrate as shown in FIG. 13A. Similarly, the shield electrode 29 surrounds the external connection means 15 and faces a pn junction occurring between the drain region 13 and the other part of the semiconductor body 21, which junction intersects the main surface of the body.

Each of the shield electrodes 28 and 29 is connected to the gate conductor 1
6' and 16'' are each shown to be farther from the main surface of the semiconductor substrate 21 than the distance from the main surface of the semiconductor substrate 21. The distance from the main surface of the shield electrodes 28 and 29 is usually , two to five times the distance between the same main surface and the respective gate conductors 16' and 16''.

When the MOS field effect transistor element is in a non-conducting state, that is, the pn between the drain and the substrate
A large reverse bias is applied to the junction (first
In Figure 3A, the drain region 13 is the substrate. 13A), and the shield electrode 29 and the gate 16'' are connected in phase as shown by the broken line in FIG. 13A, and are further connected to the drain region 13. Then, the additional electric field generated from the shield electrode 29 and the gate conductor 16'' causes the electric field generated from the edge of the depletion region of the drain region 13 to be pushed deeper below the main surface of the semiconductor substrate 21. The charges in the resulting depletion layer are terminated, thereby weakening the electric field strength at the pn junction of the drain region in the main surface of the semiconductor body 21. The above main surface and gate conductor 1
Since the distance between the shield electrode 29 and the main surface of the semiconductor substrate 21 is larger than the distance between the shield electrodes 29 and the main surface of the semiconductor substrate 21, the breakdown voltage increases in relation to the electric field generated from the shield electrode 29. conductor 1
This is because the electric field generated from the shield electrode 29 spreads farther than the electric field generated at the drain region 13. However, since the shield electrode 29 is located closer to the edge of the depletion region generated in the drain region 13, the electric field generated from the shield electrode 29 has a considerable effect on the electric field emanating from the edge of this depletion region.

The insulation that prevents electrical contact between gate conductor portions 16'' and 16' causes gate conductor 16'' to be at the same voltage as drain region 13 without the device shown in FIG. 13A being switched "on". A similar condition exists in the source region 10 for a reverse voltage applied to the external interconnect means 12.

The broken line circuit shown in FIG. 13A is constructed by symmetrically connecting the elements shown therein, for example.
It can be used in AC circuits to operate. When this structure is switched "on", the two switch bars 30 and 31 are switched together to a common switch point 33. Switch point 33 is then connected to a positive voltage source greater than the threshold of the device. In this state, the device of FIG. 13A has a gate conductor 1
The operation is similar to that of a normal MOS field effect transistor in which 6' and 16'' jointly function as transistor gates.

When the structure of FIG. 13A is instead desired to be switched to the "off" state, the switch bar 30 is connected to the external connection means 12, thereby connecting the gate conductor 16' to the external connection means 12 and to the external connection means 12. and is connected to the source region 10. Similarly, the switch bar 31 is connected to the external connection means 15 and to the drain region 13. Due to this connection,
The device of FIG. 13A is maintained in the "off" state by applying a reverse voltage to the gate conductor 16' through external connection means 15 or by applying it to gate conductor 16' through external connection means 12. drooping Since only one gate is connected to a reverse voltage and the other gate is of opposite polarity to the applied voltage, the channel is not completed under this other gate and the device is therefore "off".

FIG. 13B shows the area between the shield electrode 28 and the gate conductor 16' of the device shown in FIG. 13A and the shield electrode 2.
9 and gate conductor 16'' is replaced by a continuous structure. This structure replaces the dashed short circuit between the gate conductor and its corresponding shield electrode as shown in FIG. 13A. effectively providing a short circuit.Thus, the shield and gate conductor associated with the source region 10 of FIG.
In FIG. B, they are designated by the same common reference numerals 16' and 28.
Similarly, the common symbols for the shield and gate conductors associated with drain region 13 are 16'', 29.

Assuming that we use the element shown in Figure 13B,
The circuit indicated by the broken line in Figure A becomes more convenient in practice by using the circuit shown in Figure 13C. Switching bar 30 in FIG. 13A is provided in FIG. 13C by a field effect transistor 30' and a coupling resistor 30''.Similarly, switching bar 31 is provided by a field effect transistor 31' and a coupling resistor 31''. . In some cases, transistor switching circuits are used in place of resistors 30'' and 31''.

The one in FIG. 13C with resistors 30" and 31" substantially performs the switching function of FIG. 13A. This schematic diagram is sufficient to illustrate the switching function performed by the dashed circuitry of FIG. 13A.

In FIGS. 13A and 13B, structures indicated by broken lines are in the vicinity of shield electrodes 28, 29 or integral with shield-gate conductor electrodes 16', 28 and 1.
6'', 29 and are shown at the far right and left ends of the figure.These broken line structures are directly connected to No. 13A,
The structure in Figure 13B is the 7th, 6th, 2nd, 3A, 3B
Alternatively, it is shown in a form that would appear if it were a cross section of a field effect element as shown in Figure 3C. These dashed structures are also shown for the same purpose in the structures seen in the cross-sectional views of FIGS. 13D and 14 and 15. These dashed structures will not be further explained.

If the structure of FIG. 13A or 13B is properly combined with the structure of FIG. 11 or 12, a higher breakdown voltage can be obtained than the structure of FIG. 13A or 13B alone. The result of combining the structure shown in FIG. 11 with the structure shown in FIG. 13A is shown in FIG. 13D. Note that a combination of either FIG. 13A or 13B with FIGS. 11 and 12 may also be shown. The threshold voltage adjustment region is the 13th
Although not shown in any of Figures A, 13B, or 13D, it may be provided to adjust the threshold voltage of the device if desired.

In FIG. 13D, the impurity distribution in the semiconductor substrate 21 outside the source and drain regions, the impurity distribution in the source and drain regions, the thickness of the insulating layer between the semiconductor substrate 21 and the gate substrates 16' and 16'', and the thickness of the polysilicon layer are shown. The impurity level of the external connection means 12, 15 surrounds the source and drain regions.
It is determined that charge carriers are completely removed from the source and drain regions before avalanche breakdown occurs when a reverse bias voltage is applied to the pn junction. In a normal case, the impurity of the semiconductor substrate 21 is such that boron atoms reach a concentration of 2×10 ¹⁶ atoms/cm ² . The polysilicon doped n-type conductive source and drain interconnect means 12, 15 are typically doped with phosphorus to about 10 ¹⁸ -10 ¹⁹ atoms/cm ² .

Further, phosphorus atoms are used in order of (0.1 to 4)×10 ¹⁶ atoms/cm ² to dope the n-type conductive source and drain regions 10 and 13 in the semiconductor substrate 21 . This is provided in carefully controlled amounts by ion implantation techniques, so that the total number of net impurity atoms per unit area of the semiconductor body is carefully controlled. The impurity is implanted into the semiconductor substrate below the main surface portion of the semiconductor substrate that intersects the source and drain regions. In other words, the net impurity amount of ion implantation, that is, the semiconductor substrate 2
The excess amount of phosphorus atoms in the source region 10 or drain region 13 relative to the boron impurity atoms must be controlled to be approximately 1×10 ¹³ atoms/cm ² or less by controlling the integration of the concentration over the entire implantation depth in 1. No. Further, this net amount may generally be spread over the impurity concentration appearing in the semiconductor body 21 outside the source and drain regions, or may be spread over the threshold adjustment region provided near the main surface of the semiconductor body 21.

Also, the gate conductor 16' or 16'' may be doped polysilicon or metal. Consequently, a highly doped region occurring in the source region 10 and a highly doped region occurring in the drain region 13. are located directly below the interfaces of the polysilicon-doped external connection means 12 and 15, respectively.The extent of these heavily doped n ⁺ type conductive regions is usually below the main surface of the semiconductor body 21.
0.3 microns or less.

FIG. 13E shows a source region 10 in a semiconductor substrate 21.
Alternatively, a graph of the breakdown voltage of the device plotted against the amount of impurity used to form the drain region 13 is shown. and each of the above portions is a polysilicon external interconnect means 12.
and 15 excluding the heavily doped portion appearing directly below. These relatively lightly doped regions 10 and 13 are referred to as lower conductivity termination regions and are the complete termination region portions that act as source and drain regions 10 and 13 in FIG. 13D. . The lower curve is for the lower conductivity termination region only, and is for Figure 11 or Figure 1 without the shield electrode as shown in Figures 13A and 13B.
2 represents the impurity versus breakdown voltage in the structure shown in Figure 2.

The shape of this downward curve can be explained as follows. That is, at the lower doping level, the less conductive regions are so lightly doped that they actually appear to be part of the main part of the semiconductor base 21, and the more doped regions under the external connection means of the polysilicon are doped. Only the n ⁺ region doped in the semiconductor substrate 21
Acts effectively as a termination region in The device in such a case looks like a regular MOS field effect transistor with conductive regions of the n ⁺ type acting as source and drain, the lightly doped regions generally not participating in the operation. 13th
At the higher right end of the lower curve in Figure E, the amount of doping that is to be done in the lightly doped portion of the termination region is normal.
The entire source region 1 is not so different from the source and drain regions of a MOS field effect transistor.
0 and drain regions 13 look like normal source and drain regions of such a transistor.

The upper curve in FIG. 13E shows that, at least for the structure shown in FIG. 13D, the breakdown voltage can be large for any impurity amount relative to the above curves when appropriate parameters are chosen. Therefore, if the structure shown in FIG. 11 or 12 is combined with the structure shown in FIG. 13A or 13B, a higher breakdown voltage can be obtained. The general shape of the upper curve is described as well as the shape of the lower curve.

Another variation of the structure shown in FIG. 13, which provides many of the same advantages, is shown in FIG. 14th
In Figure A, Figure 13A has two separated gate conductors 16' and 16'', whereas Figure 13A has only one gate conductor 16. Even though there is a 14th
Figure A shows only one shield electrode 34. The structure of FIG. 14A can be more easily fabricated into a monolithic integrated circuit than the structure shown in FIG. Furthermore, many of the switching circuits shown by broken lines for operating the elements in FIG. 13A are
It is not necessary to operate the device shown in Figure 4A. This is because the gate conductor 16 as a whole is operated independently of the shield electrode 34.
The shield electrode 34 is operated at a constant positive voltage that is greater than the threshold voltage of the device shown in FIG. There's no need.

In other words, shield electrode 34 is operated at a constant positive voltage whether the device of FIG. 14A is desired to be in an "on" or "off" state. When "on", shield electrode 34 is at a positive voltage as is gate electrode 16, and together these electrodes act to form a channel region between source region 10 and drain region 13 of the semiconductor body; Since the gate electrode 16 is closer to the semiconductor substrate, it has a greater influence on the formation of this channel region. When it is desired that the device structure of FIG. 14A be in the "off" state, the shield electrode 34
operate in exactly the same way as shield electrodes 28 and 29 of FIG. 13A. The electric field generated from the shield electrode 34 is applied to the source region 10 and the drain region 13, respectively.
weakens the electric field strength generated at the intersection of the pn junction with the main surface of the semiconductor substrate around the 14th A
Increase the breakdown voltage of the device shown in the figure. Further, for this purpose, the voltage applied to the shield electrode 34 is selected to be an optimum value. After all, the shield electrode 34 is the first
This is because the shield electrodes 28 and 29 in FIGS. 3A and 13B are not connected to either the source region 10 or the drain region 13. In these structures of FIG. 13, the voltage applied to the shield electrodes 28, 29 can be very high to achieve the best possible breakdown voltage, and in some structures it may be useful to increase the breakdown voltage. You can also do it.
Broken line interconnection means 35 for connection to a voltage source
is shown connected to the shield electrode 34. However, of course, the switching function for this dashed interconnect circuit is not shown.

Also, the structure shown in FIG. 11 or 12 can be effectively combined with the structure of FIG. 14A.
The combined element is the p-channel element and the 14th B
As shown in the figure. In this case, the impurity distribution in the semiconductor body 21 other than the source region 10 and drain region 13 and the impurity distribution in the lightly doped portions of the source region 10 and drain region 13 and the external interconnection means 12 and 15 of polysilicon. and the doping level of gate conductor 16 and semiconductor body 21.
When a reverse bias voltage is applied to these regions from the source region 10 or the drain region 13, the thickness of the insulating layer between the main surfaces of the pn
All are chosen so that the junction is completely free of charge carriers before avalanche breakdown occurs. Typical values of these various parameters for the well-constructed device of FIG. 14B are approximately the same as those for the device of FIG. 13D, although of course the device of FIG. 14B is a p-channel device, and the Since this is different from the n-channel elements shown in Figures 12 and 13, the type of impurity is reversed. This change from n-channel to p-channel devices is simply to demonstrate that either type can be made, and that one type may be superior to the other depending on the specific application of the device. There may be.

Another modification shown in FIG. 14C is one in which only a part of the structure of FIG. 11 or FIG. 12 is changed, and the breakdown voltage is improved. That is, the lightly doped portions of the source region 10 or the drain region 13 do not entirely surround the p ⁺ region occurring under the external interconnect means 12 and 15, respectively (in the main surface of the semiconductor body 21). ), the lightly doped regions are
In FIG. 14C, it occurs as an annular region around the P ⁺ region, and is also in contact with the rest of the semiconductor body 21 under this annular region.

The structure shown in FIG. 14C has a breakdown voltage not as high as that shown in FIG. 14B, but it has a breakdown voltage higher than that shown in FIG. 14A. Furthermore, the 14th
The structure shown in Figure C can be made completely by the self-alignment method, and therefore, as far as the area occupied by the main surface of the semiconductor body 21 is concerned, the area required to create an element with the same "on" channel resistance is small. is the first
A smaller element can be obtained than in the case of Fig. 4B. Thus, in connection with a particular application, the fourteenth
If the breakdown voltage achieved by the device in diagram C is sufficient, then
Manufacturing a single element or monolithic integrated circuit of the structure of FIG. 14C is less costly and therefore requires a smaller chip than that of the structure of FIG. 14B. A detailed description of the manufacturing method for the structure shown in FIG. 14C will be given later. In this case, the values of impurity distribution, spacing, etc. are typical values.

FIG. 14D is a plot of the breakdown voltage of the device with respect to the amount of impurity in the lower conductivity termination region for the structure shown in FIG. 14B or FIG. 14C. The values of the curves are different from each other. The lowermost curve marks only the less conductive termination region.
FIG. 11 or 12, ie, FIG. 14B or 14C, shows the case where a shield electrode is not provided or is not used. The uppermost curve represents the case in Figures 14B or 14C when the shield electrode is operated at -60V, which is the appropriate polarity for the p-channel devices in these figures. The shapes of these curves are described in exactly the same manner as described for the curve shapes of FIG. 13E.

The middle curve shown in FIG. 14D represents the case in which the shield electrode 34 is directly electrically connected to the gate conductor 16 or to the semiconductor substrate except for the termination region in FIG. 14B or 14C. The shield electrode 34 is connected to the gate conductor 16
When shorted to , the breakdown voltage is higher than without the shield electrode 34, but not quite as high as the breakdown voltage obtained when the shield electrode 34 is biased to the appropriate voltage, which is quite useful. This is because no power supply is required for it, and no means of external connection of such a power supply to the elements or to the monolithic integrated circuit chip containing such elements need be provided. That is, the shield electrode 34 is connected to the gate conductor 16 of a monolithic integrated circuit chip containing devices or devices that do not require additional interconnections.
Or directly electrically connected to the substrate.

Due to the short circuit between the shield electrode 34 and the gate conductor 16, the breakdown voltage becomes higher than that without the shield electrode 34. The case in which the shield electrode 34 is not present is unlikely to be envisaged, considering the previous explanation of how the presence of the shield electrode causes a higher breakdown voltage. In the above explanation, the electric field generated from the shield electrode due to the voltage applied to the shield electrode is generated at the intersection of the main surface of the semiconductor substrate 21 and the source region or the drain region from the pn junction around each of these regions to the source region or the drain region. It was shown that the electric field originating from the edge of the depletion region in the drain region is expelled. When shield electrode 34 is shorted to gate conductor 16, little or no voltage will be developed across shield electrode 34. The reason is that the gate conductor 1
6 is at or near zero voltage to keep the device in the "off" state. Therefore, no electric field is generated from the shield electrode 34. Rather, depending on whether a reverse bias voltage is applied to source region 10 or drain region 13, a portion of the electric field generated from the edge of the depletion layer in either source region 10 or drain region 15 ends at shield electrode 34.

In fact, this explains why the electric field across the pn junction surrounding either the source region 10 or the drain region 13, which is subjected to a reverse bias voltage, is weakened when the shield electrode 34 is shorted to the gate conductor 16 or to the substrate. . Shield electrode 34
There is no electric field generated at the intersection of these pn junctions on the main surface of the semiconductor substrate 21, and there is no change in the electric field generated at the intersection of these pn junctions on the main surface of the semiconductor substrate 21. Rather, even if a reverse bias voltage is applied to either the source region 10 or the drain region 13, the electric field generated from the edge of the depletion layer ends at the shield electrode 34, and the electric field generated in the depletion region in the semiconductor substrate 21 and the gate conductor 16 end. Contrast with something that has no choice but to end. Thus, by diverting some of the electric field from terminating at the semiconductor body 21 charge and gate conductor 16, the predetermined inversion that exists along the path from the edge of the depletion region to the semiconductor body 21 and gate conductor 16 can be avoided. The electric field for the bias voltage is smaller than what would occur without the shield electrode. Eventually, a larger reverse bias voltage is applied to either the source region 10 or the drain region 13 before this field causes breakdown in the p-n junction around the source and drain regions.
Can be applied to p-n junction. In addition, the shield electrode 34
The relative position of the source region 10 or the more lightly doped portion of the drain region 13 reduces the curvature of the electric field that increases the breakdown voltage.

The three advantages listed below are that at least gate 16
When short-circuited to the shield electrode 34, the 14th B
or FIG. 14C.

The first advantage is that when the device in either of these figures is “off,” the substrate and gate conductor 1
6/This means that there is no electric field generated between the shield electrodes 34. This is true because the substrate and gate are at approximately the same voltage, creating an "off" state. Therefore, when the device is “off,” there is a Fowler-Nordheim tunnel between the substrate and the gate.
tunnelling). If this Fuora Nordheim tunnel occurs, abnormal operation results will occur.

Second, due to the presence of the shield electrode 34, the lightly doped portion of either the source region 10 or the drain region 13 is not only located along the p-n junction between these regions and the semiconductor body 21, but also along the semiconductor body 21. A depletion region is formed along the major surface and having edges generally parallel to the major surface. Eventually, the depletion region along the junction into the semiconductor body 21 will not grow quickly enough to accommodate the increasing voltage, and therefore the punch-through voltage of the device for a given width of the gate conductor 16 will decrease without the shield electrode 34. increase than that of the case.

A final advantage is that the use of shield electrode 34 with portions of source region 10 and drain region 13 that are lightly doped for the purpose of increasing breakdown voltage reduces the "on" state of the structure shown in FIGS. 14B and 14C. The channel resistance of shield electrode 34
It can be reduced compared to the case without it. The reason for this is that when a significant voltage is applied to gate region 16, a significant voltage appears at shield electrode 34 for the purpose of switching "on" the device seen in either of these figures. This voltage across shield electrode 34 is applied to source region 10 and drain region 13.
a lightly doped part of one or the other of
The enhancement produced on the major surface of semiconductor body 21 is increased, thereby reducing the channel resistance when "on".

Shield electrode 34 in Figure 14B or Figure 14C
When used without connecting to the gate conductor 16,
Disadvantages arise due to the possibility of electric field induced junction breakdown. This is due to the voltage developed in the shield electrode 34, which has a sharp edge, which induces an inversion layer in the semiconductor body 21 just below the edge of the shield electrode 34 and which acts as a virtual source and has a relatively low breakdown voltage. . However, this drawback can be prevented by selecting an appropriate shape or by limiting the voltage applied to the shield electrode 34.

Since it is desirable that the shield electrode 34 be directly electrically connected to the gate conductor 16, a broken line interconnect 36 is shown in FIGS. 14B and 14C as this shorting means.
It is shown. However, this need not be a separate external connection means, but may be a connection means on the element itself or on a monolithic integrated circuit containing such an element. In fact, the device can actually phase bond the shield electrode 34 of doped polysilicon or metal and the gate conductor 16 in a manner that does not require any separate mutual tangents, whether internal or external connections. can be made. As mentioned above, the shield electrode 34 can be connected to the substrate, i.e., to a portion of the semiconductor body 21, but it is not possible to achieve this while retaining all of the above-mentioned advantages.

Another means of achieving a direct electrical connection between shield electrode 34 and gate conductor 16 as shown in FIGS. 14B and 14C is shown in FIG. 15. That is, the shield electrode 34 and the gate conductor 16 can be made to have a common structure as shown in FIG. 15A, as opposed to the structure shown in FIG. 14A. This common structure is labeled with group numbers 16 and 34. Similarly, FIG. 15B corresponds to FIG. 14C.

15C corresponds to the structure shown in FIG. 14B but with a lightly doped source region 1.
0 and the drain region 13 are different. The difference is that the lightly doped portions of each of the source region 10 and drain region 13 are provided with a hump at the bottom. This hump results from an alternative method of making the structure shown in Figure 15C. In this method, the hump of the lightly doped portion of each of regions 10 and 13 is made separate from the remainder of the lightly doped portion of regions 10 and 13. Of course, the fabrication of these two portions of the lightly doped portions of each of regions 10 and 13
This was described in the structure shown in Figure 4B. Shield electrode 3
A corresponding dashed line variant of 4 is shown in FIG. 15C to show that it can be changed.
The dashed deformations are shown with either rising or falling from the shield electrode portions occurring at the right and left ends of the structure in FIG. 15C. These are shown in such a way that the cross-section of FIG. 15C shows the structure found in just a few of the field effect devices having multiple source and drain regions as described above. .

Next, FIG. 16 will be described. Here is the first
The process results of the manufacturing method for manufacturing the element shown in Figure 4C are shown. The process begins with a semiconductor substrate, typically silicon doped with phosphorus to have a resistivity of 4 ohm-cm. Silicon is generally grown using czochralski growth.
It has a major surface, and manufacturing processes are performed in and on the major surface. This plane is the (100) plane. This semiconductor body is designated 110 in FIG. 16A and is of n-type conductivity.

A thin layer of silicon dioxide 111 is applied to the semiconductor substrate 11
0 is placed in an oxygen atmosphere at 975°C for 2 hours to thermally grow on the surface of the substrate. This results in a thin layer approximately 650 Å thick. Next, silicon nitride 11
2 is deposited on the surface of layer 111 by standard chemical vapor deposition (hereinafter referred to as "SCVD"), and the thickness of the layer is approximately 2000 Å. Then again
Another layer 113 of approximately 1000 Å of silicon dioxide is deposited over layer 112 by SCVD. Finally, a photoresistor layer is provided on layer 113, and then openings are provided in this layer in the desired pattern. All of this is done using standard methods.

This arrangement of the photoresist dioxide layer allows the silicon dioxide layer 113 to be buffered as an etchant.
Etched through the opening in the photoresistor layer using HF. The photoresist is then removed, followed by etching silicon nitride layer 112 through the opening in layer 113 using standard wet etching techniques using H ₃ PO ₄ . These openings are where field regions are formed, separating the formed electronic components from each other. These isolation regions are called device regions (feature
region) and contours the device area within and beneath which individual electronic devices are fabricated.

Although a MOS field effect transistor having only a single source and a single drain is shown formed in four device regions in FIG. 15A, it is possible to have multiple sources and drains of the type described above. Field effect devices can also be made using the same manufacturing method.

After providing isolation region openings through layers 113 and 112, the exposed portions of layer 111 and the underlying silicon are implanted using phosphorous ions with an energy of 120 keV. This implantation is done with an impurity level of 10 ¹³ ions/cm ² . This ion implantation is used to adjust the threshold of the isolation region, raising the threshold to prevent operation of the MOS field effect transistor between adjacent electronic devices in adjacent device regions. The ion implantation creates an n ⁺ type conductive region approximately 0.1 microns below the major surface of the semiconductor body 110.

The structure is then placed in an oxygen atmosphere at 975° C. for 10 hours to create a field oxide 114. This separates the layers 113 and 112.
oxidized by thermal growth through the openings of the At the same time, the ions initially implanted into the isolation region penetrate deep into the semiconductor body 110 by diffusion. The results are shown in FIG. 16B. In the figure, the phosphorus ions initially implanted into the separation region penetrate to a depth of 0.1 microns, which is indicated by the number 115.

The remainder of the silicon dioxide layer 113 is then removed without a mask using buffer HF. layer 11
3 is much thinner than the oxidized separation zone 114, and the layer 113
Since region 114 is not significantly removed even if the etching is performed together with the removal of the region 114, there is no need to mask it. This etched layer 114 is designated as 114'. All silicon nitride layer 112 is removed by etching with H ₃ PO ₄ .

A layer of photoresist with selected openings is then applied to the surface of oxide layer 111 using standard techniques. These openings are made in the photoresist layer to expose open portions of layer 111 over the device areas. A depletion element is to be formed in the element region, and therefore, ion implantation is performed to form a depression type region. The manufacturing method shown in FIG. 16 shows the case of manufacturing a normal MOS field effect transistor and a high breakdown voltage MOS field effect transistor. Also, one conventional MOS field effect transistor is of the enhancement type and the other is of the depletion type. These same alternatives to high breakdown voltage MOS field effect transistors are shown.

After openings are made in the photoresist above layer 111, an ion implantation is performed using boron with an energy of 100 Kev and an impurity dose of (0.5-4.0)×10 ¹² ions/cm ² . As a result, the semiconductor substrate 11
A depletion-shaped region with a pn junction is formed approximately 0.3 microns below the main surface of 0. The results are shown in FIG. 16C. The photoresist layer is numbered 116 in the figure. high breakdown voltage
The depletion-type region of the MOS field effect transistor is indicated by the number 117, while the normal MOS
The depression type region of the field effect transistor is indicated at 118.

After completing the ion implantation of the depression-shaped region, the photoresist 116 is removed. The device is then annealed by placing the structure at 975° C. for half an hour. After that, silicon dioxide layer 11
1 is also etched away using buffer HF. Etching of layer 111 includes oxidized isolation regions 1
14 is relatively thick so it is done without a mask. A portion of the oxidized isolation region is removed by etching and is designated by the numeral 114''.

Next, the gate oxide thickness is 1000 Å, which is chosen according to the design of the device made in light of its application.
The gate oxide is thermally grown by placing the structure in an oxygen atmosphere containing 4% HCL at 975° C. to a value between 2500 Å. 5000 Å polysilicon doped with phosphorus so that the sheet resistance is 50 ohms/□.
Deposited with SCVD. Of course, by depositing undoped polysilicon and then implanting impurities,
It can also be made highly conductive. After polysilicon deposition, silicon dioxide is deposited by SCVD onto the doped polysilicon to a thickness of 4000 Å. Finally, following the silicon dioxide deposition, the desired opening pattern is created in the photoresist layer over the silicon dioxide by standard techniques.

The opening in this last applied photoresist layer is located at a location under which it is not desired to provide the polysilicon gate region of the MOS field effect transistor to be fabricated. The silicon dioxide deposited on top of the polysilicon is exposed to the buffer HF through these openings in the photoresist.
The unwanted doped polysilicon is then removed using standard plasma etching techniques. After this plasma etching, the photoresist is removed using an etchant. The results are shown in No. 16D. The doped polysilicon is shown in the figure at 119, and this polysilicon is left to make the gates of the individual MOS field effect transistors being made. The remaining silicon dioxide, which was initially used as a mask to make the polysilicon gate, is shown at 120. A silicon dioxide layer used as a gate oxide separating gate 119 from the main surface of semiconductor body 110 is shown at 130 .

Moreover, what is shown in FIG. 16D is after forming the low conductivity termination region, that is, the low conductivity source and drain region.
This is performed by implanting boron ions into the semiconductor substrate 110 using an impurity amount of 10 ¹² to 10 ¹³ ions/cm ² at an energy of 100 keV. The actual amount of impurity used within this range will depend on the use of the device being made. A polysilicon gate 119 with an oxide isolation region 114'' and a silicon oxide cap 120 is used as an implant mask. Ultimately, the implanted low conductivity regions of ions provided in this way are affected by the individual MOS electric fields created. The pn junction between the low conductivity drain and source regions and the rest of the semiconductor body 110 is self-aligned with the oxide separator and gate already provided in the effect transistor. It spreads to 0.3 microns.

The low conductivity source and drain regions of a high breakdown voltage enhancement type MOS field effect transistor, i.e. the regions into which ions are implanted forming the termination region, are indicated at 121 and 122.
Regions 123 and 124 are shown at 123 and 124, where ions are implanted to form the low conductivity termination region of a high breakdown voltage depletion type MOS field effect transistor. A depletion type region into which ions of this transistor are implanted is indicated by 117'. It is narrowed considerably so that it is directly below the gate region 119 of the device.

The regions for the final ion implantation, located where the source and drain regions of a conventional enhancement type MOS field effect transistor occur, are indicated at 125 and 126. Finally, the implanted regions are shown at 127 and 128, where the source and drain regions of a conventional depletion type MOS field effect transistor are to be created. Depletion-type region 118 is designated 118' in view of the fact that it is considerably narrower as it is directly below the gate 119 of a conventional depletion-type device.

As a next step, silicon dioxide is applied over the gate oxide 130 where it is not covered by polysilicon 119, over the polysilicon gate 119 where it is not covered by gate cap 120, and over gate cap 120. It will be done.

This silicon dioxide cools this structure at 975℃.
The exposed surfaces of semiconductor body 110 and gate 119 are first thermally grown to a thickness of 1600 Å by being placed in an oxygen atmosphere containing 50% HCL for 3 hours. Next, the thickness containing 1% phosphorus is made by SCVD.
3000 Å of silicon dioxide is deposited on this structure. This structural array was placed at 950°C for half an hour and
A “crowding” of silicon dioxide is provided. in the end,
Silicon dioxide appears all around gate region 119, and all this oxide, including gate oxide layer 130, is indicated generally at 130'.

At this point in the process, the shield electrode consists of a 5000 Å thick polysilicon layer doped with phosphorus to the extent that it can be said to have a thin film resistance of 50 ohms/□.
Provided by SCVD deposition. Of course, undoped polysilicon may also be deposited which can later be doped by diffusion or ion implantation. Following this deposition, silicon dioxide is grown to a thickness of 0.1 micron over the doped polysilicon layer by placing the structure in an oxygen atmosphere at 975° C. for one hour. This silicon dioxide deposition is followed by a layer of photoresist having a desired pattern of openings over the deposited silicon dioxide using standard techniques. These openings are provided at certain locations in the photoresist layer. Next, when impurities are introduced into the semiconductor substrate 110 under these openings, high conductivity termination regions of a high breakdown voltage transistor element, that is, high conductivity drain and source regions and the source of a normal transistor are formed. A drain region is obtained. This high-conductivity termination region is located within the low-conductivity termination region as a whole when viewed from the main surface of the semiconductor substrate 110.

The silicon dioxide under these openings in the photoresist layer is removed using buffer HF. The photoresist is then removed. After etching this silicon dioxide and removing the photoresist,
HF/
Using a mixture of HNO ₃ /CH ₃ COOH in a ratio of 1:100:110, a concentric layer of silicon dioxide was deposited on the last deposited doped polysilicon beneath these openings in the photoresist layer. Etch the openings and then use another etchant to create concentric openings in the polysilicon layer. This second polysilicon layer, which is provided for the purpose of serving as a shield pole, is not required for the normal MOS field effect transistors fabricated in the two device regions on the right in FIG. This is because shield electrodes are not used in such electronic devices. The photoresist layer is removed at this time.

The results of these steps are shown in Figure 16E. In the figure, the remaining part of the polysilicon layer of the shield electrode is
31. The silicon dioxide caps on these remaining shield polysilicon 131 are used as masks during polysilicon etching.
Shown as 2.

Silicon dioxide layer 132 and polysilicon layer 13
1, the silicon dioxide layer 130' is etched using buffer HF and using the polysilicon shield electrode 131 and the silicon dioxide isolation region 114'' as an etch mask. The opening is provided through the silicon dioxide layer 130' to reach the main surface of the semiconductor body 110' directly below the opening appearing in the silicon shield electrode 131. This occurs adjacent to region 114'' and adjacent to gate region 119 of these devices. Gate region 119 becomes an etch mask after the overlying silicon dioxide is etched away. At the same time, silicon dioxide residue 1
32 is completely removed as portions of the oxidized isolation region 114'' are removed. Thus, portions of the low conductivity termination regions 121, 122, 123 and 124 are exposed on the main surface of the semiconductor body 110. Regions of conductivity 125, 126, 127 and 128
, which are located where the source and drain of a conventional transistor are made and which intersect the main surface of semiconductor body 110, are exposed. Oxidized isolation regions 114'' are shown at 114 as some of these areas are removed in the etch step.

An ion implantation step is then performed to provide high conductivity termination regions for high breakdown voltage MOS field effect transistors and to provide complete source and drain regions for conventional MOS field effect transistors. Boron ions with an energy of 100 keV are implanted with an impurity dose of 4×10 ¹⁵ ions/cm ² and the device is then annealed at 950° C. for half an hour. Subsequently, this structure is placed in an oxygen atmosphere at 975° C. for one and a half hours to thermally grow silicon dioxide to a thickness of 1000 Å on the exposed portion of the main surface of the semiconductor substrate 110 and on the polysilicon shield electrode 131. On top of this thermally grown oxide, silicon dioxide containing 6% phosphorus is deposited to a thickness of 6000 Å by SCVD. Subsequently, the regions provided by the ion implantation are allowed to diffuse deeply into the semiconductor substrate by placing the device at 1025° C. for 2.5 hours. The pn junction obtained by this diffusion is approximately below the main surface of the semiconductor substrate 110.
Reach a depth of 1.5 microns. the previously provided depletion-shaped regions 117' and 118' and the previously provided low conductivity termination regions 121, 12;
2, 123 and 124 penetrate deeply into the semiconductor substrate 110 due to this diffusion, and the semiconductor substrate 11
It reaches a depth of about 0.4 microns below the main surface of 0.

The results of these steps are shown in Figure 16F. Oxide isolation region 114 is formed after this final ion implant step by forming silicon dioxide 13 around gate 119.
It dissolves into the silicon dioxide so that the remainder of 0' dissolves into the silicon dioxide. Nevertheless, oxide isolation region 114 and silicon dioxide 130'
The remainder is shown in dashed lines in Figure 16F. This is to make it easier to understand what happened at this stage of the manufacturing process. The new layer of silicon dioxide applied after this last ion implant step is shown at 133. This is a common representation of dissolved structures.

High conductivity termination regions, ie, drain and source regions, of a high breakdown voltage enhancement type MOS field effect transistor are shown at 134 and 135. The low-conductivity termination region is 121', taking into account that the central part of these regions is modified by the presence of regions 134 and 135, and because the depth reached by these low-conductivity regions is deeper than before. and 122'.

The high conductivity termination region of the depletion type MOS field effect transistor with high breakdown voltage is 136
and 137. The low-conductivity termination region of this element is such that the center of these low-conductivity regions is the region 13.
6 and 137, and the depth reached by these low-conductivity termination regions is deep, so they are indicated by 123' and 124'. The depression-shaped region is designated 117'' since this region extends deep into the semiconductor body 110.

The termination regions, ie, the drain and source regions, of a conventional enhancement type MOS field effect transistor are designated 125' and 126', taking into account that these regions change from P conductivity to P ^- conductivity. The termination regions of conventional depletion mode MOS field effect transistors are also designated 127' and 128' for the same reason. The depression-shaped region is designated by 118'', considering that this region extends deep into the semiconductor body 110.

At this stage, a photoresist layer is provided over layer 133 according to standard methods, and openings in the photoresist layer are provided corresponding to the desired locations of the external interconnect means to be provided within layer 133. The portion of the silicon dioxide layer 133 that corresponds to the bottom of the opening provided in the photoresist layer is removed using buffer HF. The external interconnection means are here chosen to be of metal, although they may be doped polysilicon. The metal chosen is a copper-aluminum alloy, deposited as a 2.0 micron thick layer using standard vapor deposition techniques. A photoresist layer is provided over this metal layer, with openings provided at locations where no metal is needed. All of this is done using standard methods.
A mixture of H ₃ PO ₄ /HNO ₃ /CH ₃ COOH in a ratio of 50:1:5 is used as an etchant to remove the copper-aluminum alloy at these locations. Then, an annealing process is performed at 450°C for 30 minutes. Finally, a 1% phosphorus-containing silicon dioxide bathibation layer is deposited over the device by SCVD.

The results of these steps are shown in Figure 16G. The silicon dioxide layer 133, the isolation region 114Δ and the remainder 130' are shown in one piece in FIG. 16F;
As mentioned above, it is the same as 133. This combined structure is shown at 133' after portions have been removed to provide external interconnection means.
A copper-aluminum alloy body for making the external interconnection means is shown at 138 in FIG. 16G. A buffering layer over external interconnect 138 and over silicon dioxide 133' is shown at 139.

The results shown in Figure 16G show how to simultaneously incorporate enhancement type and depletion type high breakdown voltage MOS field effect elements and enhancement type and depletion type normal MOS field effect elements on one monolithic integrated circuit chip. This shows what can be done.

As mentioned above, the termination regions, ie, the source and drain regions, in the device region where a high breakdown voltage MOS field effect transistor is fabricated are shown in cross-sectional views of several devices.

Relatively high breakdown voltage devices made by the method described above, whether in enhancement or depletion mode, can have breakdown voltages from 40V to 100V. On the other hand, typical devices have a breakdown voltage of 30V or less. N-channel devices can also be made using the method for manufacturing p-channel devices.

[Brief explanation of drawings]

Figures 1A, 1B, 1C, and 2 are diagrams showing the geometrical arrangement of the source, drain, and gate of a conventional field effect transistor, and Figures 3A, 3B, and 3C are
Figure 4 shows the geometrical arrangement of the source, drain, and gate of various field effect transistors.・A graph showing the geometrical arrangement of drains and gates. FIG. 5 is a graph showing the evaluated relative cost of the arrangement of sources, drains and gates of three types of field effect transistors. FIG.
7 shows a part of the transistor of FIG. 6, FIG. 8 shows a cross-sectional view of a part of another embodiment of the transistor of FIG. 7, and FIG. 9 shows a cross-sectional view of a part of the transistor of FIG. , FIG. 7 is a cross-sectional view of a portion of another embodiment of the transistor of FIG. 7, and FIG. 10 is a cross-sectional view of a portion of another embodiment of the transistor that can withstand high reverse bias voltages. 13A, 13B,
13D is a cross-sectional view of a portion of still another embodiment of a transistor that can withstand a high reverse bias voltage, FIG. 13C is a partial circuit diagram for explaining the operation of the device in FIG. 13B, and FIG. 13E The figure is a graph comparing characteristics between elements, Nos. 14A, 14B, 1
Figures 4C, 15A, 15B, and 15C are cross-sectional views of parts of other embodiments of transistors that can withstand high reverse bias voltages, Figure 14D is a graph comparing characteristics between elements, and Figures 16A to 16G are 14C shows steps in a method for manufacturing a transistor of the type shown in FIG. 14C. DESCRIPTION OF SYMBOLS 10... Source, 12... Source interconnection element, 13... Drain, 15... Drain interconnection element, 16... Gate, 17... Gate connection opening, 19... Insulating layer, 20... Passivation layer , 21... semiconductor substrate, 28, 29... shield electrode.

Claims (1)

[Claims] 1. An electric field having a source, a drain, a gate, and a channel, and capable of withstanding a relatively high voltage between the drain and the channel and between the drain and the source in a non-conducting state. A semiconductor device including a plurality of effect transistors provided on a semiconductor substrate having a main surface, each of the field effect transistors having a channel region of a first conductivity type, a drain region of a second conductivity type, the second conductivity type source region;
a gate conductive element, a shield conductive element, a drain region interconnect element in electrical contact with the drain region, and a source region interconnect element in electrical contact with the source region; The drain region of the second conductivity type intersects with the main surface of the semiconductor substrate, forms a surface net-like portion, and has a first impurity distribution so as to be of the first conductivity type, and the drain region of the second conductivity type is a drain region of the semiconductor substrate. a drain p-n junction that intersects with the main surface of and forms a triangular surface portion and separates the drain region and the channel region; and a second impurity distribution so as to have the second conductivity type; A source region of a second conductivity type intersects the main surface of the semiconductor substrate to form a triangular surface portion, and a source p-n junction separating the source region and the channel region; the gate conductive element has a second impurity distribution such that the gate conductive element is spaced from the channel region by a first insulating layer of a first thickness and is spaced apart from the channel region by a first insulating layer; the shield conductive element is spaced from the drain and source regions by a second insulating layer of a second thickness that is greater than the first thickness;
The drain and source are separated by an insulating layer.
disposed opposite substantially all of the p-n junction, each triangular surface portion of said drain region and source region being separated in a major plane by a surface reticulation of said channel region, each triangular surface portion having a surface portion thereof an outer edge of the triangular surface portion of the drain region and an outer edge of the triangular surface portion of the source region are adjacent to each other separated by the width of the surface reticular portion; A semiconductor device, wherein the region and the source region have substantially symmetrical cross-sectional shapes with respect to the gate conductive element. 2 a plurality of field effect transistors each having a source, a drain, a gate, and a channel and capable of withstanding relatively high voltages between the drain and the channel and between the drain and the source when in a non-conducting state; A semiconductor device provided on a semiconductor substrate having a main surface, wherein each of the field effect transistors includes a channel region of a first conductivity type, a drain region of a second conductivity type, and a drain region of the second conductivity type. and the source region of
a gate conductive element, a shield conductive element, a drain region interconnect element in electrical contact with the drain region, and a source region interconnect element in electrical contact with the source region; The drain region has a first impurity distribution so as to have a first conductivity type, and the drain region of the second conductivity type is a drain region separating the drain region and the channel region.
a p-n junction, and a second conductivity type
The source region of the second conductivity type has a source p-n junction separating the source region and the channel region, and a second impurity distribution so as to have the second conductivity type. the gate conductive element is spaced from the channel region by a first insulating layer of a first thickness and positioned opposite the channel region across the first insulating layer; and the shield conductive element is separated from the drain region and the source region by a second insulating layer having a second thickness that is thicker than the first thickness;
The drain and source are separated by an insulating layer.
The drain region and the source region intersect with the main surface of the semiconductor substrate, and either one of the drain region and the source region intersects the main surface of the semiconductor substrate.
one forming a triangular surface portion, the other forming a surface reticular portion, the channel region surrounding the entire periphery of each triangular surface portion on the main surface of the semiconductor substrate to form a larger triangular surface portion; and the larger triangular surface portions have an outer edge that serves as a boundary for the surface portions, and these larger triangular surface portions are separated by said surface reticulation, and the outer edge A semiconductor device, wherein the drain region and the source region face each other separated by the width of the mesh portion, and the cross-sectional shapes of the drain region and the source region are substantially symmetrical with respect to the gate conductive element.