GB2045525A

GB2045525A - Field effect transistor construction

Info

Publication number: GB2045525A
Application number: GB8010180A
Authority: GB
Original assignee: Honeywell Inc
Current assignee: Honeywell Inc
Priority date: 1979-03-28
Filing date: 1980-03-26
Publication date: 1980-10-29
Also published as: CA1142271A; JPS55132054A; FR2452789A1; DE3011778A1; JPH0332234B2

Abstract

The punch-through and breakdown voltages of an FET are increased by providing shield electrode means 28, 29 which surround the conductive connections 11, 14 to the source and drain regions 10, 13. The shield electrode means lie in the insulating layer 19 over the semiconductor body 21, closer to the conductive connections and further from the surface of the semiconductor body than the gate electrode means 16. The gate 16 may be split, 16' and 16'', and the shield electrode means may be connected to or formed as part of the gate electrode means. If separate, the shield electrode means can be a single sheet surrounding both connections 11 and 14 and connected to a fixed voltage. A further increase of voltage limits results from making the connections 11 and 14 of doped polysilicon, giving a further thin, highly doped layer in each of the source and drain regions. <IMAGE>

Description

SPECIFICATION Field-effect transistor construction The present invention relates to field-effect transistors, and more specifically to structural arrangements for improving their capability of withstanding reverse bias.

In particular, there is a need for a fieldeffect transistor having a substantial minimum punch-through voltage and a substantial minimum breakdown voltage. Such characteristics are desirable where the transistor is used, for example, for direct switching and control of high voltage supplies such as mains supplies.

These character.stics are difficult to achieve, particularly with monolithic integrated circuits.

Accordingly the present invention provides an FET (field-effect transistor) comprising:~ a semiconductor body of one conductivity type having formed therein source and drain regions of the other conductivity type, with the region between the source and drain regions forming the gate region; an insulating layer over the surface of the semiconductor body, having apertures through which conductive connections are formed to the source and drain regions; gate electrode means in or on the insulating layer and over the gate region; and shield electrode means formed in or on the insulating layer, encircling the conductive connections to the source and drain regions and being nearer to those connections than the gate electrode means and spaced further from the semiconductor body by the insulating layer than the gate electrode means.

A variety of field-effect transistors and a method of making them will now be described, by way of example, with reference to the drawings, in which: Figures 1A, 1 B, 1 E and 2A to 2C are diagrammatic part sectional views of various devices; Figure 1 C is a circuit diagram showing how the device of Fig. 1 B is to be operated; Figure ID is a set of graphs indicating the operating characteristics of the devices relative to the prior art; Figures 3A to 3E show various stages of the manufacture of a plurality of transistor devices, including one of the Fig. 2B type.

Fig. 1A shows a first version of an MOS field-effect device which provides increased minima for device punch-through and breakdown voltages by using a shield electrode.

This structure with its variants, as shown in later Figures, may be taken as representing a cross section of an individual MOS field-effect transistor device.

The device has a pair of terminating regions, 10 and 13, formed in semiconductor material body 21. These regions are joined by a channel region appearing underneath a split gate conductor 16, or split gate region. The components of this gate conductor are designated 16' and 16". The terminating regions 10 and 13 are the source and drain regions, which is which depending on the polarity of the applied voltage.

External interconnection means 12 are made in opening 11 to source region 10, and external interconnection means 15 are made in opening 14 to drain region 13. A silicon dioxide insulating layer 19 is shown around gates 16' and 16" and a passivating layer 20 is shown over insulating layer 19 and interconnection means 12 and 15.

Further, in the silicon dioxide insulating layer 19 there is a pair of shield electrodes, 28 and 29. Shield electrode 28 completely surrounds external interconnection means 12 and is in insulating layer 19 directly across from the pn junction, occurring between source region 10 and other parts of semiconductor material body as 21, where this junction intersects the major surface of that body, as shown in the Figure. Similarly, shield electrode 29 surrounds external connection means 15 and is across from the pn junction, occurring between drain region 13 and other parts of semiconductor material body 21, where this junction intersects the major surface of that body.

The shield electrodes 28 and 29 are spaced away from the major surface of semiconductor material body 21 further than the gate conductors 16' and 16" are spaced away from that surface. This spacing of the shield electrodes 28 and 29 from the major surface of semiconductor material body 21 is typically 2 to 5 times that spacing occurring between the same major surface and either of gate conductors 16' and 16".

Consider the situation when MOS fieldeffect transistor device is in the "off" condition, with a large reverse bias on the drainsubstrate pn junction (meaning that drain region 13 is positive with respect to the substrate, i.e., the other portions of semiconductor material body 21) and with electrode 29 and. gate 16" both connected together and to drain region 13 as shown by the dashed line circuits. Then the additional field emanating from shield electrode 29 and from gate conductor 16" will force the field emanating from the depletion region edge in drain region 13 to terminate on exposed charge in the depletion region occurring deeper below the major surface in semiconductor material body 21 to thereby lessen the field intensity at the drain region pn junction in the major surface of semiconductor material body 21.Relatively larger spacing between shield electrode 29 and the major surface of semiconductor material body 21 compared to the spacing between that surface and gate conductor 16" will increase the breakdown of voltages associated with the field emanating from shield electrode 29 as this electric field is spread out over a greater distance than is the electric field occurring on conductor 16". Neverthe less, the location of electrode shield 29 closer to the edge of the depletion region occurring in drain region 13 permits the field emanating from shield electrode 29 to have a substantial effect on the electric field amanating from this depletion region edge.

The insulation preventing electrical contact between gate conductor portion 16" and 16' permits having gate conductor 16" at the same voltage that is present on drain region 13 without the device being switched "on".

A similar situation exists at source region 10 for a reverse voltage applied to external inter connection means 12.

The dashed line circuit permits operating the device symmetrically, e.g., in an alternat ing polarity circuit application. When this structure is to be switched "on", the two switch bars 30 and 31 are both switched together to common switch point, 33, which is in turn connected to a positive voltage exceeding the threshold voltage of the device.

In this condition, the device will operate as would an ordinary MOS field-effect transistor with gate conductors 16' and 16" together serving jointly as the transistor gate.

When the device is desired to be switched to the "off" condition, switch bar 30 is connected to external connection means 12 which thereby connects gate conductor 16' to external connection means 12 and so to source region 10. Similarly, switch bar 31 is connected external connection means 15 and so to drain region 13. This arrangement permits holding the device "off" whether the voltage to be withstood is applied to external connection means 15, and so to gate conductor 16", or to external connection means 12, and so to gate conductor 16', relative to external means 15. Since but one gate is connected to the voltage to be withstood, and the other gate to the other polarity of the applied voltage, no channel will be completed under this other gate and so the device is off.

The dashed line circuitry of Fig. 1A may be more practically implemented therewith by use of the circuit shown in Fig. 1 C. The switching bar 30 of Fig. 1A is implemented by a field-effect transistor, 30', and a coupling resistor, 30", at Fig. 1C. Similarly, switching bar 31, is provided by a field-effect transistor, 31', and a coupling resistor, 31". In some instances, a transistor switching circuit arrangement will be used in place of resistors 30" and 31".

The arrangement of Fig. 1 C with resistors 30" and 31" can approximately provide the switching function of Fig. 1A. This approximation is sufficiently close enough too provide the switching functions achieved by the dashed line circuitry shown in Fig. 1A.

The structure of Fig. 1A can advantageously incorporate a further feature to provide an even higher breakdown voltage than for the structure of Fig. 1A taken alone. The result of this is shown in Fig. 1 B.

It should first be noted that in Fig. 1B, the shield electrode 28 and the gate conductor 16' have been combined into a continuous structure 16', 28. Likewise, the shield electrode 29 and the gate conductor 16" have been combined into a continuous structure 16", 29. This eliminates the need for external connections between the shields and the gate conductors.

In addition, the metal conductors 12 and 15 have been replaced by polysilicon, and the dopant distributions in the semiconductor 21 have been modified. These dopant distributions, the thickness of the insulating layer between the semi-conductor body 21 and the gate conductors 16' and 16", and the dopant distribution in the polysilicon external connections 12 and 15 are all such that drain regions 10 and 13 can be completely depleted of charge carriers prior to avalanche breakdown of the pn junctions surroundiDJ these regions when these junctions are subjected to reverse bias voltage. In a typical situation, doping of semiconductor 21 will be such that there will be boron atoms present reaching a concentration of up to 2 X 1016 atoms/cm3.The doped polycilicon n-type conductivity source and drain interconnection means 12 and 15 are typically doped by phosphorus to the extent of 1019 to 1019 atoms/cm3.

There will also be phosphorus atoms used in doping the n-type conductivity source and drain regions 10 and 13 in semiconductor material body 21 on the order of 0.1 to 4 X 1016 atoms/cm3. This will be provided by a carefully controlled dose in an ion implantation step to carefully control the total number of net impurity atoms per unit area provided the semiconductor below the surface at the source and drain regions. That is, the ion implantation net dose, i.e., the integral of the concentration over depth in the semiconductor 21, must be controlled, so the excess of phosphorus atoms in either the source region 10 or the drain region 13 over the boron dopant atoms there is due to a dose of less than approximately 1 X 10'3 atoms/cm2.

Again, this net may be over the dopant concentration appearing in the semiconductor 21 outside the source and drain regions generally, or above a threshold adjust region provided adjacent to the surface of semiconductor 21.

The gate conductor 16' or 16" can be either of doped polysilicon or of metal. Finally, there will be a heavily doped region occurring in source region 10 and one in source region 13 just below the interface of the doped polysilicon external connection means 12 and 15, respectively. These heavily doped n±type conductivity regions will typi cally extend less than 300 nm below the major surface of semiconductor 21.

In the structure of Fig. 1 B, the doping levels in regions 10 and 11 are extremely low so that when the device is in the "off" condition, with a large reverse bias on the drain-substrate pn junction (i.e. the drain region 13 is positive with respect to the substrate), the drain region 13 is completely depleted of charge carriers prior to avalanche breakdown of the drain-substrate pn junction.

As a result, the drain region side of the depletion region around the drain-substrate junction extends into drain interconnection means 15 for sufficient reverse bias voltage.

A similar result would be obtained at source region 10.

By ensuring that source region 10 and drain region 13 each do not contain sufficient impurity doping to reach a critical electrical field prior to complete depletion under reverse bias, the breakdown properties become determined essentially by a depletion region spread over a relatively long path over the metallurgical junction involved and by the conditions existing around the electrical contact means made to these regions. This situation, to a substantial extent, removes the influence of gate 16 from affecting breakdown and limits the lateral extent of the depletion region on the substrate side of the metallurgical junctions.

To assure these conditions exist, the structure of Fig. 1 B uses highly doped polysilicon source interconnection means 12 and highly doped polysilicon drain interconnection means 15. Providing the interconnection means or electrical contacts in operations subsequent to providing regions 10 and 13 also leads to a slight diffusion into regions 10 and 13 shown just below the interface between the semiconductor material body 21 and these interconnection means. The depth of this diffusion is very shallow, approximately 100 nm or less, and does not have a significant effect on the behaviour of region 10 and 13 under reverse bias conditions.

The high doping level of the doped polysilicon electrical contacts, and the low doping level of the source and drain regions, leads to the extending of the contact depletion region portions-those on the electrical contact side of the pn junctions around the source and drain regions, respectively-into the source and drain interconnection means very soon with increasing reverse biasing voltage on these pn junctions.

A threshold voltage adjust region, 21', also of p-type conductivity, may be provided in semiconductor 21 immediately adjacent to its surface, as shown in Fig. 1 E (which omits much of the structure above the semiconductor body 21). This region would usually be fabricated by implanting boron atoms reaching a concentration of typically around 2 X 1016 atoms/cm3. The depth of threshold adjust region 21' below the major surface of body 21 may be less than, equal to, or exceed the depth of the source and drain region 10 and 13.

The effects of increasing reverse bias voltage on the drain-substrate pn junction, i.e. an increasing positive voltage applied to the drain interconnection means 15 in Fig. 1 E with respect to the substrate, are shown by the dashed lines displayed in that figure. For low reverse bias voltages, a pair of long dashed lines on either side of the solid line depicting the pn junction, separating the drain region 13 from the remainder of the semiconductor material body 21, represents the limits of the depletion region in this condition. That is, the depletion region occurs entirely within the semiconductor material body 21.

Since the immobile charge within the depletion regions on either side of the drain-substrate metallurgical junction must be equal, the depletion region around the curved portion of the pn junction extends less far into the channel region of the semiconductor material body 21 than it does into the drain region 13. This is because the receding of the depletion region boundaries from the pn junction with increasing reverse bias will more quickly include additional immobile charges in the depletion region on the semiconductor material body 21 side of the pn junction than on the drain region 13 side because of the greater radius of curvature of the depletion region boundary on the body side of the junction as opposed to the radius on the drain side of the junction.Thus, the depletion region will not extend into the channel region as rapidly and the punch-though voltage minimum will be increased.

For a higher reverse bias voltage on the drain interconnection means 15, the short dashed lines in Fig. 1 E result. The depletion region boundary on the drain region 13 side of the metallurgical pn junction has now receded into the doped polysilicon interconnection means 15. Again, there has been relatively little increase in the depletion region limit on the substrate side of the pn junction into the channel, but rather the increase in the depletion region on the substrate side goes deeper into the substrate body. This is based on the fact that little more immobile charge is being uncovered by increasing reverse bias voltage in the drain interconnection means 15 in the direction parallel to the major surface of the semiconductor material body 21 (no further immobile charge is uncovered in region 13 as it is completely depleted).Consequently, to maintain equal amounts of immobile charge in the depletion region on both sides of the metallurgical junction, little more immobile charge is uncovered on the substrate side of the channel region along this same direction with the increasing reverse bias voltage.

This being so, very short channel lengths can be used for the MOS field-effect transistor device of Fig. 1 E without encountering punchthrough. This use of short channel lengths lowers the "on" condition channel resistance and reduces the semiconductor material body major surface area taken up by the device.

There is also a substantial improvement in the breakdown voltage minimum because in the condition shown by the pair of shortdashed lines in Fig. 1 E, the depletion region on the drain 13 side of the drain-substrate pn junction has receded into the drain interconnection means 15. While there is some curvature of the electric field in this geometry, the reverse bias voltage applied to the drain interconnection means 15 is spread over a substantial longer depletion region having less concentrated exposed immobile charge by virtue of the use of the lightly doped drain region 13 leading to a lower electric field for a particular reverse bias voltage. Further, with the boundary of the drain portion of the depletion region in the drain interconnection means 15, the influence of the gate 16 on breakdown is much reduced. Thus, the Fig.

1 E structure obtains improved minimum punch-through voltages and breakdown voltages.

For the structure of Fig. 1 E, the avoidance of a substantial doping diffusion step to provide heavily doped source and drain regions in the semiconductor material body present, as is typically done, allows closer spacing of the effective portions of the gate conductor to the source and drain interconnection means contacts. This is so because no sideways, or lateral, diffusion of the source and drain regions need be allowed for in and packing of the MOS field-effect device in the major surface of the semiconductor material body. That is, in Fig. 1 E, the lightly doped portions of the source and drain regions in the semiconductor material body 21 may be provided through ion implantation which will self-align with gate conductor 16. This means that only a relatively small area in the semiconductor material body major surface need be used in forming a MOS field-effect device.The closer source and drain contact spacing with respect to the gate, permitting reduced distances across the device between the source and drain contacts, will tend to offset the somewhat larger distances involved between the effective source and drain, on the one hand, and the effective gate portions on the other, due to having the contacts serve as the effective source and drain regions.

Because of the importance of having the proper doping level in both (at least where more or less symmetrical capabilities are desired) the source region 10 and the drain region 13 of Fig. 1 E, to assure that depletion therein occurs prior to breakdown of the pn these septrating ttese regions from Ihe remainder of the substrate, the doping requirements for these regions must be relatively precisely met. Rather than a concentration level alone being the criteria, the total number of net impurity atoms per unit area provided in the semiconductor material body below the portions of the semiconductor material body major surface intersected by the source and drain regions is to be controlled.

That is, the ion implantation net dose must be controlled, i.e. the integral of the concentration over depth in the semiconductor material body must be controlled, so that the excess of phosphorus atoms in either drain region 13 and in source region 10 over the boron dopant atoms in region 21' (or in substrate 21 if no differentiated region 21' is provided) is due to a dose of less than approximately 1 X 10'3 atoms/cm2.

Whether the proper doping levels for the source and drain regions of Fig. 1 E has been achieved can be determined by checking that the drain regions, for instance, are completely depleted when reverse biased without the junction being in breakdown, which will require the application of a reverse bias voltage of between 25 and 35 V. On the other hand, for a p-channel device, the drain-substrate pn junction should completely deplete without the junction being in breakdown when subjected to a sufficient reverse bias voltage which will be between approximately 80 to 90 V. In practice then, the breakdown voltage across, for instance, the drain-substrate pn junction in devices satisfying these requirements, will be found to be around 200 V or more with the substrate and source commonly grounded.

Using an implantation energy of 150kV, the source regions 10 and drain regions 13 of Fig. 1 E will be separated from the remainder of the semiconductor material body 21 by a pn junction being at a depth of approximately 1 ym below the major surface of the semiconductor material body 21. Source regions 10 and drain regions 13 will be separated from one another by approximately 2 to 4Ism below gate 16. Gate 16 can be either doped polysilicon or metal and will be separated from the major surface of semiconductor material body 21 by a portion of, typically, silicon dioxide of insulating material 19 usually about 0.2#m thick.

Doped polysilicon is not the only material which can satisfactorily be used for making the source and drain interconnection means of Fig. 1 E. An alternative is to form the source interconnection means 12 and the drain interconnection means 15 by the use of multiple metal layer contacts, the first contact being platinum which is provided in a manner to form platinum silicide at the interface between the platinum and the very shallow n±type conductivity region implated or diffused below these interconnection means in silicon semiconductor material body 21 (and in threshold adjust region 21' if present). In this arrangement, the regions marked in n+ are provided by ion implantation, and are very shallow, being less than 100nm below the major surface of semiconductor material body 21.

Thereafter, various layers of metal on the platinum can be provided to form the interconnection means in one of the well known electrical contact structures for monolithic integrated circuits. Other interconnection means structures can be used with other materials such contacting the silicon with aluminum contacts of any other metallurgical arrangement which does not lead to spiking through the nf regions provided below these contacts.

Fig. 1 D is a graph of device breakdown voltage VBD plotted against the dose DOSE used in providing those portions of either source region 10 or drain region 13, in semiconductor material body 21, occurring outside of the heavily doped portions appearing just below polysilicon external interconnection means 12 and 15, respectively. These relatively lightly doped portions of region 10 and drain region 13 can be termed lower conductivity terminating regions in being portions of the complete terminating regions which serve as source region 10 and drain region 13 in Fig. 13D. The lower curve A represents the breakdown voltage versus dose for a structure without a shield, and curve B shows the effect of using a shield as shown in Figs. 1A, 1 B and 1 E.

The shape of curve A can be explained by noting that in lower doses, the lower conductivity terminating region becomes so lightly doped as to appear nearly intrinsic or actually as part of the main portion of semiconductor material body 21 so that only the heavily doped n+ region below polysilicon external connection means is effective is acting as the terminating region in semiconductor material body 21. In such a circumstance, the device appears as an ordinary MOS field-effect transistor with the n ±type conductivity regions serving as the source and drains therein, the lightly doped regions being generally ineffective.At high doses on the right hand edge of the lower curve of Fig. 1 D, the doping in what is supposed to be at the lightly doped portion of the terminating regions becomes so great as to not differ much from the source and drain regions in an ordinary MOS fieldeffect transistor so that the entire source region 10 and drain region 13 appear as ordinary source and drain regions for such a transistor.

Curve B shows that the breakdown voltage can be increased at every dose for which the curve is presented, at least when the proper parameters are chosen for the structure shown in Fig. 1 E. Thus the use of shields leads to a device with a higher breakdown voltage. The general shape of the upper is explained in the same manner as the shape of the lower curve.

An alternative structure which can provide many of the same advantages is shown in Fig.

2. In Fig. 2A, there is now but one gate conductor 16 as opposed to the two split gate conductors 16' and 16" shown in Fig. 1A.

There is also but one shield electrode, 34, shown in Fig. 2A as opposed to the two shield electrodes 28 and 29 shown in Fig.

1A. The structure shown in Fig. 2A is more readily fabricated in monolithic integrated circuit form than are the structures shown in Fig.

1. Further, much of the switching circuitry shown in dashed lines in Fig. 1A to operate the device shown there is not required for operating the device shown in Fig. 2A. This is because the gate conductor 16 can be operated entirely independently of shield electrode 34. Shield electrode 34 can be operated at some positive, constant voltage greater than the threshold voltage of the device shown in Fig. 2A but need not be operated at a voltage as high as the voltage to be withstood in the "off" condition at either of the external connections 12 or 15.

That is, shield electrode 34 can be operated at a constant positive voltage whether the device of Fig. 2A is desired to be in the "on" condition or the "off" condition. In the "on" condition, the shield electrode 34 will be at a positive voltage as will gate electrode 16 both of which will act to induce formation of a channel region in the semiconductor material between source region 10 and drain region 13, although gate conductor 16 will be much more effective in achieving this inducement by being closer to the semiconductor material.

When the device structure of Fig. 14A is desired be in the "off" condition, shield electrode 34 will act just as did shield electrodes 28 and 29 in Fig. 1A. The electric field emanating from electrode 34 will force a reduction in the electric field intensity occurring at the semiconductor material major surface intersections of the pn junctions around source region 10 and drain region 13, respectively, to thereby increase the breakdown voltage of the device shown in Fig. 2A. Further, the optimum value of voltage for this purpose to be applied to shield electrode 34 can be chosen because shield electrode 34 is not connected to either source region 10 or to drain region 13, as were shield electrodes 28 and 29 in Fig. 11A. In the structures in Fig.

1, it was possible that the voltage applied to shield electrodes 28 and 29 would be too high for achieving the best breakdown voltage as possible and could even contribute to an increase in breakdown voltage in some configurations. A dashed line interconnection, 35, for connection to a voltage supply is shown made to shield electrode 34 and, of course, no switching function is shown with this dashed interconnection circuit.

Again, the structure of Fig. 2A can be modified in the same way that the structure of Fig. 1A was modified to give the structure shown in Fig. 1 B, by using doped polysilicon for the conductors 12 and 15. Naturally, the device can be either p-channel or n-channel.

Further modification is shown in Fig. 2B, in which only the semiconductor body is shown.

Rather than having the lightly doped portion of source region 10 or drain region 13 entirely surround the p+ region occurring below external interconnection means 12 and 15, respectively (except along the surface of semiconductor 21), the lightly doped region occurs in Fig. 2B as an annulus region around a p+ region which is also in contact with the remaining portion of semiconductor 21 below this annulus.

The configuration shown in Fig. 2B does not give as high a breakdown voltage as does the doped polysilicon modification of the structure of Fig. 2A but does provide a greater breakdown voltage than does the structure shown in Fig. 2A alone. Furthermore, the structure shown in Fig. 2B can be fabricated in a completely self-aligned manner to thereby provide a smaller device insofar as use of area of the major surface of semiconductor material body 21 is concerned as compared to the area required to fabricate the device shown in Fig. 2A, with the doped polysilicon modification, for the same "on" condition channel resistance.Thus, if in the particular use involved, if the breakdown voltage achieved by the device of Fig. 2B is sufficient, the fabrication of a device or monolithic integrated circuit using the structure of Fig. 2B will be less costly, through permitting a small chip, than one relying on the configuration shown in Fig. 2A.

Fig. 1 D can be used to show the effect of the structures of Figs. 2A and 2B. Curve A again represents the conventional structure, i.e. without the presence and use of shield electrode 34. Curve C represents the situation in Fig. 2A or 2B when shield elelctrode 34 is operated at - 60 V, which is the proper polarity for the p-channel device as shown in Fig. 2B. The intermediate curve B represents the situation in Fig. 2B in which shield electrade 34 is directly electrically connected to gate conductor 16 or to semiconductor material body 21 outside the terminating regions, i.e., the substrate. The fact that shorting shield electrode 34 to gate conductor 16 results in a high breakdown voltage than in the absence of shield electrode 34, although not as high as can be achieved when shield electrode 34 is biased to an optimum voltage, is quite useful.This is because no further power supply is required and no provisions need be made for an external connection of such a power supply to a device or a monolithic integrated circuit chip having such a device. That is, the shield electrode 34 can be directly electrically connected to gate conductor 16 or the substrate right in the device or in the monolithic integrated circuit chip containing the device without any further interconnections being needed.

The direct electrical connection between the gate conductor 16 and the shield electrode 34 can be made by modifying the Fig. 2A or 2B structure in the same way as the Fig. 1A structure was modified to give the Fig. 2B structure with its combined gate and shield arrangement. Of course, when this modification is made to the Fig. 2A or 2B structure, there is only a single combined gate and shield element.

That shorting of field electrode 34 to gate conductor 16 results in a higher breakdown voltage than would be the case in the absence of shield electrode 34 may seem unexpected in view of the earlier description of how the presence of a shield electrode permits reaching a higher breakdown voltage. The earlier description indicated that a voltage on a shield electrode leads to an electric field emanating from the shield electrode forcing the electric field emanating from the edge of the depletion region in the source or drain region away from the pn junction around each of these source and drain regions at the intersection of these junctions with the major surface of semiconductor material body 21.Here, there is likely to be little or no voltage occurring on the shield electrode 34 when shorted to gate conductor 16 because gate 16 will likely be at or near zero volts to hold the device in the "off" condiction. Thus, there will be no electric field emanating from shield electrode 34. Rather, there will terminate on shield electrode 34 a portion of the electric field emanating from the depletion region edge, either of the source region 10 or drain region 15 depending on which of these is subjected to withstanding a reverse bias voltage.

And indeed, this is the explanation of why the electric field intensity is reduced across the pn junctions surrounding either source region 10 and drain region 13 when subjected to a reverse bias voltage when shield electrode 34 is shorted to gate conductor 16 or the substrate. There is not an electric field emanating from shield electrode 34 to force a change in the electric field occurring at intersection of these pn junctions on the major surface of semiconductor material body 21.

Rather, the field emanating from the depletion region edge, in whichever of source region 10 or drain region 13 is withstanding a reverse voltage, terminates on shield electrode 34 in contrast to otherwise having to terminate on gate conductor 16 or on exposed charge in the depletion region portion occurring in semiconductor material body 21. Thus, by diverting part of the electric field away from terminating on change in semiconductor material body 21 or on gate conductor 16, a smaller electric field will exist along paths from the depletion region edge to semiconductor material body 21 and gate conductor 16 for any given voltage being withstood by the pertinent terminating region than would occur if shield electrode 34 was not present.As a result, a larger reverse voltage can be applied to the pn junctions around either source region 10 or drain region 13 before the electric field leading to breakdown across the junctions around these regions is reached. Further, the relative positions of shield electrode 34 and the more lightly doped portions of either source region 10 or drain region 13 lead to less curvature in the electric field which also increases the breakdown voltage.

Three further advantages come from the structures shown in Figs. 2B, at least when gate 16 shorted to electrode 34. First, note that there will be no electric field generated between the substrate and gate conductor 16 and shield electrode 34 when the device in either of these figures is in the "off" condition. This is true since the substrate and the gate are at approximately the same voltage potential to produce the "off" condition.

Thus, there will be little Fowler-Nordheim tunnelling between the substrate and gates when the device is in the "off" condition; unusual operation can result if this occurs.

Second, because of the presence of shield electrode 34, the lightly doped portion of either source region 10 or drain region 15 will have a depletion region formed along the major surface of semiconductor material body 21, with an edge more or less parallel with this surface, as well as along the pn junction between these regions and semiconductor material body 21. As a result, the depletion region along the junction into semiconductor material body 21 need not grow as rapidly with increasing voltage and so the punchthrough voltage of the device for a given width of gate conductor 16 is increased over what it would be in the absence of shield electrode 34.

Finally, the use of shield electrode 34 along with lightly doped portions of source region 10 and drain region 13 for the purpose of increasing the breakdown voltage, also aids in reducing the "on" condition channel resistance for the device structure shown in Fig.

2B over what it would be in the absence of shield electrode 34. This is because the application of a substantial voltage to gate region 16 for the purpose of switching "on" the device shown in either of these figures also leads to a substantial voltage appearing on shield electrode 36. This voltage on shield electrode 36 then aids in increasing the enhancement occurring at the major surface of semiconductor material body 21 in these lightly doped portions of one or the other of source region 10 and drain region 13 to thereby reduce "on" condition channel resistance.

A possible disadvantage in the use of shield electrode 34 of Fig. 2B without the shield electrode connected to gate conductor 16 comes about because of the possibility of field-induced junction breakdown. This is the result of voltage, occurring on shield electrode 34, inducing an inversion layer in semiconductor material body 21 underneath the edges of the shield electrode which would serve as a virtual source and which would have a sharp corner with a relatively low voltage breakdown. However, proper configurational choices, or limiting voltages applied to shield electrode 34, can prevent this from occurring.

Because of the desirable possibility of having shield electrode 34 directly electrically connected to gate conductor 16, a dashed line interconnection, 36, has been shown in Fig. 2A as a possible means for accomplishing this shorting. However, this need not be a separate external connection but could be a connection made in the device itself or in a monolithic integrated circuit containing such a device. In fact, the device may be fabricated in such a manner that the doped polysilicon or metal making up shield electrode 34 and gate conductor 16 actually join one aother to remove any need for forming a separate interconnection, external or internal. As earlier noted, shield 34 can be connected to the substrate, i.e., portions of semiconductor body 21, but not while retaining all of the above advantages.

Fig. 2C corresponds to the structure shown in Fig. 1 B but with a polarity reversal and a change in the lightly doped portions of source region 10 and drain region 13. This change is the appearance of a hump in the bottom part of the lightly doped portion in each of source region 10 and drain region 13. This hump can occur because of an alternative method of fabricating the structure shown in Fig. 2C. In this method of fabrication, the hump part of the lightly doped portion in each of regions 10 and 13 is provided separately from the remaining parts of lightly doped portions in regions 10 and 13.

Turning now to Fig. 3, the results of steps in a fabrication process for manufacturing the device shown in Fig. 2B are shown.

The process starts with a silicon semiconductor material body 110 doped with phosphorus to have a resistivity of 4 ohm-cm to have an n--type conductivity. The silicon is Czochralski grown and its major surface, through and on which the fabrication process will take place, is a (100) plane.

Fig. 3A. A thin layer of silicon dioxide, 111, is thermally grown on the major surface of the semiconductor 110 by placing it in an oxygen atmosphere at 975 C for two hours, the layer then having a thickness of approximately 65mm. Then a 200nm thick layer of silicon nitride 112 is deposited on the surface of layer 111 by a standard chemical vapor deposition process. This is followed by depositing a 100nm thick layer of silicon dioxide 113 onto layer 112, again by using a standard chemical vapor deposition process.

Next, a photoresist layer is formed on layer 113 and provided with openings therein in a desired pattern. This photoresist dioxide layer arrangement permits silicon dioxide layer 113 to be etched through the openings in the photoresist layer using buffered HF as an etchant. Next, the photoresist is stripped away and this is followed by etching silicon nitride layer 112 through the openings in layer 113 using a standard wet etch process using H3PO4. These openings are where field regions will be formed which will separate from one another the electronic component devices to be formed. These field regions surround and so outline the feature regions in and below which the individual electronic component devices will be formed. MOS field-effect transistors having but a single source and single drain will be exhibited as being formed in the four feature regions shown in Fig. 3A.

Fig. 3B. Following the provision of the field region openings through layers 113 and 112, the exposed portions of layer 111 and the silicon below are subjected to an ion implantation step using phosphorus ions having an energy of 120 keV. This implantation occurs with a dose 10'3 ions/cm2. This implantation is used to adjust the field regions threshold, increasing this threshold to prevent MOS field-effect transistor action between adjacent electron component devices in adjacent feature regions. The implantation step forms an n±type conductivity region at approximately 100 nm below the surface of semiconductor 110.

The field regions are then oxidized by thermal growth through the openings in layers 113 and 112 by placing the structure at 975 C for ten hours in an oxygen atmosphere to form the field oxide 114. Concurrently, the original implanted ions in the field regions are driven deeper by diffusion into semiconductor material body 110. The result is shown in Fig.

3B where the original implanted phosphorus ions in the field regions have been driven to a depth of 1000nm and are designated 115.

Fig. 3C. Without further masking, the remnants of silicon dioxide layer 113 are then etched away using buffered HF. No masking is required because layer 113 is much thinner than field oxide 114 and the simultaneous etching thereof with the etching away of layer 113 does not remove too much of regions 114, which as a result of this etching are redesignated 114'. Then all of silicon nitride layer 11 2 is stripped away by etching with H3PO4.

Next, a photoresist layer having selected openings therein is provided over the surface of oxide layer 111 in a standard process.

These openings are made in this photo-resist layer to expose those portions of layer 111 over feature regions that are to have depletion mode devices formed therein, and are therefore to undergo an ion implantation to form a depletion mode region. The fabrication process illustrated by Fig. 3 will demonstrate making both ordinary MOS field-effect transistors and high breakdown voltage MOS fieldeffect transistors. In addition, one ordinary MOS field-effect transistor will be an enhancement mode and the other will be a depletion mode. These same alternatives will be shown for the high breakdown voltage MOS fieldeffect transistors.

After the openings are provided in the photoresist on layer 111, an ion implantation step is performed using boron ions having energy of 100 keV with a dose used of from.5 to 4.0 X 1 Of 2 ions/cm2 which results in a depletion mode region having a pn junction occurring at approximately 300nm below the sl r- face of semiconductor 110. The results are shown in Fig. 3C where the photoresist layer is designated 116. The resulting depletion implant region in the high breakdown voltage MOS field-effect transistor is designated 117 while the depletion mode region for the ordinary MOS field-effect transistor is designated 118.

Fig. 3D. After completing the depletion mode region implant step, photoresist 116 is stripped away. Then, the device is annealed by placing the structure at 975 C for a half hour. Thereafter, silicon dioxide layer 111 is also etched away using buffered HF. Etching of layer 111 occurs without further masking because, again, the field-oxide regions 114' are relatively thick. The etching does remove a part of the field oxide regions and so these are now redesignated 114".

Next, a gate oxide is thermally grown by placing the structure at 975 C in an oxygen atmosphere containing 4% HCI until the gate oxide thickness reaches somewhere between 100 and 250nm with the thickness chosen depending on the design for the device being fabricated in light of its planned utilization.

Then, 500nm of phosphorus doped polysilicon doped to have a sheet resistance of 50 ohms/square is deposited in a standard chemical vapor deposition process. Of course, undoped polysilicon could have been deposited and then implanted with a dopant to make it high conductive. After the polysilicon deposition, silicon dioxide is deposited by a standard chemical vapor deposition process on the doped polysilicon to a depth of 400 nm. Finally, this silicon dioxide deposition is followed by providing a photoresist layer with a pattern of desired openings over the silicon dioxide by a standard process.

The openings in this last provded photore sist layer are made to occur in locations below which polysilicon gate region portions are not desired to be provided for the MOS fieldeffect transistors being formed. The silicon dioxide provided over the polysilicon is then etched using buffered HF through these openings in the photoresist followed by using a standard plasma etch process to remove the doped polysilicon where unwanted. This plasma etching is then followed by stripping away the photoresist by use of an etchant.

The result is shown in Fig. 3D, where the doped polysilicon is designated 119 as it remains to form the gates for each of the MOS field-effect transistors being fabricated.

The silicon dioxide remaining thereon, originally used as a mask for forming the polysilicon gates, is designated 120. The silicon dioxide layer used as the gate oxide separating the gates 119 from the major surface of semiconductor material body 110 is designated 130.

Also shown in Fig. 3D is the result of providing the lower conductivity terminating region portions, i.e., the lower conductivity portions of the source and drain regions, which is accomplished by implanting boron ions in semiconductor material body 110 using an energy of 100 keV and a dose of from 1012 to 1013 ions/cm2. The actual dose used in this range depends on the planned use for the device being formed. Both the field oxide regions 114" and polysilicon gates 119 with silicon oxide caps 120 are used as implantation masks. As a result, the implanted lower conductivity portions just provided are self aligned with the field oxide and the gates already provided in each of the MOS fieldeffect transistors being formed. The pn junction between the lower conductivity portions of the drain and source regions and other portions of semiconductor 110 extend to 300 m below its surface.

The implanted regions forming the lower conductivity portions of the source and drain regions, i.e., the terminating regions, of the high breakdown voltage enhancement mode MOS field-effect transistor are designated 121 and 122. The implant regions forming the lower conductivity portions of the terminating regions for the high breakdown voltage, depletion mode MOS field-effect transistor are designated 123 and 124. The implant depletion mode region for this transistor has been redesignated 117' in view of its being substantially narrowed to being just below gate region 119 for the device.

The regions resulting from the last implantation step located where the source and drain regions will occur for the ordinary enhancement mode MOS field-effect transistor are designated 125 and 126. Finally, the implanted regions located where the source and drain regions will occur for the ordinary depletion mode MOS field-effect transistor are designated to 127 and 128. Depletion mode region 118 has been redesignated 118' in view of its being substantially narrowed to being just below gate 11 9 for the ordinary depletion mode device.

Fig. 3E. As the next step, silicon dioxide is then provided over gate oxide 130 except where covered by polysilicon gates 119, over polysilicon gates 119 except for cover by gate caps 120, and over gate caps 120. This silicon dioxide is provided by first thermally growing 160nm of silicon dioxide on the exposed surfaces of semiconductor material body 110 and gates 119 by placing the structure in an oxygen atmosphere containing 4% HCI at 975 C for three hours followed by depositing on this structure 300nm of silicon dioxide containing 1 % phosphorus in a standard chemical deposition process. This structural arrangement is placed at 950 C for a half hour for "densification" of the silicon dioxide so provided.As a result, silicon dioxide appears all around gate regions 119 and so all this oxide, including gate oxide layer 130, is now generally designated by 130'.

At this point in the process, shield electrodes are provided through depositing in a standard chemical deposition process a polysilicon layer of 500nm thickness doped with phosphorus to the point of having a sheet resistance of 50 ohms/square. Of course, undoped polysilicon could be deposited which could later be doped by diffusion or ion implantation. Following this deposition, silicon dioxide is grown to a thickness of 100 nm on the doped polysilicon layer by placing the structure in an oxygen atmosphere at 975 C for one hour. This silicon dioxide deposition is followed by providing a photoresist layer having a desired pattern of openings on the deposited silicon dioxide using a standard process.These openings are provided in the photoresist layer at locations such that a subsequent introduction of dopants in semiconductor material body 110 below these openings will result in providing a higher conductivity terminating region portions, i.e., higher conductivity portions of the drain and source regions, of the high breakdown voltage transistor devices and the source and drain regions in the ordinary transistors. The higher conductivity terminating region portions are located to be entirely within the lower conductivity portions of these regions when viewed from the surface of semiconductor 110.

The silicon dioxide below these openings in the photoresist layer is etched away using buffered HF. Then the photoresist is stripped away. This silicon dioxide etching and photoresist stripping is followed by using a HF/HN03/CH3C0OH mixture in a 1:100:11 ratio through the openings in the silicon dioxide layer to etch concentric openings in the polysilicon layer. Note that none of this second polysilicon layer, provided for use as shield electrodes, will be requirled for use over the ordinary MOS field-effect transistors being fabricated in the two right hand feature regions in Fig. 3 since shield electrodes are not used in such electrical components. The photoresist layer is stripped away completely in these regions.

The results of these steps are shown in Fig.

3E where the remaining portions of the shield electrode polysilicon layer are designated 131. The silicon dioxide caps over these remaining shield polysilicon partions 131, used as masks during etching of the polysilicon, are designated 132.

Fig. 3F. Withe the openings through silicon dioxide layer 132 and polysilicon layer 131 complete, silicon dioxide layer 130' is now etched using buffered HF and using polysilicon shield electrodes 131 and silicon dioxide field regions 114" as etching masks. As a result, openings are provided in silicon dioxide layer 130' all the way to the major surface of semiconductor material body 110 beneath the openings appearing in the polysilicon shield electrodes 131. Openings also occur in the ordinary field-effect transistor feature regions adjacent to the field oxide regions 114" and adjacent to gate regions 11 9 for these devices, gate regions 119 becoming etching mask portions after the silicon dioxide over them is etched away. Concurrently, the silicon dioxide layer remnants are entirely removed as are portions of field oxide 114".Thus, parts of the lower conductivity regions 121, 122, 123 and 124 are exposed at the surface of semiconductor 11 0. All of the lower conductivity regions 125, 126, 127 and 128, located where the sources and drains of the ordinary transistors are to be formed as they intersect the surface of semiconductor 110 are exposed. The field oxide regions 114" are again redesignated 114"' because of the etching step removing parts of these regions.

Then an implantation step is performed to provide the higher conductivity terminating region portions for the high breakdown voltage, MOS field-effect transistors and to provide the complete source and drain regions for the ordinary MOS field-effect transistors. Boron ions having an energy of 100 keV are implanted using a dose of 4 X 1015 ions/cm2 followed by annealing the device at 950 C for a half hour. This is followed by thermally growing 100nm of silicon dioxide, through placing the structure in an oxygen atmosphere at 975 C for 1.5 hours, on the exposed surface portions of the major surface of semiconductor material body 110 and on polysilicon shield electrodes 131.On this thermally grown oxide there is then deposited 600 nm of silicon dioxide having a 6% phosphorus therein in a standard chemical vapor deposition process. Following this, the ion implanted regions just provided are caused to diffuse deeper into semiconductor material body 110 by placing the device at 1025 C for 2.5 hours. The pn junction resulting from this diffusion reach approximately 1500 m below the major surface of semiconductor material 110. The earlier provided depletion mode regions 117' and 118' and the earlier provided lower conductivity terminating region portions 121, 122, 123 and 124 are forced deeper into semiconductor material body 110 by this diffusion, all reaching approximately 400nm below the major surface of semiconductor material body 110.

The results of these steps are shown in Fig.

3F. Field oxide regions 114"' will be merged into the silicon dioxide layer provided after the last implantation step, as will the remaining portions of the silicon dioxide 130' around gates 119. The new layer of silicon dioxide, provided after the last implantation step, is designated 133 and this will be the general designation for the merged structure.

The higher conductivity portions of the terminating regions, i.e., of the drain and source regions, for the high breakdown voltage, enhancement mode MOS field-effect transistor have been designated 134 and 135. The lower conductivity terminating region portions have been redesignated 121' and 122' in view of the central portion of them having been transformed by the presence of regions 134 and 135 and because of the greater depth these lower conductivity regions have now reached.

The higher conductivity terminating region portions of the high breakdown voltage, depletion mode MOS field-effect transistor have been designated 136 and 137. The lower conductivity terminating region portions for this device have been redesignated 123' and 124' in view of the central portion of these lower conductivity regions having become part of the regions 136 and 137 and because of the greater depths reached by these lower conductivity terminating region portions. The depletion mode region has been redesignated 117" because theis region has reached a greater depth of semiconductor material body 110.

The terminating regions, i.e., the drain and source regions, for the ordinary enhancement mode MOS field-effect transistor have been redesignated 125' and 126' in view of the transforming of these regions from a p- conductivity to a p+ conductivity. The terminating regions for the ordinary depletion mode MOS field-effect transistor have been redesignated 127' and 1 28' for the same reason.

The depletion mode region has been redesignated 118" in view of its greater depth this region has reached in semiconductor material body 110.

Fig. 3G. At this point, by a standard process, a photoresist layer is provided over layer 133 in which photoresist layer openings are provided which correspond to the desired lo cations for the external interconnection means to be provided. Silicon dioxide layer 133 is etched away using buffered HF beneath the openings provided in the photoresist layer.

The external interconnection means is chosen here to be of metal although such means could be provided by doped polysilicon. The metal chosen is a copper-aluminium alloy and is deposited in a standard evaporation process as a layer of 2000nm thickness. A photoresist layer is provided over this metal layer in which openings are provided, all done in a standard process, at locations where no metal is desired. H3PO4/HNO3/CH3COOH in a ratio of 50:1:5 is introduced as an etchant through these openings to remove the copperaluminium alloy layer at these locations.

Thereafter, an annealing step is performed at 450 C for 30 minutes. Finally, a passivating layer of silicon dioxide containing 1 % phosphorus is deposited on the device in a standard chemical vapor deposition process.

The results of these steps are shown in Fig.

16G. The merged or combined silicon dioxide layer 133 of Fig. 3F is now designated 133' as a portion has been removed therefrom to permit providing external interconnection means. The copper-aluminium alloy structures to form the external interconnection means have been designated 138 in Fig. 3G. The passivating layer over external interconnection structures 138 and over silicon dioxide 133' is designated 139.

The results shown in Fig. 3G indicate how there can be simultaneously formed in one monolithic integrated circuit chip high breakdown voltage MOS field-effect devices, both enhancement mode and depletion mode, and ordinary MOS field-effect devices, again both enhancement mode and depletion mode.

It will be seen that two self-alignment procedures have been used, in which ion implantation is carried out using masking structures on the semiconductor body which form parts of the conductive regions required in the final structure. This self-alignment procedure for minimizing the distance between the edge of the gate and the higher conductivity region portions helps to reduce the channel resistance when the FET is turned on.

Up to now, we have implicity assumed that the devices being considered have the simple structure of a source region and a drain region each of more or less compact shape, separated by a gate region which stretches between the source and drain. This construction is satisfactory when the power capacity of the transistor is irrelevant. However, if the transistor is intended for switching large amounts of power, e.g. for controlling an AC supply to some electromechanical device, then further considerations arise.

The basic problem is that the "on" resistance of a field-effect transistor is normally quite a bit higher than that of a bipolar transistor of the same size. It is therefore desirable to minimize this "on" resistance.

A first step to this end is to make the transistor with its source and drain as two parallel linear regions, with a narrow gate region between them. The "on" resistance Ron is approximately proportional to the aspect ratio L/w of the gate region, where L is the "length", or distance between the source and drain, and w is the width; in the construction just mentioned, L is of course much less than w.

For a high power FET, therefore, we need a gate region which is very wide and very short ~or, looking at it from the other aspect, very long and narrow. This involves taking up quite a bit of space on the chip, and a further objective therefore is to minimize the area occupied by the transistor. This means laying out the gate region so that the area taken up by the source and drain region bounding it are minimized. In fact, the objective is to minimize the on-resistance by device-area product Row A One way to improve the Row A product over the construction described above is to form a large number of parallel regions as alternate sources and drains, with a gate region between each. This results in each unit length of source or drain region having the associated amount of gate region doubled.

A further improvement of the Row A product can be achieved by constructing the source and drain regions as a regular array of square regions. The gate region is then formed by the square grid or lattice lying between the source and drain regions and having square holes in it for those regions. The square regions are alternately source and drain regions in both directions.

Another known arrangement for giving a good R0n.A product uses an array of hexagons for the source regions, with Y-shaped regions inserted at the places where 3 hexagons meet to form the drain regions.

We have found that, given normal practical constraints (such as tolerable interconnection resistances, etc.), the best arrangement for minimizing the Row A product is a triangular one. In its basic form, this consists of a closepacked array of equilateral triangles forming alternate source and drain regions, with the gate region consisting of the triangular-holed lattice between them.

A modification of this arrangement is to take the basic array of triangles as all source regions, and form a triangular border round each as a gate region, and the remaining triangular mesh or lattice forming the drain region. This construction enables the drain connections to consist of a series of parallel conductors running right across the structure.

Between each pair of drain electrodes, there is than a single line of triangular source-and-gate regions, with the triangles in each line being oriented in alternately "up" and "down" di rections.

A further modification is to join the apex of the gate region of each "up" triangle to the gate region of the adjacent two "down" tri angles so interconnecting all the gate regions of the line. This simplifies the problem of forming the interconnections to the gate regions.

Claims

1. An FET (field-effect transistor) comprising: a semiconductor body of one conductivity type having formed therein source and drain regions of the other conductivity type, with the region between the source and drain regions forming the gate region; an insulating layer over the surface of the semiconductor body, having apertures through which conductive connections are formed to the source and drain regions; gate electrode means in or on the insulating layer and over the gate regions; and shield electrode means formed in or on the insulating layer, encircling the conductive connections to the source and drain regions and being nearer to those connections that the gate electrode means and spaced further from the semiconductor body by the insulating layer than the gate electrode means.

2. An FET according to Claim 1, wherein the source and drain regions each comprise a main region and an inner region within the main region of higher conductivity than the main region and to which the connections are made.

3. An FET according to either previous claim, wherein the source and drain regions each comprise a main region with an annular region surrounding it at the surface of the semiconductor of lower conductivity than the main region.

4. An FET according to either of Claims 1 and 2, wherein the source and drain regions each comprise a main region with a circular region below it of lower conductivity than the main region.

5. An FET according to any previous claim, wherein the semiconductor body includes a threshold voltage adjust region, of lower conductivity than the bulk of the semiconductor body, in which the source and drain regions are formed.

6. An FET according to any previous claim, wherein the gate electrode means comprise two separate electrodes, one covering a portion of the gate region adjacent to the source and the other covering the remaining portion of the gate region, and each electrode is connected to the shield electrode around the connection to the corresponding source or drain region.

7. A circuit including an FET according to Claim 6, and gating circuitry operative to connect each gating electrode and its associated field electrode to the connection to the associated one of the source and drain connections when the FET is to be turned off and to a source of voltage exceeding the threshold voltage of the FET when the FET is to be turned on.

8. An FET according to any one of Claims 1 to 5, wherein the shield electrode means comprise a continuous conductive layer surrounding the connections to both the source and the drain.

9. An FET according to any one of Claim 1 to 5, wherein the shield electrode means are connected to the gate electrode means.

10. An FET according to Claim 9, wherein the gate electrode means are continuous with the shield electrode means.

11. A circuit comprising an FET according to any one of Claims 1 to 5 and 8, wherein the gate electrode means and the shield electrode means are distinct and the shield electrode means are connected to ground.

12. A circuit comprising an FET according to any one of Claims 1 to 5 and 8, wherein the gate electrode means and the shield electrode means are distinct and the shield electrode means are connected to a voltage exceeding the threshold voltage of the FET.

13. An FET according to any one of Claims 1 to 6 or 8 or 11, wherein the gate region is constructed as a triangular mesh separating a plurality of source and/or drain regions.

14. A method of making an FET according to Claim 2 or any claim dependent thereon, comprising the steps of (a) forming a first insulating layer on the surface of the semiconductor body, (b) providing a first gate electrode region on the insulating layer, (c) providing source and drain regions in the semiconductor body, (d) providing a second insulating layer over the gate electrode means, (e) providing shield electrode means on the second insulating layer extending beyond the gate electrode means, and (f) providing higher conductivity regions within the source and drain regions.

15. An FET substantially as herein described.

16. A circuit including a FET substantially as herein described.

17. A method of making an FET substantially as herein described.