JP2950025B2 - Insulated gate bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter, referred to as an IGBT) used as a high voltage, high current power switching element.

[0002]

2. Description of the Related Art An IGBT has a structure similar to that of a power MOSFET. However, by providing a pn junction in a drain region, conductivity modulation is caused in a high-resistance drain layer during operation. On-resistance can be achieved at the same time.

However, the withstand voltage of the guard ring structure at the element outer periphery, which is usually used as a means for increasing the withstand voltage, is n
Taking a channel IGBT as an example, the breakdown voltage is determined by the breakdown operation of the intrinsic pnp three-layer structure, and compared to a power MOSFET whose breakdown voltage is determined by the breakdown of the pn2 layer structure, it has a high-resistance drain layer having the same resistivity and thickness. In this case, the on-resistance is extremely small, but the breakdown voltage is low.
On the other hand, according to Japanese Patent Application Laid-Open No. 62-219667,
N ⁺ is added to the surface of the high-resistance drain layer 3 on the outer periphery of the IGBT element.
A structure is proposed in which a base region 15 is provided, and the n ⁺ base region 15 and the substrate p ⁺ region 2 are electrically shorted by an external wiring (see FIG. 4).

However, in this conventional configuration, it is necessary to provide a wire bonding electrode pad 14 for electrically short-circuiting the n ⁺ base region 15 and the p ⁺ drain layer 2 in the surface n ⁺ base region 15. The effective area serving as a passage is reduced. There is also a problem that the effect of increasing the breakdown voltage is not large.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and does not require a new electrode pad for the IGBT element and improves the withstand voltage of the guard ring portion without sacrificing on-resistance. Is provided.

[0006]

In the IGBT, a first semiconductor layer of a first conductivity type is formed from the drain electrode side, and a second semiconductor layer of a second conductivity type that causes conductivity modulation by carrier injection is formed thereon. The surface of the second semiconductor layer is selectively covered with the first
A conductive third semiconductor layer is formed, and a second conductive fourth semiconductor layer is selectively formed on a surface of the third semiconductor layer;
A gate electrode is formed on the surface of the third semiconductor layer between the second semiconductor layer and the fourth semiconductor layer via a gate insulating film, and a source electrode is formed from the surface of the third semiconductor layer to the surface of the fourth semiconductor layer. I have.

[0007] In order to achieve the above object, an IGBT of the present invention is provided.
With respect to a second semiconductor layer in a region (hereinafter referred to as a B region) extending from an edge of a region (hereinafter, referred to as an A region) in which a plurality of the third and fourth semiconductor layers are arranged (hereinafter, referred to as a B region). Only in a peripheral region including the formed guard ring breakdown voltage structure, a means for selectively shortening the life of minority carriers in the second semiconductor layer is provided.

More specifically, a crystal defect is formed in the second semiconductor layer in the B region for the purpose of shortening the life of minority carriers. Another structure is such that a sixth semiconductor layer of the second conductivity type containing impurities at a higher concentration than the second semiconductor layer is provided at or near the boundary surface between the second semiconductor layer and the first semiconductor layer in the B region. It is what you are doing.

[0009] Still another configuration of the present invention is the second region of the B region.
A crystal defect is formed in the semiconductor layer, and a sixth semiconductor layer of the second conductivity type is provided at or near the boundary between the second semiconductor layer and the first semiconductor layer.

[0010]

Operation and effect The operation and effect achieved by the above configuration will be described below. Consider a situation in which a voltage is applied between the drain electrode and the source electrode, the pn junction formed by the third semiconductor layer and the second semiconductor layer is in a reverse bias state, and the depletion layer spreads in the high-resistance second semiconductor layer. Here, in the region A, in the adjacent third semiconductor layer and the second semiconductor layer region located therebetween, a depletion layer extends from the adjacent third semiconductor layer to the second semiconductor layer located therebetween, and overlaps with each other. Mitigation is achieved. And it takes the maximum of the electric field value E _A at the pn junction of the bottom portion of the third semiconductor layer. On the other hand, at the edge of the region A where the repetitive arrangement of the third semiconductor layer ends, the above-mentioned electric field relaxation effect is lost, and the maximum electric field value at the corner of the third semiconductor layer at the edge or the surface of the second semiconductor layer near the third semiconductor layer. take the E _B. Here for the general E _A <E _B, like descending avalanche than A area B area occurs first,
The breakdown voltage of the element is determined by the breakdown voltage of the B region. Therefore in order to increase the breakdown voltage of the device, in order to reduce the maximum electric field E _B of region B, first from the edge of the third semiconductor layer which is repeatedly arranged 2
A withstand voltage structure is provided in a region B reaching the peripheral edge of the semiconductor layer. Generally, a guard ring structure is used to improve the withstand voltage of the element. Here, the guard ring withstand voltage of the IGBT is A
The withstand voltage BV _{CEO of the} bipolar transistor inherent in the source electrode, the third semiconductor layer, the second semiconductor layer, the first semiconductor layer, and the drain electrode at the edge of the region. Therefore, the breakdown voltage BV of the pn junction composed of the third semiconductor layer and the second semiconductor layer
_The breakdown voltage is lower than _CBO . This phenomenon is explained by the following equation.

[0011]

[ _Equation 1] BV _CEO = BV _CBO / (1 + β) ^{1 / n}

[0012]

[Mathematical formula-see original document] β = γ · α _T / (1−γ · α _T ) Equations 1 and 2 are extracted from “Basics of Semiconductor Devices”, (published by McGraw-Hill, translated by Yasuo Tarui), p. It was done.

From equation (1), the breakdown voltage BV _CEO due to the avalanche of the guard ring due to the influence of the current amplification factor β of the bipolar transistor due to the operation of the intrinsic bipolar transistor at the time of the breakdown causes the breakdown due to the avalanche of the pn junction. A phenomenon that the voltage is further lowered than the down voltage BV _CBO occurs. Here, by decreasing the β value of the intrinsic bipolar transistor in the B region, the BV _CEO can be brought closer to the BV _CBO to improve the guard ring breakdown voltage.

In the present invention, a crystal defect for shortening the life of minority carriers is formed in the second semiconductor layer from the edge of the region A to the region B. As a result, the minority carrier arrival rate α _T of the intrinsic bipolar transistor in the guard ring region
(Also referred to as transport efficiency), thereby decreasing the β value, as shown in Equation 2, resulting in an increase in the value of BV _CEO .

Next, the operation and effect of another configuration of the present invention will be described. By providing a sixth semiconductor layer of the second conductivity type containing impurities at a higher concentration than the second semiconductor layer at or near the boundary surface between the second semiconductor layer and the first semiconductor layer in the B region, the first bipolar transistor of the intrinsic bipolar transistor is provided. Injection of minority carriers from the semiconductor layer is suppressed. That is, the injection efficiency γ of the intrinsic bipolar transistor is reduced and
The current amplification factor β decreases, and as a result, BV _CEO increases.

[0016] Still another structure, that is, formation of crystal defects in the second semiconductor layer in the B region, and formation of the second semiconductor layer and the first semiconductor layer.
If the formation of the sixth semiconductor layer at or near the boundary surface of the semiconductor layer is performed in combination, the current amplification factor β can be reduced by reducing both the arrival rate α _T and the injection efficiency γ of the intrinsic bipolar transistor in the B region. Extra small BV
_CEO increase is achieved.

In the structure described above, it is not necessary to form a new electrode pad on the element surface to reduce the area of the region A, which is the cell region, and to further reduce the current amplification factor β of the intrinsic bipolar transistor in the region B. Only in this case, there is no decrease in the current amplification factor of the intrinsic bipolar transistor in the region A, and there is no increase in the resistance in the ON state. Therefore, the withstand voltage of the guard ring can be improved without increasing the on-resistance of the element.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to an embodiment shown in the drawings. In the embodiment, a case of an n-channel IGBT using p-type as the first conductivity type and n-type as the second conductivity type will be described.

FIG. 1 is a circuit diagram showing an I-type semiconductor device according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a unit cell portion (A region) and a guard ring portion (B region) of the GBT element. This will be described according to the manufacturing process.

First, the p ⁺ drain layer 2 as a semiconductor substrate
(First semiconductor layer) is prepared, and a high-resistance n ⁻ drain layer 3 is formed thereon by a vapor phase growth method or a wafer direct bonding method.
Forming the (second semiconductor layer) at a predetermined impurity concentration N _D and thickness t _e. Next, a p-well layer 4a (which forms a part of the third semiconductor layer), a p-layer 10 and a p-layer 4 'are formed at a depth of 3 to 6 [mu] m simultaneously by a selective diffusion method. Here, the p layer 10 is a guard ring formed for the purpose of increasing the breakdown voltage, and the p layer 4 'is a removal layer for removing excess carriers to the source electrode. Further, the p-channel layer 4b is overlapped with the p-layer 4a, and the p-channel layer 4a and the p-channel
An n ⁺ source layer 5 (fourth semiconductor layer) is formed in the layer (third semiconductor layer). In the above manufacturing process, n ⁻
Using a gate electrode 7 formed on a gate oxide film 6 formed by oxidizing the surface of the drain layer 3 as a mask, a so-called DSA technique (Diffusion Self Al
The p-channel layer 14b and the n ⁺ source layer 5 are formed in a self-aligned manner, thereby forming a channel.

Thereafter, in order to form an interlayer insulating film 8 and subsequently to form an ohmic contact with the p layer 4 and the n ⁺ layer 5, contact holes are opened in the gate oxide film 6 and the interlayer insulating film 8, and aluminum is formed. Is deposited by several μm and selectively etched to form a source electrode 9 and a gate electrode pad (not shown). Then, a metal film is deposited on the back surface of the p ⁺ drain layer 2 to form the drain electrode 1.

Further, a metal mask (for example, a stainless steel mask) is used to selectively form a guard ring region (region B).
For example, helium ions are implanted by ion implantation to form crystal defects in at least a part of the region (shown by oblique lines) 13. Further, heat treatment for stabilizing the electrical characteristics of the device is performed.

In the guard ring region of the IGBT element thus configured, minority carriers injected from the emitter region (substrate p ⁺ layer 2) of the intrinsic bipolar transistor via the base region (n ⁻ region 3) The amount reaching the collector region (p ⁺ layer 10) is reduced, thereby reducing the current amplification factor β as shown in the above equation (2), and as a result, the breakdown voltage BV _CEO of the guard ring region is reduced.
Is improved.

In addition, the formation of crystal defects is not only the above He ^{+ but also}
It is also possible by implanting Ar ions or H ⁺ ions, or by irradiating an electron beam or a neutron beam. FIG. 2 shows the structure of the second embodiment. The difference from FIG. 1 is that an n ⁺ layer 11 is selectively formed near the substrate pn junction 12 in the guard ring region (region B). The n ⁺ layer 11 selectively diffuses impurities on the surface of the p ⁺ layer 2 which is a semiconductor substrate, or selectively forms the n ⁻ layer on the surface of the p ⁺ layer to a certain thickness and then selectively diffuses impurities on the surface. Thereafter, by performing the manufacturing process shown in FIG. 1, it can be formed in the vicinity of the substrate pn junction 12.

In the guard ring region of the IGBT element thus configured, minority carriers (holes) are injected from the emitter region (substrate p ⁺ layer 2) of the intrinsic bipolar transistor into the base region (n ⁻ layer 3). As a result, the current amplification factor β shown in Expression 2 decreases, and as a result, the breakdown voltage BV _{CEO in the} guard ring region increases.

Further, the first and second embodiments may be combined as in the third embodiment shown in FIG. According to the present embodiment, the base region (n) of minority carriers injected from the emitter region (substrate p ⁺ layer 2) of the intrinsic bipolar transistor in the guard ring region (region B).
⁻ Region 3), the amount reaching the collector region (p ⁺ layer 10) is reduced, and the emitter region (substrate p)
The injection of minority carriers (holes) from the ⁺ layer 2) to the base region (n ⁻ layer 3) is suppressed, and as a result, the current amplification factor β shown in the above equation 2 is drastically reduced, and the breakdown voltage of the guard ring region is reduced. BV _CEO can be further increased.

In the various embodiments described above, an example was described in which a p-type is used as the first conductivity type and an n-type is used as the second conductivity type. However, a p-channel type IGB in which these conductivity types are reversed is used.
The present invention is also effective at T.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a cell region and an outer peripheral guard ring region of an IGBT according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view of a cell region and an outer peripheral guard ring region of an IGBT according to a second embodiment of the present invention.

FIG. 3 is a sectional structural view of a cell region and an outer guard ring region of an IGBT according to a third embodiment of the present invention.

FIG. 4 is a sectional structural view of a cell region and an outer peripheral guard ring region of a conventional IGBT element.

[Explanation of symbols]

Reference Signs List 1 drain electrode 2 P ⁺ layer (first semiconductor layer) 3 n ⁻ layer (second semiconductor layer) 4 p layer (third semiconductor layer) 5 n ⁺ layer (fourth semiconductor layer) 6 gate insulating film 7 gate electrode 9 Source electrode 10 P layer (fifth semiconductor layer) 11 n ⁺ layer (sixth semiconductor layer) 12 Substrate pn junction 13 Lifetime killer formation region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 21/265

Claims (5)

(57) [Claims] A first drain layer of a first conductivity type; a second drain layer of a second conductivity type in contact with an upper surface of the first drain layer; and a second drain layer formed in a region of the second drain layer. (2) a first conductivity type semiconductor layer formed on the surface of the drain layer, an insulated gate structure using the second conductivity type semiconductor layer formed in the first conductivity type semiconductor layer as a channel layer and a source layer, respectively; A guard ring structure of the first conductivity type formed in a peripheral region surrounding one region of the second drain layer; and first and second drain layers and a guard ring structure of the peripheral region selectively set only in the peripheral region. Means for reducing the current amplification factor of the bipolar transistor comprising: 2. A first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer; and a second semiconductor layer formed in the second semiconductor layer. A third semiconductor layer of the first conductivity type partially formed on the surface of the layer so that the junction is terminated; and a junction formed on the third semiconductor layer and terminated on the surface of the third semiconductor layer. A fourth semiconductor layer of a second conductivity type partially formed as described above, and a gate insulating film formed on at least the channel region using the third semiconductor layer between the second semiconductor layer and the fourth semiconductor layer as a channel region. A source electrode having contact portions in both the third semiconductor layer and the fourth semiconductor layer; and a source electrode outside a region where a plurality of the third and fourth semiconductor layers are arranged. Formed in the second semiconductor layer in the two semiconductor layers An insulated gate bipolar transistor including a peripheral region including a guard ring structure including a fifth semiconductor layer of the first conductivity type, and a drain electrode for supplying a drain current through the first semiconductor layer. Minority carriers selectively formed in or near the second semiconductor layer from the edge portions of the disposed third and fourth semiconductor layers to the peripheral edge portion of the second semiconductor layer, and to the second semiconductor layer. An insulated gate bipolar transistor, comprising means for limiting the amount of injected Si or shortening the life of minority carriers in the second semiconductor layer. 3. The insulated gate bipolar transistor according to claim 2, wherein the means for limiting the amount of minority carriers injected into the second semiconductor layer is a defect formed by ion implantation. 4. A means for limiting the amount of minority carriers injected into the second semiconductor layer, wherein the means extends from an edge of the third and fourth semiconductor layers to a peripheral edge of the second semiconductor layer. 3. The semiconductor layer according to claim 2, wherein the semiconductor layer is a sixth semiconductor layer of a second conductivity type having an impurity concentration higher than that of the second semiconductor layer and formed at or near a bonding surface between the semiconductor layer and the first semiconductor layer. Insulated gate bipolar transistor. 5. A means for limiting the amount of minority carriers injected into the second semiconductor layer, wherein the means for limiting the amount of minority carriers injected from the edge of the third and fourth semiconductor layers to the peripheral edge of the second semiconductor layer, The sixth semiconductor layer of a second conductivity type having a higher impurity concentration than that of the second semiconductor layer and formed at or near a bonding surface between the semiconductor layer and the first semiconductor layer. Insulated gate bipolar transistor.