JPH03166766A - Insulated-gate bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To optimize trade OFF relationship between an ON resistance and turing OFF time by irradiation with an ionized radioaction-ray such as of an ion beam, by providing crystal defects in protrusions of the uneven junction surface of first and second semiconductor layers. CONSTITUTION:Life time is so controlled that a light ion beam 50 is applied so that its range is disposed in the vicinity of the center in a P<+> type collector region 20 (indicated by a broken line in the drawing) and a crystal defect is contained in a P<+> type collector region 20 and an N<-> type base layer 2' of a depth part formed with the region 20. In this case, a PNP transistor to be controlled by ON/OFF of a MOSFET (field-effect transistor) 12 is composed of a parallel connection of a PNP transistor 11a having a P-well region 3, an N<-> type base layer 2' having no crystal defect and a P<+> type collector region 20 having a crystal defect and a P<+> type collector layer 1, and a PNP transistor 11b having a P-well region 3, an N<-> type base layer 2 having a crystal defect on the rear, and a P<+> type collector layer 1. Thus, trade OFF relationship between an ON resistance and turning OFF time can be optimized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate bipolar transistor (Insulated gate bipolar transistor).
Sulated Gate Bipolar Tran
The present invention relates to slstor (hereinafter referred to as ``GBT''), and particularly relates to improving the trade-off relationship between turn-off time and on-resistance associated with lifetime control.

[Conventional technology]

In general, bipolar transistors have a problem of low output impedance but low input impedance, and conversely, field effect transistors have high input impedance but also have a problem of high output impedance.

The IGET is intended to be integrated to compensate for the drawbacks of these various transistors, and to achieve high input impedance and low output impedance.

In other words, a bipolar transistor and a field effect transistor (MOSFET) are integrated, and the MOSFET is turned on by creating a highly concentrated impurity diffusion layer with a conductivity type different from that of the substrate on the back side of the substrate on which the MOSFET is formed. The current generated by this is injected into the base region of the bipolar transistor, and the bipolar transistor is controlled by the injected current.

Generally, an IGBT device consists of a large number of IGBT elements (hereinafter referred to as IGBT elements).
It has a structure in which cells (referred to as ET cells) are connected in parallel.

FIG. 7 is a sectional view showing the structure of a conventional n-channel type IGBT cell, and FIG. 8 is a circuit diagram showing its equivalent circuit.

In FIG. 7, 1 is a P collector layer, and an N 2 epitaxial layer 2 is formed on one main surface.

In a part of the surface of the N epitaxial layer 2, a P-well region 3 is formed by selectively diffusing P-type impurities, and in a part of the surface of this P-well region 3, a high concentration N emitter region 4 is formed by selectively diffusing N type impurities. A gate insulating film 5 is formed on the surface of the P well region 3 sandwiched between the surface of the N epitaxial layer 2 and the surface of the N ivy region 4, and this gate insulating film 5 is formed between adjacent IGBT cells. It is also formed on the surface of the N-evitaxial layer 2 so as to be integrated. A gate electrode 6 made of polysilicon, for example, is formed on the gate insulating film 5, and an emitter electrode made of a metal such as aluminum is formed to be electrically connected to both the P well region 3 and the N well region 4. 7 is formed. Note that the gate electrode 6 and the emitter electrode 7 have a multilayer structure with an insulating film 8 interposed therebetween, so that the entire IG
It has a structure in which it is electrically connected in common to the BT cells. A metal collector electrode 9 is integrally formed on the back surface of the P collector layer 1 for all IGBT cells.

The vicinity of the surface of the P well region 3 sandwiched between the N epitaxial layer 2 and the N vine region 4 has an n channel MOS structure, and by applying a positive voltage to the gate electrode 6 through the gate terminal G, Electrons flow from the N-shaped region 4 to the N-epitaxial layer 2 through a channel formed near the surface of the P-well region 3 directly under the gate electrode 6 .

■ indicates the electron current flowing in this way. On the other hand, from the eP collector layer 1, holes, which are minority carriers, are transferred to N
Injected into the epitaxial layer 2, part of it recombines with the electrons and disappears, and the rest flows through the P well region 3 as a hole current Ih. In this way, the IGBT basically operates in a bibolar manner, and the conductivity of the N epitaxial layer 2 increases due to the effect of conductivity modulation, resulting in a lower on-voltage and larger current capacity than conventional power MOS. It has the advantage of being able to achieve

In addition, in FIG. 8, 10 is N.Evitaxial layer 2
, P-well region 3 and N-type transistor; 11 is P-type collector layer 1,
A PNP transistor consisting of an N epitaxial layer 2 and a P well region 3, 12 an NMOS transistor whose channel region is the surface of the P well region 3 under the gate electrode 6, RB a diffused resistance of the P well region 3, and RLo a PN transistor.
P } indicates the on-resistance of the transistor 11.

Although the IGBT has the above-mentioned advantages, it has the disadvantage that the operating frequency cannot be increased because the hole current Ih decreases more slowly at turn-off than in a field effect transistor or the like. This is because when the PNP transistor 11 is in the on state, the N epitaxial layer 2, which is its base region, is filled with electrons and holes, and when the MOS transistor 12 is turned off, electrons are transferred to the N epitaxial layer 2. This is because even if the injection of holes is blocked, holes do not suddenly decrease due to their low mobility.

In order to shorten this turn-off time, two methods are known. One is to use heavy metal atoms such as gold and platinum as so-called lifetime killers to reduce PNP.
This is a means of introducing N into the N-epitaxial layer 2, which is the base region of the transistor 12, and this lifetime killer becomes a recombination center for electrons and holes in the N-epitaxial layer 2, and removes these carriers within a short time. to disappear.

The other is an electron beam. This is a means of irradiating radiation such as gamma rays, neutron beams, and various ion beams. Since these radiations introduce deep trap levels into the N-evitaxial layer 2, these trap levels cause recombination with carriers. Since it is the center, carriers can be annihilated within a short time during turn-off. These techniques are called lifetime control techniques and are applied to various elements such as thyristors and power diodes.

In general, lifetime control technology using radiation irradiation has yielded better results than heavy metal diffusion in terms of controllability and reproducibility. However, during radiation irradiation, electron beams,
In methods using gamma rays and neutron beams, the irradiation generates trap levels in the N-evitaxial layer 2, and at the same time changes the film quality of the gate oxide film 5, resulting in a change in the threshold value as well. , there is a problem that reduces its operational reliability. This problem can be solved by a method of irradiating various ion beams such as protons from the collector electrode 9 side.

That is, as shown in FIG. 7, various light ion beams 50 such as protons are irradiated from the side where the collector electrode 9 is formed, and the range position is set in the N-evitaxial layer 2. (shown by the broken line in FIG. 7), by adjusting the acceleration energy, the gate insulating film 5 and other
Lifetime control can be performed without any influence on each layer 3.4 formed on the emitter side.

Furthermore, as shown in Fig. 9, crystal defects (mainly vacancies) due to irradiation with various ions such as protons occur intensively in the half-width W of the defect distribution peak around the range D, and other It has characteristics that do not have much influence on location.

By utilizing this characteristic, it is possible to perform lifetime control with high controllability. For example, JP-A-6
4-19771, the P collector region (
Range D is within the N base region (corresponding to N-evitaxial layer 2 in Figure 7) close to P (corresponding to collector layer 1 in Figure 7).
By setting , effective lifetime control can be performed. This is because the base region near the MOSFET plays an important role in causing conductivity modulation triggered by carriers injected from the MOSFET channel, so creating crystal defects in this region will increase the on-resistance. Therefore, P which is farthest from the channel region of the MOSFET and N″″ closest to the collector region
This is because it is desirable that the range of the ion beam be within the base region. Furthermore, it is effective to generate crystal defects in a concentrated manner in the N″″ base region near the P collector region in order to quickly capture the holes that are continuously injected until the initial stage of the off-operation.

[Problem to be solved by the invention]

However, all of the above-mentioned lifetime controls still generate crystal defects over the entire surface of the IGBT element.
``The resistance value of the epitaxial layer 2 inevitably increases, and I
The on-resistance RLc of the GBT increases. In other words, I
There is a trade-off relationship between the on-resistance and the turn-off time of the GBT, and there is a problem in that the trade-off relationship is not optimal at present.

This invention was made to solve the above problems, and it is an insulation structure that optimizes the trade-off relationship between on-resistance and turn-off time by lifetime control using irradiation with ionizing radiation such as ion beams. The purpose is to obtain a gate-type bipolar transistor.

[Means to solve the problem]

In the insulated gate bipolar transistor according to the present invention, first and second transistors are stacked so that their junction surfaces are uneven.
a first and second semiconductor layer of a conductivity type, a first semiconductor region of a first conductivity type selectively formed on a surface of the second semiconductor layer, and a surface of the first semiconductor region. a second semiconductor region of a second conductivity type selectively formed on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; an insulating film formed on the insulating film; a control electrode formed on the insulating film;
a first main electrode formed across the semiconductor region of the first semiconductor layer; and a second main electrode formed on the back surface of the first semiconductor layer; The structure is such that each convex portion of the concave and convex joint surface has a crystal defect.

Further, in the method for manufacturing an insulated gate bipolar transistor according to claim 2, a second semiconductor layer of a second conductivity type is formed on the first semiconductor layer of the first conductivity type so that the junction surface is uneven. selectively forming a first semiconductor region of a first conductivity type on the surface of the second semiconductor layer; Second
a step of selectively forming a semiconductor region of the first semiconductor region sandwiched between the semiconductor layer of the MS2 and the second semiconductor region;
forming an insulating film on the surface of the semiconductor region; forming a control electrode on the insulating film; and forming a first main electrode over the first and second semiconductor regions. and a step of forming a second main electrode on the back surface of the first semiconductor layer; and a step of forming a second main electrode on the back surface of the first semiconductor layer; irradiating smaller ionizing radiation from above the main surface on which the second main electrode is formed so that the range is near the center of the uneven joint surface.

[Effect]

In the insulated gate bipolar transistor according to the present invention, the bipolar transistor on the equivalent circuit which is a component thereof includes a first semiconductor region, a second semiconductor layer having no crystal defects, and a first semiconductor layer having crystal defects. Parallel connection of a first bipolar transistor made of a semiconductor layer and a second bipolar transistor made of a first semiconductor region, a second semiconductor layer having crystal defects, and a first semiconductor layer having no crystal defects. It can be regarded as equivalent if it is constructed by .

The first bipolar transistor has crystal defects in the first semiconductor layer but does not have crystal defects in the second semiconductor layer, so its advantage is that the on-resistance is low, and its disadvantage is that it has a long turn-off time. On the other hand, since the second bipolar transistor has crystal defects in the second semiconductor layer, its disadvantage is that its on-resistance is high, and its advantage is that its turn-off time is short.

Further, in the method for manufacturing an insulated gate bipolar transistor according to the present invention, the ionizing radiation is applied to the second semiconductor layer in which the range in which the generated crystal defects are distributed is smaller than the thickness of the uneven junction surfaces of the first and second semiconductor layers. Irradiation is applied from above the main surface on which the main electrode is formed so that the range is near the center of the uneven joint surface.

As a result, crystal defects are formed on the uneven junction surfaces of the first and second semiconductor layers. Therefore, in the same manner as the insulated gate bipolar transistor described above, a bipolar transistor on an equivalent circuit can be constructed by equivalently connecting the first and second bipolar transistors in parallel.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of an IGBT according to the present invention. In FIG. 1, 1 is a P collector layer, and on the other hand, on the main surface is an N-base layer 2 (N in FIG.
(corresponding to the epitaxial layer 2) is formed. This N-
A P-well region 3 is formed in a partial region of the surface of the base layer 2' by selectively diffusing P-type impurities;
Further, in a part of the surface of this P well region 3, an N+ emitter region 4 is formed by selectively diffusing highly concentrated N type impurities. On the other hand, N-base layer 2'
A P collector region 20 is selectively formed in a part of the back surface of the P collector region 20 . In other words, the joint surface between the base region and collector region of the IGBT of this embodiment is formed to be uneven.

A gate insulating film 5 is formed on the surface of the P well region 3 which is sandwiched between the surface of the N'' base layer 2' and the surface of the N4 vine region 4, and this gate insulating film 5 covers the adjacent IGB.
It is also formed on the surface of the N base layer 2' so as to be integrated between the T cells. A gate electrode 6 made of polysilicon, for example, is formed on the gate insulating film 5. Further, an emitter electrode 7 made of a metal such as aluminum is formed to be electrically connected to both the P well region 3 and the N well region 4. Note that the gate electrode 6 and the emitter electrode 7 have a multilayer structure with an insulating film 8 interposed therebetween, so that they are electrically connected in common to all IGBT cells. A metal collector electrode 9 is integrally formed on the back surface of the P+ collector layer 1 for all IGBT cells. That is, the parts other than the P+ collector region 20 of the IGBT according to this embodiment are the same as those of the conventional IGBT shown in FIG.
It has a similar structure to a BT, and therefore its basic operation is also similar to a conventional IGBT.

A light ion beam 50 is irradiated from the side of the collector electrode 9 of the IGBT having such a structure so that the range is located near the center of the P+ collector region 20 (indicated by a broken line in the figure) to eliminate crystal defects. is inside the P+ collector region 20 and N″″ base layer 2 at the depth where the P collector region 20 is formed.
Perform lifetime control to keep it within ′. When lifetime control is performed in this way, as shown in the equivalent circuit diagram of FIG. A PNP consisting of a base layer 2' and (a P+ collector region 20 with crystal defects + a P+ collector layer 1) } A PNP consisting of a transistor lla, a P well region 3, an N- base layer 2 having crystal defects on the back surface, and a P collector layer 1 }It can be considered that it is configured by parallel connection with transistor 1lb.

PNP} In transistor 1lb, the region of N-base layer 2' near P collector layer 1 is exposed to light ion beam 50
Since crystal defects are generated by the irradiation, the advantage is that the turn-off time is shortened, but the disadvantage is that the on-resistance RLC is high.

On the other hand, in the PNP transistor lla, crystal defects are formed in the P+ collector region 20 by irradiation with the light ion beam 50, but the P+ collector region 20 contains a high concentration of P type impurities and is a high conductivity region. Therefore, changes in electrical conductivity due to crystal defects can be ignored. Therefore, as a disadvantage, the turn-off time is not shortened, but as an advantage, the on-resistance does not increase due to irradiation with the light ions 50.

In the IGBT having such a configuration, the on-resistance in the on-state can be sufficiently reduced by the active operation of the PNP transistor lla whose on-resistance does not increase due to lifetime control. On the other hand, the turn-off time is determined by the PNP transistor 1 whose turn-off time is shortened by lifetime control.
It can be sufficiently shortened by actively working with lb.

In this way, by making the PNP transistors lla and 11b each function to compensate for each other's shortcomings,
The trade-off relationship between the on-resistance and turn-off time of the IGBT can be further improved. In other words, I.G.
The formation width of the P collector region 20 may be set so as to optimize the trade-off relationship between the on-resistance and turn-off time of the BT.

Note that, in order not to lower the on-resistance of the PNP transistor 11a, it is necessary to generate crystal defects only in the P collector region 2o where the P collector region 20 exists, as described above. Therefore, P collector area 2
The thickness of 0 is W. Then, it is necessary to select ions whose defect distribution peak half width W of the light ions irradiated so that the range is located at the center of the P collector region 20 is W and WG.

Figure 3 shows silica in hydrogen ions and helium ions. It is a graph showing the relationship between the average range D and the half width W of the defect distribution peak in a con. In a general IGBT, the thickness of the P collector layer 1 is approximately 270 μm, so the thickness W
In order to generate crystal defects only in the P collector region 20 where G is about 10 μm, it is necessary to implant helium ions instead of hydrogen ions. When the P collector region 20 is thick (WG>about 20 μm), hydrogen ions can be used. Although not shown in Fig. 3, ions heavier than helium ions have a defect distribution peak half width W
is smaller than helium ions, so it can be applied in place of helium ions.

Figures 4A to 4F show the first IGBT according to the above embodiment.
FIG. 2 is a cross-sectional view showing a manufacturing method. Note that the P well region 3 in this case is a first region with a relatively low impurity concentration and a shallow depth.
The first P well region 3a has a relatively high impurity concentration and a deep second P well region 3b formed in the center of the first P well region 3a.

First, as shown in FIG. 4A, an N base layer 2 serving as a substrate is prepared.
A P collector region 20 is formed by selectively diffusing P-type impurities into a part of the back surface region of . Then, as shown in FIG. 4B, a P collector layer 1 is epitaxially grown on the back surface of the N-base layer 2'.

Then, as shown in FIG. 4C, a mask 33 is formed by forming, for example, a silicon oxide film on the surface of the N-base layer 2' and patterning it. Then, by selectively ion-implanting P-type impurities such as boron into the N-base layer 2' through this mask 33 and further diffusing them, the surface concentration is 5X101B to IX1019.
A second P well region 3b having a thickness of about cm-3 is formed.

Next, as shown in FIG. 4D, mask 33 is removed and another mask 34 is formed. Then, by selectively ion-implanting P-type impurities such as boron into the N base layer 2' through this mask 34 and further diffusing them, a P-type impurity with a lower concentration and depth than the second P-well region 3b is formed. A shallow first P well region 3a is formed. In this way, the first P well region 3
A P-well region 3 is formed in which a second P-well region 3b is provided at the center of a.

Next, as shown in FIG. 4E, the mask 34 is removed and an oxide film and a polysilicon film are formed on the entire surface instead, and by patterning them, the gate insulating film 5, the gate electrode 6, and the polysilicon layer 6a are formed. form.

Next, by selectively diffusing N-type impurities such as phosphorus into the P-well region 3 using the gate electrode 6 and the polysilicon layer 6a as a mask, the N-type ivy region 4 is formed in a self-aligned manner.

Next, as shown in FIG. 4F, after removing the polysilicon layer 6a, an insulating film 8 is formed on the entire surface and then battered. Then, by forming a metal layer over the entire surface and patterning, the emitter electrode 7 electrically connected to the ivy region 4 and the gate extraction portion 37 electrically connected to the gate electrode 6 are formed. Thereafter, irradiation with the light ion beam 50 is performed according to the procedure described in connection with FIG.

5A to 5C show the second IGBT according to the above embodiment.
FIG. 2 is a cross-sectional view showing a manufacturing method.

First, as shown in FIG. 5A, an N base layer 2 serving as a substrate is prepared.
A P collector region 20 is formed by selectively diffusing P-type impurities into a part of the back surface region of .

Furthermore, as shown in FIG. 5B, by depositing and diffusing P-type impurities on the entire back surface of the N'' base layer 2', a thin P diffusion layer 21 is formed on the back surface of the N- base layer 2'. Form.

Next, the P substrate 22 is prepared, and as shown in FIG. 5C,
The surface of this P substrate 22 and the P diffusion layer 21 are bonded,
A P collector layer 1 consisting of a P diffusion layer 21 and a P substrate 22 is formed. The method of bonding the P+ diffusion layer 21 and the P substrate 22 is as follows: "UDC l121.382.3"
3! l. 34.028.027,5”, the paper by Akio Nakagawa et al. “Bibolar type M using Sl direct bonding technology”
OSFETJ, Institute of Electrical Engineers of Japan Study Group, Electronic Devices, Semiconductor Power Conversion Joint Study Group Materials “EDD-89-4”
2 8PC-89-51” Masanobu Ogino’s paper “
There are bonding methods disclosed in ``Current status of wafer bonding technology and its applications'' and the like.

The subsequent manufacturing method is the same as the first manufacturing method, so a description thereof will be omitted.

6A and 6B show the third IGBT according to the above embodiment.
FIG. 2 is a cross-sectional view showing a manufacturing method.

First, as shown in FIG. 6A, by selectively diffusing N-type impurities into a part of the surface region of the P substrate 23,
N diffusion region 24 is formed.

Then, as shown in FIG. 6B, an N 2 epitaxial layer 25 is epitaxially grown on the surface of the P 2 substrate 23. When manufactured in this manner, the N-base layer 2' of FIG.
is formed, and P in the N diffusion region 24 is not formed.
The surface area of the substrate 23 becomes the P collector region 20 in FIG. 1, and the remaining area of the P substrate 23 becomes the P collector layer 1 in FIG.

Since the subsequent manufacturing method is the same as the first manufacturing method,
Explanation will be omitted. Note that although the IGBT manufactured by the third manufacturing method has a high concentration in the back surface region of the N-base layer 2', this does not adversely affect the operation of the IGBT.

〔Effect of the invention〕

As explained above, according to the IGBT according to claim 1, the bipolar transistor on the equivalent circuit that is a component thereof has a first semiconductor region, a second semiconductor region having no crystal defects, and a second semiconductor region having no crystal defects.
a first bibolar 1 to transistor consisting of a semiconductor layer and a first semiconductor layer having crystal defects, a first semiconductor region, a second semiconductor layer having crystal defects, and a first semiconductor having no crystal defects; It can be equivalently considered to be configured by a parallel connection with a second bipolar transistor consisting of two layers.

The first bipolar transistor has crystal defects in the first semiconductor layer but does not have crystal defects in the second semiconductor layer, so its advantage is that the on-resistance is low, and its disadvantage is that it has a long turn-off time. On the other hand, since the second bipolar transistor has crystal defects in the second semiconductor layer, its disadvantage is that its on-resistance is high, and its advantage is that its turn-off time is short.

Therefore, by setting the uneven junction surfaces of the first and second semiconductor layers so as to optimally compensate for the shortcomings of the first bipolar transistor and the second bipolar transistor, it is possible to reduce the This has the effect of optimizing the trade-off relationship between on-resistance and turn-off time.

Further, according to the method for manufacturing an IGBT according to claim 2,
Ionizing radiation in which the range in which crystal defects are distributed is smaller than the thickness of the uneven junction surface of the first and second semiconductor layers,
Irradiation is applied from above the main surface on which the second main electrode is formed so that the range is near the center of the uneven joint surface. This allows the first
And crystal defects are formed on the uneven junction surface of the second semiconductor layer. Therefore, in the same manner as the insulated gate bipolar transistor described above, a bipolar transistor on an equivalent circuit can be constructed by equivalently connecting the first and second bipolar transistors in parallel.

Therefore, by forming the uneven junction surfaces of the first and second semiconductor layers so as to optimally compensate for the respective shortcomings of the first bipolar transistor and the second bipolar transistor. This has the effect of optimizing the trade-off relationship between on-resistance and turn-off time due to irradiation with ionizing radiation such as ion beams.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing an IGBT which is an embodiment of the present invention, Fig. 2 is its equivalent circuit diagram, and Fig. 3 shows the relationship between the range and the half-width of the defect distribution peak for hydrogen ions and helium ions. The graph shown in Figure 4 is the IGB shown in Figure 1.
5 is a sectional view showing the second manufacturing method of the IGBT shown in FIG. 1, and FIG. 6 is a sectional view showing the third manufacturing method of the IGBT shown in FIG. FIG. 7 is a cross-sectional view showing a conventional IGBT, FIG. 8 is an equivalent circuit diagram thereof, and FIG. 9 is a graph showing a crystal defect distribution generated by ion irradiation. In the figure, 1 is a P+ collector layer, 2' is an N base layer,
3 is a P well region, 4 is an N-type ivy region, 5 is a gate insulating film, 6 is a gate electrode, 7 is an emitter electrode, 8 is an insulating film, 9 is a collector electrode, 20 is a P collector region, 50
is a light ion beam. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) First and second semiconductor layers of first and second conductivity types stacked such that their bonding surfaces are uneven, and a first semiconductor layer selectively formed on the surface of the second semiconductor layer. a first semiconductor region of a conductivity type; and a second semiconductor region selectively formed on a surface of the first semiconductor region.
a second semiconductor region of a conductivity type; an insulating film formed on a surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; a control electrode formed on the first semiconductor layer; a first main electrode formed on the first and second semiconductor regions; and a second main electrode formed on the back surface of the first semiconductor layer. An insulated gate bipolar transistor, characterized in that the first and second semiconductor layers have a crystal defect in each convex portion on the junction surface of the concave and convex portions. (2) The first conductivity type is
a step of laminating a second semiconductor layer of a second conductivity type on the semiconductor layer; and a step of selectively forming a first semiconductor region of the first conductivity type on the surface of the second semiconductor layer. selectively forming a second semiconductor region of a second conductivity type on the surface of the first semiconductor region; and a step of selectively forming a second semiconductor region of a second conductivity type on a surface of the first semiconductor region; forming an insulating film on the surface of the first semiconductor region; forming a control electrode on the insulating film; and forming a first main electrode over the first and second semiconductor regions. a step of forming a second main electrode on the back surface of the first semiconductor layer; and a step of forming a second main electrode on the back surface of the first semiconductor layer;
irradiating ionizing radiation smaller than the thickness of the uneven bonding surface of the semiconductor layer from above the main surface on which the second main electrode is formed such that the range is near the center of the uneven bonding surface; A method for manufacturing an insulated gate bipolar transistor with