JPH0786580A - High-voltage semiconductor device - Google Patents
High-voltage semiconductor deviceInfo
- Publication number
- JPH0786580A JPH0786580A JP5231281A JP23128193A JPH0786580A JP H0786580 A JPH0786580 A JP H0786580A JP 5231281 A JP5231281 A JP 5231281A JP 23128193 A JP23128193 A JP 23128193A JP H0786580 A JPH0786580 A JP H0786580A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- breakdown voltage
- resistance
- withstand voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000015556 catabolic process Effects 0.000 claims description 44
- 238000009792 diffusion process Methods 0.000 claims description 11
- 238000009413 insulation Methods 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000000926 separation method Methods 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳＦＥＴからなる
高耐圧半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device composed of a MOSFET.
【０００２】[0002]
【従来の技術】近年、コンピュータや通信機器の重要部
分には、多数のトランジスタや抵抗等を電気回路を達成
するようにむすびつけ、１チップ上に集積化して形成し
た集積回路（ＩＣ）が多用されている。このようなＩＣ
中で、高耐圧素子を含むものはパワーＩＣと呼ばれてい
る。パワーＩＣの中でも駆動回路と制御回路とが一体化
されたものは、ディスプレー駆動装置や車載用ＩＣ等、
多くの用途に用いることができる。この種のパワーＩＣ
の出力段に用いられるＭＯＳＦＥＴには、高いドレイン
耐圧と低いオン抵抗が要求される。2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and forming them on one chip has been widely used in important parts of computers and communication equipment. ing. IC like this
Among them, a device including a high breakdown voltage element is called a power IC. Among the power ICs, the one in which the drive circuit and the control circuit are integrated is a display drive device, an in-vehicle IC, or the like.
It can be used for many purposes. This kind of power IC
In the MOSFET used in the output stage of, the high drain breakdown voltage and the low on resistance are required.
【０００３】図８は、従来の出力段に用いられる高耐圧
ＭＯＳＦＥＴの構造を示す素子断面図である。図中、７
１はｐ型半導体基板を示しており、このｐ型半導体基板
７１上には、高抵抗のｎ- 型活性層７２がエピタキシャ
ル成長されている。このｎ- 型活性層７２の表面には、
ｐ型ベース層７４ａおよび低抵抗のｐ+ 型ベース層７４
ｂが選択的に形成されており、これらベース層７４ａ，
７４ｂの表面には、ｎ+ 型ソース層７５が選択的に形成
されている。ｐ+ 型ベース層７４ｂおよびｎ+ 型ソース
層７５にはソース電極７８が設けられている。FIG. 8 is a cross-sectional view of an element showing the structure of a high breakdown voltage MOSFET used in a conventional output stage. 7 in the figure
Reference numeral 1 denotes a p-type semiconductor substrate. On this p-type semiconductor substrate 71, a high-resistance n − -type active layer 72 is epitaxially grown. On the surface of the n − type active layer 72,
p-type base layer 74a and low-resistance p + -type base layer 74
b are selectively formed, and these base layers 74a,
An n + type source layer 75 is selectively formed on the surface of 74b. A source electrode 78 is provided on the p + type base layer 74 b and the n + type source layer 75.
【０００４】また、ｎ- 型活性層７２の表面には、ｎ型
オフセット層７３が選択的に形成されており、このｎ型
オフセット層７３の表面には、ｎ+ 型ドレイン層７６が
選択的に形成されている。このｎ+ 型ドレイン層７６に
は、ドレイン電極７９が設けられている。An n-type offset layer 73 is selectively formed on the surface of the n -- type active layer 72, and an n + -type drain layer 76 is selectively formed on the surface of the n-type offset layer 73. Is formed in. A drain electrode 79 is provided on the n + type drain layer 76.
【０００５】また、ｎ+ 型ドレイン層７６とｎ+ 型ソー
ス層７５とで挟まれた領域上には、ゲート酸化膜８１を
介して、フィールドプレートを有するゲート電極８０が
設けられている。A gate electrode 80 having a field plate is provided on a region sandwiched by the n + type drain layer 76 and the n + type source layer 75 with a gate oxide film 81 interposed therebetween.
【０００６】このように構成された高耐圧ＭＯＳＦＥＴ
によれば、ｎ+ 型ドレイン層７６がｎ型オフセット層７
３内に形成されているため、通常のＭＯＳＦＥＴに比べ
て耐圧が高くなる。High breakdown voltage MOSFET configured as described above
According to the description, the n + -type drain layer 76 is the n-type offset layer 7
Since it is formed inside 3, the breakdown voltage becomes higher than that of a normal MOSFET.
【０００７】しかしながら、この種の高耐圧ＭＯＳＦＥ
Ｔにあっては、ｐ型半導体基板７１とｎ- 型活性層７２
とによるｐｎ接合分離が行なわれているが、素子間を十
分に絶縁分離できず、ノイズに対して弱いなどの問題が
あった。However, this type of high voltage MOSFE
In T, the p-type semiconductor substrate 71 and the n − -type active layer 72
Although the pn junction isolation is performed by the method described above, there is a problem in that the elements cannot be sufficiently insulated and isolated and weak against noise.
【０００８】更に、ハイサイド・スイッチとして用いた
場合、オン状態においては、ｐ型半導体基板７１とｎ+
ドレイン層７６との間に電源電位が印加されるので、ｐ
型半導体基板７１とｎ- 型活性層７２との接合部から上
下方向に空乏層が広がり、オン抵抗が高くなるという問
題があった。Further, when used as a high side switch, in the ON state, the p type semiconductor substrate 71 and the n +
Since the power supply potential is applied between the drain layer 76 and the drain layer 76, p
There is a problem that a depletion layer spreads in the vertical direction from the junction between the type semiconductor substrate 71 and the n − type active layer 72, and the on-resistance increases.
【０００９】[0009]
【発明が解決しようとする課題】上述の如く、従来の高
耐圧ＭＯＳＦＥＴは、必要な耐圧は確保できたが、素子
間の絶縁分離が不十分であった。また、ハイサイド・ス
イッチとして用いた場合には、素子内に空乏層が広が
り、オン抵抗が高くなるという問題があった。As described above, the conventional high breakdown voltage MOSFET can secure the required breakdown voltage, but the insulation isolation between elements is insufficient. Further, when used as a high-side switch, there is a problem that a depletion layer spreads in the element and the on-resistance increases.
【００１０】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、耐圧、絶縁分離および
オン抵抗を同時に改善できる高耐圧半導体装置を提供す
ることにある。The present invention has been made in view of the above circumstances, and an object thereof is to provide a high breakdown voltage semiconductor device capable of simultaneously improving breakdown voltage, insulation isolation, and on-resistance.
【００１１】[0011]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の高耐圧半導体装置は、表面が絶縁層であ
る基板上に高抵抗半導体層と、この高抵抗半導体層の表
面に選択的に形成された第１導電型ベース層と、この第
１導電型ベース層の表面に選択的に形成された第１の第
２導電型半導体層と、前記高抵抗半導体層の表面に選択
的に形成され、前記絶縁層に達しない第２導電型オフセ
ット層と、この第２導電型オフセット層の表面に選択的
に形成された第２の第２導電型半導体層と、前記第１の
第２導電型半導体層と前記第２の第２導電型半導体層と
の間の領域上にゲート絶縁膜を介して設けられたゲート
電極とを備え、前記第２導電型オフセット層は、その拡
散深さが１〜２μｍで、そのドーズ量が２〜３×１０12
ｃｍ-2であることを特徴とする。In order to achieve the above object, a high breakdown voltage semiconductor device of the present invention has a high resistance semiconductor layer on a substrate whose surface is an insulating layer, and a high resistance semiconductor layer formed on the surface of the high resistance semiconductor layer. A first conductive type base layer selectively formed, a first second conductive type semiconductor layer selectively formed on the surface of the first conductive type base layer, and a surface of the high resistance semiconductor layer Second conductive type offset layer that is formed selectively and does not reach the insulating layer, a second second conductive type semiconductor layer selectively formed on the surface of the second conductive type offset layer, and the first A gate electrode provided via a gate insulating film on a region between the second conductive type semiconductor layer and the second second conductive type semiconductor layer, wherein the second conductive type offset layer is a diffusion layer thereof. The depth is 1-2 μm and the dose is 2-3 × 10 12.
It is characterized by being cm −2 .
【００１２】[0012]
【作用】本発明によれば、絶縁層上に素子を形成してい
るので、従来のｐｎ接合分離よりも確実に素子間を分離
できる。更に、本発明者等の研究によれば、上記の如き
に第２導電型オフセット層の不純物濃度および深さを選
べば、耐圧およびオン抵抗について良好な結果が得られ
ることが分かった。したがって、本発明によれば、絶縁
分離、耐圧およびオン抵抗を同時に改善できる。According to the present invention, since the elements are formed on the insulating layer, the elements can be separated more reliably than the conventional pn junction separation. Further, according to the research conducted by the present inventors, it has been found that, when the impurity concentration and the depth of the second conductivity type offset layer are selected as described above, good results can be obtained with respect to the breakdown voltage and the on-resistance. Therefore, according to the present invention, the insulation isolation, the breakdown voltage and the on-resistance can be improved at the same time.
【００１３】[0013]
【実施例】以下、図面を参照しながら実施例を説明す
る。図１は、本発明の第１の実施例に係わる高耐圧ＭＯ
ＳＦＥＴの素子構造を示す素子断面図である。Embodiments will be described below with reference to the drawings. FIG. 1 shows a high breakdown voltage MO according to the first embodiment of the present invention.
It is an element sectional view showing an element structure of SFET.
【００１４】図中、１は半導体基板を示しており、この
半導体基板１上には、絶縁層２を介して、高抵抗のｐ-
型活性層３が設けられている。このｐ- 型活性層３は、
例えば、エピタキシャル成長法により形成する。このｐ
- 型活性層３の表面には、パンチスールー防止用の低抵
抗のｐ+ 型ベース層４ａ、およびｐチャネル形成用のｐ
型ベース層４ｂが選択的に形成されており、これらベー
ス層４ａ，４ｂの表面には、ｎ+ 型ソース層５が選択的
に形成されている。ｐ+ 型ベース層４ｂおよびｎ+ 型ソ
ース層５にはソース電極８が設けられている。In the figure, reference numeral 1 denotes a semiconductor substrate, on which a high resistance p − is provided via an insulating layer 2.
A mold active layer 3 is provided. The p − type active layer 3 is
For example, it is formed by an epitaxial growth method. This p
- The surface of the mold active layer 3, p for low resistance p + -type base layer 4a, and p-channel formation for preventing punch Sulu
The type base layer 4b is selectively formed, and the n + type source layer 5 is selectively formed on the surfaces of these base layers 4a and 4b. A source electrode 8 is provided on the p + type base layer 4b and the n + type source layer 5.
【００１５】また、ｐ- 型活性層３の表面には、ｎ型オ
フセット層７が選択的に形成されている。このｎ型オフ
セット層７は、例えば、ドーズ量２〜５×１０12ｃｍ-2
の条件でドナーとなるイオンを注入した後、熱処理によ
って浅い拡散を行なって形成する。このｎ型オフセット
層７の表面には、ｎ+ 型ドレイン層６が選択的に形成さ
れている。このｎ+ 型ドレイン層６にはドレイン電極９
が設けられている。An n-type offset layer 7 is selectively formed on the surface of the p -- type active layer 3. The n-type offset layer 7 has a dose amount of 2 to 5 × 10 12 cm −2 , for example.
After implanting the ion serving as the donor under the condition of 1., shallow diffusion is performed by heat treatment. The n + type drain layer 6 is selectively formed on the surface of the n type offset layer 7. A drain electrode 9 is formed on the n + -type drain layer 6.
Is provided.
【００１６】また、ｎ+ 型ソース層５とｎ- 型ドレイン
層６とで挟まれた領域上には、厚さ１５ｎｍ程度のゲー
ト酸化膜１１を介してゲート電極１０が設けられてい
る。このゲート電極１０はフィールドプレートを有し、
このフィールドプレートはゲート部のドレイン端におけ
る電界を弱める働きを行なっている。A gate electrode 10 is provided on a region sandwiched by the n + type source layer 5 and the n − type drain layer 6 with a gate oxide film 11 having a thickness of about 15 nm interposed therebetween. This gate electrode 10 has a field plate,
This field plate serves to weaken the electric field at the drain end of the gate portion.
【００１７】このように構成された高耐圧ＭＯＳＦＥＴ
によれば、ｎ+ 型ドレイン層６がｎ型オフセット層７内
に形成されているため、通常のＭＯＳＦＥＴに比べて耐
圧が高くなるのは勿論のこと、半導体基板１上に絶縁層
２を介して素子が形成され、つまり、ＳＯＩ基板上に素
子が形成されているので、従来に比べて、素子間の分離
が完全なものになる。High breakdown voltage MOSFET configured as described above
According to the above, since the n + -type drain layer 6 is formed in the n-type offset layer 7, the breakdown voltage is higher than that of a normal MOSFET, and the insulating layer 2 is formed on the semiconductor substrate 1 via the insulating layer 2. Since the elements are formed by using the SOI substrate, that is, the elements are formed on the SOI substrate, the isolation between the elements becomes more complete than in the conventional case.
【００１８】更に、上記の如きにｎ型オフセット層７の
不純物濃度および深さを選んでいるので、耐圧およびオ
ン抵抗の両方を改善できる。図５，図６は、そのことを
示す実験データである。Furthermore, since the impurity concentration and the depth of the n-type offset layer 7 are selected as described above, both the breakdown voltage and the on-resistance can be improved. 5 and 6 are experimental data showing this.
【００１９】図５は、拡散深さをパラメータとしたとき
のオフセット領域へのドーズ量と耐圧との関係を示す特
性図である。この図５からドーズ量が３×１０12ｃｍ-2
以上になると耐圧は拡散深さによらずに急激に低下す
る。また、拡散深さが１μｍ以下だと耐圧のピークも低
く、最適なドーズ量の領域も狭い。したがって、必要な
耐圧を得るためには少なくとも１μｍ，より好ましくは
１．５μｍ以上の拡散深さが必要である。そして、ドー
ズ量が２〜３×１０12ｃｍ-2の範囲にあれば、十分な耐
圧を得ることが可能である。FIG. 5 is a characteristic diagram showing the relationship between the dose amount to the offset region and the breakdown voltage when the diffusion depth is used as a parameter. From FIG. 5, the dose amount is 3 × 10 12 cm -2
With the above conditions, the breakdown voltage sharply decreases regardless of the diffusion depth. Further, when the diffusion depth is 1 μm or less, the peak of breakdown voltage is low and the region of the optimum dose amount is narrow. Therefore, a diffusion depth of at least 1 μm, more preferably 1.5 μm or more is required to obtain the required breakdown voltage. If the dose amount is in the range of 2 × 3 × 10 12 cm −2 , it is possible to obtain a sufficient breakdown voltage.
【００２０】図６はドーズ量を２．７×１０12ｃｍ-2と
したときの拡散深さとオン抵抗との関係を示す特性図で
ある。この図６より拡散深さ１．５〜２μｍまでは深く
なるにつれてオン抵抗が減少するがそれ以上になるとオ
ン抵抗は増加することが分かる。FIG. 6 is a characteristic diagram showing the relationship between the diffusion depth and the on-resistance when the dose amount is 2.7 × 10 12 cm -2 . It can be seen from FIG. 6 that the on-resistance decreases as the diffusion depth increases to 1.5 to 2 μm, but increases above that.
【００２１】以上の結果をまとめると、ｎ型オフセット
層７は、拡散深さが１〜２μｍ、ドーズ量が２〜３×１
０12ｃｍ-2であれば、オン抵抗および耐圧の改善につい
て両立できる。To summarize the above results, the n-type offset layer 7 has a diffusion depth of 1 to 2 μm and a dose of 2 to 3 × 1.
If it is 0 12 cm -2, it is possible to achieve both improvement in on-resistance and breakdown voltage.
【００２２】図７に、ｐ型基板の濃度をパラメータとし
たきのドーズ量と耐圧との関係を示す特性図を示してお
く。ドーズ量を増やしていくと、大体２×１０12ｃｍ-2
を越えると急速に耐圧は低下する。ｐ型基板の濃度を上
げていくと、耐圧が低下するドーズ量を増やすことがで
き、オン抵抗の低減が図れる。しかし、ｐ型基板の濃度
が１×１０16ｃｍ-2を越えると耐圧が低下するので、ｐ
型基板の濃度は１×１０16ｃｍ-2付近が良い。FIG. 7 is a characteristic diagram showing the relationship between the dose amount and the breakdown voltage when the concentration of the p-type substrate is used as a parameter. When the dose is increased, it is about 2 × 10 12 cm -2
If the voltage exceeds, the breakdown voltage will drop rapidly. When the concentration of the p-type substrate is increased, the dose amount at which the breakdown voltage decreases can be increased, and the on-resistance can be reduced. However, when the concentration of the p-type substrate exceeds 1 × 10 16 cm -2 , the breakdown voltage decreases, so p
The concentration of the mold substrate is preferably around 1 × 10 16 cm -2 .
【００２３】以上述べたように本実施例によれば、ＳＯ
Ｉ基板の採用と、ｎ型オフセット層７の最適化により、
ハイサイド・スイッチングに用いても、オン抵抗を上げ
ること無く、高いドレイン耐圧を達成できる高耐圧ＭＯ
ＳＦＥＴが得られる。As described above, according to this embodiment, the SO
By adopting the I substrate and optimizing the n-type offset layer 7,
High breakdown voltage MO that can achieve high drain breakdown voltage without increasing the on-resistance even when used for high-side switching.
SFET is obtained.
【００２４】図２は、本発明の第２の実施例に係わる高
耐圧ＭＯＳＦＥＴの素子構造を示す素子断面図である。
本実施例の高耐圧ＭＯＳＦＥＴが先の実施例のそれと異
なる点は、ｎ型オフセット層７ａがｐ+ 型ベース層４ｂ
の下部にまで延びていることにある。このようなｎ型オ
フセット層７ａは、基板全面に対してイオン注入を行な
うことにより、容易に作成できる。このように構成され
た高耐圧ＭＯＳＦＥＴでも、先の実施例のそれと同様な
効果が得られる。FIG. 2 is an element cross-sectional view showing the element structure of the high breakdown voltage MOSFET according to the second embodiment of the present invention.
The high-voltage MOSFET of this embodiment differs from that of the previous embodiments in that the n-type offset layer 7a is a p + -type base layer 4b.
It extends to the bottom of the. Such an n-type offset layer 7a can be easily formed by implanting ions on the entire surface of the substrate. The high withstand voltage MOSFET configured as described above can also obtain the same effect as that of the above-described embodiment.
【００２５】図３は、本発明の第３の実施例に係わる高
耐圧ＭＯＳＦＥＴの素子構造を示す素子断面図である。
本実施例の高耐圧ＭＯＳＦＥＴが第１の実施例のそれと
異なる点は、ｎ型オフセット層７ｂの濃度プロファイル
にある。すなわち、ｎ型オフセット層７ｂの濃度ピーク
が表面よりも深い位置にある。このようなｎ型オフセッ
ト層７ｂは、加速エネルギーを高くしてイオン注入すれ
ば形成できる。また、ｎ型オフセット層７ｂの濃度ピー
クが深くなるので、ｎ+ ドレイン層６ａも深く形成して
ある。FIG. 3 is a device sectional view showing a device structure of a high breakdown voltage MOSFET according to a third embodiment of the present invention.
The high withstand voltage MOSFET of this embodiment is different from that of the first embodiment in the concentration profile of the n-type offset layer 7b. That is, the concentration peak of the n-type offset layer 7b is located deeper than the surface. Such an n-type offset layer 7b can be formed by increasing the acceleration energy and implanting ions. Since the concentration peak of the n-type offset layer 7b becomes deep, the n + drain layer 6a is also deeply formed.
【００２６】本実施例によれば、表面よりも深い領域に
電流が流れるため、表面抵抗の影響を受けなくなり、耐
圧を保ったまま更にオン抵抗を低くできる。図４は、本
発明の第４の実施例に係わる高耐圧ＭＯＳＦＥＴの素子
構造を示す素子断面図である。According to the present embodiment, since the current flows in a region deeper than the surface, the influence of the surface resistance is eliminated, and the on-resistance can be further reduced while maintaining the breakdown voltage. FIG. 4 is a device sectional view showing the device structure of a high breakdown voltage MOSFET according to the fourth embodiment of the present invention.
【００２７】本実施例の高耐圧ＭＯＳＦＥＴが第１の実
施例のそれと異なる点は、ゲートおよびフィールドプレ
ートのエッジ部のｎ型オフセット層７ｃのｎ型不純物濃
度が、他の部分のｎ型オフセット層７のそれよりも低く
なっていることにある。このようなｎ型オフセット層７
は、例えば、ｎ型オフセット層７ｃの部分にマスクをつ
けてイオン注入を行なえば形成できる。The high withstand voltage MOSFET of this embodiment is different from that of the first embodiment in that the n-type offset concentration of the n-type offset layer 7c at the edge portions of the gate and field plate is different from that of the other portions. It is lower than that of 7. Such an n-type offset layer 7
Can be formed, for example, by applying a mask to the portion of the n-type offset layer 7c and performing ion implantation.
【００２８】本実施例によれば、ｎ型オフセット層７ｃ
がガードリングとして機能するので、オフセット層７の
ｎ型不純物の濃度を高くできる。このため、オフセット
層７の総ドーズ量を増加できるので、耐圧を保ったまま
更にオン抵抗を低くできる。According to this embodiment, the n-type offset layer 7c
Function as a guard ring, the n-type impurity concentration of the offset layer 7 can be increased. Therefore, the total dose of the offset layer 7 can be increased, and the on-resistance can be further reduced while maintaining the breakdown voltage.
【００２９】なお、ｎ型オフセット層７ｃの代わりに、
低濃度のｐ- 型半導体層を用いても良い。以上四つの実
施例について説明したが、本発明は上述した実施例に限
定されるものではない。In place of the n-type offset layer 7c,
A low concentration p − type semiconductor layer may be used. Although the four embodiments have been described above, the present invention is not limited to the above embodiments.
【００３０】例えば、ソース層，ドレイン層その他の半
導体層の導電型を全て逆導電型にしても良い。なお、活
性層の導電型は、他の半導体層の導電型に関係なく、ｐ
型およびｎ型のどちらでも良い。また、上記実施例を組
み合わせても良い。その他、本発明の要旨を逸脱しない
範囲で、種々変形して実施できる。For example, all the conductivity types of the source layer, the drain layer and the other semiconductor layers may be reverse conductivity types. The conductivity type of the active layer is p regardless of the conductivity types of other semiconductor layers.
Either type or n-type may be used. Further, the above embodiments may be combined. In addition, various modifications can be made without departing from the scope of the present invention.
【００３１】[0031]
【発明の効果】以上詳述したように本発明によれば、耐
圧を保ったまま、絶縁分離およびオン抵抗を改善できる
高耐圧ＭＯＳＦＥＴが得られる。As described in detail above, according to the present invention, it is possible to obtain a high breakdown voltage MOSFET capable of improving insulation isolation and ON resistance while maintaining the breakdown voltage.
【図１】本発明の第１の実施例に係わる高耐圧ＭＯＳＦ
ＥＴの素子構造を示す素子断面図FIG. 1 is a high breakdown voltage MOSF according to a first embodiment of the present invention.
Element sectional view showing the element structure of ET
【図２】本発明の第１の実施例に係わる高耐圧ＭＯＳＦ
ＥＴの素子構造を示す素子断面図FIG. 2 is a high breakdown voltage MOSF according to the first embodiment of the present invention.
Element sectional view showing the element structure of ET
【図３】本発明の第１の実施例に係わる高耐圧ＭＯＳＦ
ＥＴの素子構造を示す素子断面図FIG. 3 is a high breakdown voltage MOSF according to the first embodiment of the present invention.
Element sectional view showing the element structure of ET
【図４】本発明の第１の実施例に係わる高耐圧ＭＯＳＦ
ＥＴの素子構造を示す素子断面図FIG. 4 is a high breakdown voltage MOSF according to the first embodiment of the present invention.
Element sectional view showing the element structure of ET
【図５】ドーズ量と耐圧との関係を示す特性図FIG. 5 is a characteristic diagram showing the relationship between the dose amount and the breakdown voltage.
【図６】拡散深さとオン抵抗との関係を示す特性図FIG. 6 is a characteristic diagram showing a relationship between diffusion depth and ON resistance.
【図７】ｐ型基板の濃度をパラメータとしたきのドーズ
量と耐圧との関係を示す特性図FIG. 7 is a characteristic diagram showing the relationship between the dose amount and the breakdown voltage of the mushroom with the concentration of the p-type substrate as a parameter.
【図８】従来の出力段に用いられる高耐圧ＭＯＳＦＥＴ
の構造を示す素子断面図FIG. 8: High breakdown voltage MOSFET used in a conventional output stage
Element cross-sectional view showing the structure of
１…半導体基板 ２…絶縁層 ３…ｐ- 型活性層（高抵抗半導体層） ４ａ…ｐ+ 型ベース層（第１導電型ベース層） ４ｂ…ｐ型ベース層（第１導電型ベース層） ５…ｎ+ 型ソース層（第１の第２導電型半導体層） ６，６ａ…ｎ+ 型ドレイン層（第２の第２導電型半導体
層） ７，７ａ，７ｂ，７ｃ…ｎ型オフセット層（第２導電型
オフセット層） ８…ソース電極 ９…ドレイン電極 １０…ゲート電極 １１…ゲート酸化膜DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating layer 3 ... P - type active layer (high resistance semiconductor layer) 4a ... P + type base layer (first conductivity type base layer) 4b ... P type base layer (first conductivity type base layer) 5 ... N + type source layer (first second conductivity type semiconductor layer) 6, 6a ... N + type drain layer (second second conductivity type semiconductor layer) 7, 7a, 7b, 7c ... N type offset layer (Second conductivity type offset layer) 8 ... Source electrode 9 ... Drain electrode 10 ... Gate electrode 11 ... Gate oxide film
Claims (1)
層と、 この高抵抗半導体層の表面に選択的に形成された第１導
電型ベース層と、 この第１導電型ベース層の表面に選択的に形成された第
１の第２導電型半導体層と、 前記高抵抗半導体層の表面に選択的に形成され、前記絶
縁層に達しない第２導電型オフセット層と、 この第２導電型オフセット層の表面に選択的に形成され
た第２の第２導電型半導体層と、 前記第１の第２導電型半導体層と前記第２の第２導電型
半導体層との間の領域上にゲート絶縁膜を介して設けら
れたゲート電極とを具備してなり、 前記第２導電型オフセット層は、その拡散深さが１〜２
μｍで、そのドーズ量が２〜３×１０12ｃｍ-2であるこ
とを特徴とする高耐圧半導体装置。1. A high resistance semiconductor layer on a substrate whose surface is an insulating layer, a first conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer, and a first conductivity type base layer. A first second conductivity type semiconductor layer selectively formed on the surface; a second conductivity type offset layer selectively formed on the surface of the high resistance semiconductor layer and not reaching the insulating layer; A second second conductivity type semiconductor layer selectively formed on the surface of the conductivity type offset layer, and a region between the first second conductivity type semiconductor layer and the second second conductivity type semiconductor layer. A second conductive type offset layer having a diffusion depth of 1 to 2;
A high breakdown voltage semiconductor device, characterized in that the dose amount is 2 to 3 × 10 12 cm −2 in μm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23128193A JP3217554B2 (en) | 1993-09-17 | 1993-09-17 | High voltage semiconductor device |
| US08/425,246 US5548150A (en) | 1993-03-10 | 1995-04-17 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23128193A JP3217554B2 (en) | 1993-09-17 | 1993-09-17 | High voltage semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0786580A true JPH0786580A (en) | 1995-03-31 |
| JP3217554B2 JP3217554B2 (en) | 2001-10-09 |
Family
ID=16921150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23128193A Expired - Fee Related JP3217554B2 (en) | 1993-03-10 | 1993-09-17 | High voltage semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3217554B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100249290B1 (en) * | 1996-01-26 | 2000-03-15 | 이마이 기요스케 | Silicon-on-insulator(soi) type thin film transistor |
| JP2001044431A (en) * | 1999-05-27 | 2001-02-16 | Fuji Electric Co Ltd | Semiconductor device |
| JP2001102586A (en) * | 1999-09-28 | 2001-04-13 | Toshiba Corp | High breakdown voltage semiconductor device |
| US6294818B1 (en) | 1996-01-22 | 2001-09-25 | Fuji Electric Co., Ltd. | Parallel-stripe type semiconductor device |
| KR100342804B1 (en) * | 1999-10-29 | 2002-07-03 | 다카노 야스아키 | Semiconductor device and method of manufacturing the same |
| US6566709B2 (en) | 1996-01-22 | 2003-05-20 | Fuji Electric Co., Ltd. | Semiconductor device |
| US6943406B2 (en) | 2003-06-30 | 2005-09-13 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US7067878B2 (en) | 2001-03-08 | 2006-06-27 | Hitachi, Ltd. | Field effect transistor |
| JP2006245517A (en) * | 2005-03-07 | 2006-09-14 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2015056472A (en) * | 2013-09-11 | 2015-03-23 | 株式会社東芝 | Semiconductor device |
| WO2019202350A1 (en) * | 2018-04-19 | 2019-10-24 | 日産自動車株式会社 | Semiconductor device and method of manufacturing semiconductor device |
-
1993
- 1993-09-17 JP JP23128193A patent/JP3217554B2/en not_active Expired - Fee Related
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6734496B2 (en) | 1996-01-22 | 2004-05-11 | Fuji Electric Co., Ltd. | Semiconductor device |
| US6294818B1 (en) | 1996-01-22 | 2001-09-25 | Fuji Electric Co., Ltd. | Parallel-stripe type semiconductor device |
| US6566709B2 (en) | 1996-01-22 | 2003-05-20 | Fuji Electric Co., Ltd. | Semiconductor device |
| US6627948B1 (en) | 1996-01-22 | 2003-09-30 | Fuji Electric Co., Ltd. | Vertical layer type semiconductor device |
| US6700157B2 (en) | 1996-01-22 | 2004-03-02 | Fuji Electric Co., Ltd. | Semiconductor device |
| US6720615B2 (en) | 1996-01-22 | 2004-04-13 | Fuji Electric Co., Ltd. | Vertical-type MIS semiconductor device |
| US6724040B2 (en) | 1996-01-22 | 2004-04-20 | Fuji Electric Co., Ltd. | Semiconductor device |
| KR100249290B1 (en) * | 1996-01-26 | 2000-03-15 | 이마이 기요스케 | Silicon-on-insulator(soi) type thin film transistor |
| JP2001044431A (en) * | 1999-05-27 | 2001-02-16 | Fuji Electric Co Ltd | Semiconductor device |
| JP2001102586A (en) * | 1999-09-28 | 2001-04-13 | Toshiba Corp | High breakdown voltage semiconductor device |
| KR100342804B1 (en) * | 1999-10-29 | 2002-07-03 | 다카노 야스아키 | Semiconductor device and method of manufacturing the same |
| US7067878B2 (en) | 2001-03-08 | 2006-06-27 | Hitachi, Ltd. | Field effect transistor |
| US6943406B2 (en) | 2003-06-30 | 2005-09-13 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2006245517A (en) * | 2005-03-07 | 2006-09-14 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2015056472A (en) * | 2013-09-11 | 2015-03-23 | 株式会社東芝 | Semiconductor device |
| WO2019202350A1 (en) * | 2018-04-19 | 2019-10-24 | 日産自動車株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| JPWO2019202350A1 (en) * | 2018-04-19 | 2021-04-22 | 日産自動車株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
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