JP2561963B2 - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an insulated gate bipolar transistor (In
Sulated Gate Bipolar Transistor (hereinafter referred to as IGBT), and particularly to improvement of the trade-off relationship between turn-off time and on-resistance associated with lifetime control.

[Conventional technology]

Generally, a bipolar transistor has a problem of low output impedance but a low input impedance, and conversely, a field effect transistor has a problem of high input impedance but a high output impedance.

The IGBT is intended to realize high input impedance and low output impedance by being integrated so as to compensate for the drawbacks of these various transistors.

That is, by forming a high-concentration impurity diffusion layer of a conductivity type different from that of the substrate on the back surface of the substrate on which the MOSFET is formed, the bipolar transistor and the field effect transistor (MOSFET) are integrated and the MOSFET is turned on. The generated current is injected into the base region of the bipolar transistor, and the injected current controls the bipolar transistor.

Generally, an IGBT device has a structure in which a large number of IGBT elements (hereinafter referred to as IGBT cells) are connected in parallel. FIG. 7 is a sectional view showing the structure of a conventional n-channel type IGBT cell.
FIG. 8 is a circuit diagram showing the equivalent circuit.

In FIG. 7, reference numeral 1 is a P ⁺ collector layer, on one of which the N ⁻ epitaxial layer 2 is formed. N ^-
A P-well region 3 is formed in a partial region of the surface of the epitaxial layer 2 by selectively diffusing P-type impurities, and a partial region of the surface of the P-well region 3 is
An N ⁺ epitaxial region 4 is formed by selectively diffusing a high concentration N-type impurity. P sandwiched between the surface of the N ⁻ epitaxial layer 2 and the surface of the N ⁺ emitter region 4
The gate insulating film 5 is formed on the surface of the well region 3,
The gate insulating film 5 is also formed on the surface of the N ⁻ epitaxial layer 2 so as to be integrated between the adjacent IGBT cells. A gate electrode 6 made of, for example, polysilicon is formed on the gate insulating film 5, and the P well region 3 and N ⁺
A metal emitter electrode 7 such as aluminum is formed so as to be electrically connected to both of the emitter regions 4.
The gate electrode 6 and the emitter electrode 7 are electrically connected in common to all the IGBT cells by forming a multilayer structure with the insulating film 8 interposed therebetween.
On the back surface of the P ⁺ collector layer 1, a metal collector electrode 9 is entirely IG
It is formed integrally with the BT cell.

The vicinity of the surface of the P well region 3 sandwiched between the N ⁻ epitaxial layer 2 and the N ⁺ emitter region 4 has an n-channel MOS structure, and by applying a positive voltage to the gate electrode 6 through the gate terminal G, Electrons flow from the N ⁺ emitter region 4 to the N ⁻ epitaxial layer 2 through the channel formed in the vicinity of the surface of the P well region 3 immediately below the gate electrode 6. I _e represents the electron current flowing in this way. On the other hand, P ⁺
Holes, which are minority carriers, are injected from the collector layer 1 into the N ⁻ epitaxial layer 2, part of which is recombined with the electrons and disappears, and the rest flows in the P well region 3 as a hole current I _h . In this way, the IGBT basically operates in a bipolar manner, and the conductivity of the N ^- epitaxial layer 2 is increased due to the effect of the conductivity modulation, so that the on-state voltage and the large current are lower than those of the conventional power MOS. There is an advantage that capacity can be realized.

In FIG. 8, 10 is the N ^- epitaxial layer 2, P
Parasitic NPN consisting of well region 3 and N ⁺ emitter region 4
Transistor 11, PNP transistor consisting of P ⁺ collector layer 1, N ⁻ epitaxial layer 2 and P well region 3, 12
Is an NMOS transistor in which the surface of the P well region 3 under the gate electrode 6 is a channel region, R _B is the diffusion resistance of the P well region 3, and R _LC is the on resistance of the PNP transistor 11.

On the other hand, the IGBT has the above-mentioned advantages, but at the time of turn-off, the hole current I _h decreases more slowly in time than a field effect transistor or the like. This is because when the PNP transistor 11 is in the ON state, the N ^- epitaxial layer 2 serving as the base region of the PNP transistor 11 is filled with electrons and holes, and the MOS transistor 12 is turned off to allow the N ^- epitaxial layer 2 to reach the N ^- epitaxial layer 2. This is because even if the injection of electrons is blocked, holes do not suddenly decrease due to their low mobility.

In order to shorten the turn-off time, conventionally, there are roughly known two means. One of them is PNP, which uses heavy metal atoms such as gold and platinum as so-called lifetime killer.
This lifetime killer is a means for introducing into the N ⁻ epitaxial layer 2 which is the base region of the transistor 12.
It becomes a recombination center of electrons and holes in the N ^- epitaxial layer 2 and eliminates these carriers within a short time.

The other is a means for irradiating radiation such as electron beams, γ rays, neutron rays, various ion beams, etc. Since these radiations introduce deep trap levels into the N ^- epitaxial layer 2, this trap level Since the position becomes the recombination center for the carrier, the carrier can be extinguished within a short time at turn-off. These techniques are called lifetime control techniques and are applied to various elements such as thyristors and power diodes.

In general, the lifetime control technology by irradiation of radiation has obtained better results than heavy metal diffusion in terms of controllability and reproducibility. However, in the method using electron beam, γ ray, and neutron beam in the irradiation of radiation, the trap level in the N ⁻ epitaxial layer 2 is generated by the irradiation, and at the same time, the quality of the gate oxide film 5 is changed. And
As a result, there is a problem that even the threshold value is changed and the operation reliability thereof is lowered. This problem is solved by irradiating various ion beams such as protons from the collector electrode 9 side. That is, as shown in FIG. 7, various light ion beams 50 such as protons are irradiated from the side where the collector electrode 9 is formed, and the range position thereof is set in the N ⁻ epitaxial layer 2 ( (Indicated by a broken line in FIG. 7), by adjusting the acceleration energy, the gate insulating film 5 and others,
The lifetime control can be performed without any influence on the layers 3 and 4 formed on the emitter side.

Furthermore, as shown in FIG. 9, crystal defects (mainly vacancies) due to irradiation of various ions such as protons are concentrated in the defect distribution peak half-width W around the range D, and other It has a characteristic that does not affect the place so much. By utilizing this characteristic, it is possible to execute lifetime control with high controllability. For example, as shown in Japanese Patent Laid-Open No. 64-19771, the P ⁺ collector region (7th
N ^- base region (corresponding to P ⁺ collector layer 1 in the figure) (7th
Effective lifetime control can be performed by setting the range D within the N ⁻ epitaxial layer 2 in the figure). This is because the base region near the MOSFET plays an important role in triggering carriers injected from the channel of the MOSFET to cause conductivity modulation. Therefore, if a crystal defect occurs in this part, the on-resistance increases. This is because it is the furthest from the channel region of the MOSFET. This is because it is desirable to have the range of the ion beam in the N ^- base region near the P ⁺ collector region. Further, in order to quickly trap the holes that have been continuously injected until the initial stage of the off operation, it is effective to intensively generate crystal defects in the N ^- base region near the P ⁺ collector region.

[Problems to be Solved by the Invention]

However, all of the above-mentioned lifetime control is the same as that the crystal defects are generated over the entire surface of the IGBT element, and therefore the resistance value of the N ⁻ epitaxial layer 2 is inevitably accompanied by the occurrence of the crystal defects. And the on-resistance R _LC of the IGBT shown in FIG. 8 increases. In other words, there is a trade-off relationship between the on-resistance of the IGBT and the turn-off time, and there is a problem that the trade-off relationship is not optimal at present.

The present invention has been made to solve the above problems, and insulation of a structure that optimizes the trade-off relationship between on-resistance and turn-off time by lifetime control using ionizing radiation such as ion beam. The purpose is to obtain a gate type bipolar transistor.

[Means for solving the problem]

The insulated gate bipolar transistor according to the present invention has a structure in which first and second semiconductor layers of first and second conductivity types are laminated so that a junction surface is uneven, and a surface of the second semiconductor layer is formed. A selectively formed first conductivity type first
And a second semiconductor region of the second conductivity type selectively formed on the surface of the first semiconductor region, the second semiconductor layer and the second semiconductor region. An insulating film formed on the surface of the first semiconductor region, a control electrode formed on the insulating film, and a first main film formed over the first and second semiconductor regions. An electrode and a second main electrode formed on the back surface of the first semiconductor layer, wherein the first and second semiconductor layers have crystal defects within the range of the thickness of the unevenness on the joint surface of the unevenness. It is configured to have.

Further, in the method for manufacturing an insulated gate bipolar transistor according to claim 2, the first step is performed so that the joint surface becomes uneven.
Stacking a second semiconductor layer of the second conductivity type on the first semiconductor layer of the second conductivity type, and selecting a first semiconductor region of the first conductivity type on the surface of the second semiconductor layer. Forming step, a step of selectively forming a second semiconductor region of the second conductivity type on the surface of the first semiconductor region, the second semiconductor layer and the second semiconductor region, The first sandwiched between
A step of forming an insulating film on the surface of the semiconductor region, a step of forming a control electrode on the insulating film, and a step of forming a first main electrode over the first and second semiconductor regions. A step of forming a second main electrode on the back surface of the first semiconductor layer, and a range of the first and second semiconductor layers from the main surface on which the second main electrode is formed. Of irradiating ionizing radiation so as to be near the center of the uneven bonding surface, wherein the ionizing radiation has a distribution range of crystal defects generated during irradiation smaller than the thickness of the unevenness of the uneven bonding surface. It is a type of ionizing radiation that has properties.

[Action]

In the insulated gate bipolar transistor according to the present invention, the bipolar transistor on the equivalent circuit, which is a component thereof, includes a first semiconductor region, a second semiconductor layer having no crystal defect, and a first semiconductor having a crystal defect. By parallel connection of the first bipolar transistor including the layer and the second semiconductor transistor including the first semiconductor region, the second semiconductor layer having the crystal defect and the first semiconductor layer having no crystal defect, It can be regarded as equivalent when constructed.

Since the first bipolar transistor does not have a crystal defect in the second semiconductor layer even if it has a crystal defect in the first semiconductor layer, it has an advantage of low on-resistance and a disadvantage of long turn-off time. On the other hand, the second bipolar transistor has a crystal defect in the second semiconductor layer, and thus has a disadvantage that the on-resistance is high and an advantage that the turn-off time is short.

Further, in the method of manufacturing an insulated gate bipolar transistor according to the present invention, the range of distribution of generated crystal defects is smaller than the thickness of the unevenness of the uneven bonding surface of the first and second semiconductor layers, Irradiation is performed from the main surface on which the second main electrode is formed so that the range is near the center of the concavo-convex joint surface. As a result, crystal defects are formed on the concavo-convex joint surface of the first and second semiconductor layers. Therefore, similarly to the above insulated gate bipolar transistor, it is possible to equivalently configure a bipolar transistor on an equivalent circuit by parallel connection of the first and second bipolar transistors.

〔Example〕

FIG. 1 is a sectional view showing an embodiment of the IGBT according to the present invention. In FIG. 1, 1 is a P ⁺ collector layer, and an N ⁻ base layer 2 (corresponding to the N ⁻ epitaxial layer 2 in FIG. 7) is formed on one main surface thereof. A P well region is formed by selectively diffusing P-type impurities in a partial region of the surface of the N ⁻ base layer 2 ′, and further, in a partial region of the surface of the P well region 3, An N ⁺ emitter region 4 is formed by selectively diffusing a high concentration N type impurity. On the other hand, the P ⁺ collector region 20 is selectively formed in a partial region on the back surface of the N ⁻ base layer 2 ′.
That is, the junction surface between the base region and the collector region of the IGBT of this embodiment is formed to be uneven.

A gate insulating film 5 is formed on the surface of the P well region 3 sandwiched between the surface of the N ⁻ base layer 2 ′ and the surface of the N ⁺ emitter region 4, and the gate insulating film 5 is formed between adjacent IGBT cells. It is also formed on the surface of the N ⁻ base layer 2 ′ so as to be integrated. A gate electrode 6 made of, for example, polysilicon is formed on the gate insulating film 5, and a metal emitter electrode 7 such as aluminum is electrically connected to both the P well region 3 and the N ⁺ emitter region 4. Has been formed. The gate electrode 6 and the emitter electrode 7 are electrically connected in common to all IGBT cells by forming a multi-layer structure with the insulating film 8 interposed therebetween. On the back surface of the P ⁺ collector layer 1, a metal collector electrode 9 is formed integrally with all the IGBT cells. That is, the IGBT according to this embodiment has the same structure as the conventional IGBT shown in FIG. 7 except for the P ⁺ collector region 20, and therefore the basic operation is also the same as that of the conventional IGBT.

From the collector electrode 9 side of the IGBT having such a structure, a light ion beam 50 is irradiated so that the range is located in the vicinity of the center of the P ⁺ collector region 20 (indicated by a broken line in the figure), and crystal defects are generated. Is controlled within the P ⁺ collector region 20 and the N ⁻ base layer 2 ′ at the depth where the P ⁺ collector region 20 is formed. When the lifetime control is performed in this way, as shown in the equivalent circuit diagram of FIG. 2, the PNP transistor controlled by turning on / off the MOSFET 12 has a P well region 3 and an N ⁻ base layer having no crystal defect. 2'and (P ⁺ collector region 20 having a crystal defect + P ⁺ collector layer 1), a PNP transistor 11a, a P well region 3, an N ^- base layer 2 having a crystal defect on the back surface and a P ⁺ collector layer 1
It can be regarded as being configured by parallel connection with the PNP transistor 11b.

In the PNP transistor 11b, P ⁺ of the N ⁻ base layer 2 ′
Since the region near the collector layer 1 has crystal defects caused by irradiation with the light ion beam 50, the turn-off time is shortened as an advantage, and the on-resistance R _LC is increased as a disadvantage, as in the conventional case.

On the other hand, in the PNP transistor 11a, the light ion beam 50
The crystal defects in the P ⁺ collector region 20 by the irradiation of is formed, the P ⁺ collector region 20, since it is a P-type impurity comprises a high concentration, to form a high conductivity region, due to crystal defects The change in conductivity can be ignored. Therefore, the disadvantage is that the turn-off time is not shortened, but the advantage is that light ion
Irradiation with 50 does not increase the on-resistance.

The on-state resistance in the on-state of the IGBT having such a configuration can be sufficiently reduced by the PNP transistor 11a, whose on-state resistance did not increase due to the lifetime control, positively working. On the other hand, the turn-off time can be sufficiently shortened by actively operating the PNP transistor 11b whose turn-off time is shortened by the lifetime control at the time of turn-off. In this way, by making the PNP transistors 11a and 11b function so as to compensate for their respective disadvantages, the trade-off relationship between the on-resistance of the IGBT and the turn-off time can be further improved. That is, the formation width of the P ⁺ collector region 20 may be set so as to optimize the trade-off relationship between the on-resistance of the IGBT and the turn-off time.

Since no lower the on-resistance of the PNP transistor 11a, as described above, is where there is a P ⁺ collector region 20 is required to cause a crystal defect only P ⁺ collector region 20. Therefore, assuming that the thickness of the P ⁺ collector region 20 is W _G , the defect distribution peak half value width W of the light ions irradiated so that the range is located at the center of the P ⁺ collector region 20 is defined as W <W _G. You have to choose.

FIG. 3 is a graph showing the relationship between the average range D in silicon and the defect distribution peak half value width W in hydrogen ions and helium ions. Since the thickness of the P ⁺ collector layer 1 is about 270 μm in a general IGBT, the thickness W _G is 10 μm.
In order to generate crystal defects only in the P ⁺ collector region 20 of a certain degree, it is necessary to implant helium ions instead of hydrogen ions. When the P ⁺ collector region 20 is thick (W _G > 20 μm), hydrogen ions can be used. Although not shown in FIG. 3, the heavier ion than the helium ion has a defect distribution peak half-width W smaller than that of the helium ion, and thus can be applied in place of the helium ion.

4A to 4F are cross-sectional views showing a first method of manufacturing the IGBT according to the above embodiment. The P well region 3 in this case has a first P well region 3a having a relatively low impurity concentration and a shallow depth, and a relatively low impurity concentration formed in the central portion of the first P well region 3a. The second P well region 3b is high and deep.

First, as shown in FIG. 4A, a P ⁺ collector region 20 is formed by selectively diffusing P-type impurities into a part of the back surface region of the N ⁻ base layer 2 ′ serving as a substrate. And
As shown in FIG. 4B, the P ⁺ collector layer 1 is epitaxially grown on the back surface of the N ⁻ base layer 2 ′.

Then, as shown in FIG. 4C, a mask 33 is formed by forming, for example, a silicon oxide film on the surface of the N ⁻ base layer 2 ′ and patterning it. And this mask
P-type impurities such as boron are selectively ion-implanted into the N ^- base layer 2'through 33 and further diffused to form a second surface concentration of about 5 × 10 ^{16 -1} × 10 ¹⁹ cm ^-3 . P well region 3b is formed.

Next, as shown in FIG. 4D, the mask 33 is removed and another mask 34 is formed. Then, a P-type impurity such as boron is selectively ion-implanted into the N ^- base layer 2'through the mask 34 and further diffused to form the second P-well region 3b.
A first P-well region 3a having a lower concentration and a shallower depth is formed. Thus, the P well region 3 in which the second P well region 3b is provided in the central portion of the first P well region 3a is formed.

Next, as shown in FIG. 4E, the mask 34 is removed, and instead, an oxide film and a polysilicon film are formed on the entire surface, and these are patterned to obtain the gate insulating film 5, the gate electrode 6, and the polysilicon layer 6a. To form. Then, by using the gate electrode 6 and the polysilicon layer 6a as a mask, N type impurities such as phosphorus are selectively diffused into the P well region 3 to form the N ⁺ emitter region 4 in a self-aligned manner.

Next, as shown in FIG. 4F, after removing the polysilicon layer 6a, an insulating film 8 is formed on the entire surface and patterned. Then, the metal surface is formed over the entire surface and patterned to form the emitter electrode 7 electrically connected to the N ⁺ emitter region 4 and the gate lead-out portion 37 electrically connected to the gate electrode 6. Then, irradiation with the light ion beam 50 is performed according to the procedure described with reference to FIG.

5A to 5C are cross-sectional views showing a second method of manufacturing the IGBT according to the above embodiment.

First, as shown in FIG. 5A, a P ⁺ collector region 20 is formed by selectively diffusing P-type impurities into a part of the back surface region of the N ⁻ base layer 2 ′ serving as a substrate.

Further, as shown in FIG. 5B, by depositing P-type impurities on the entire back surface of the N ⁻ base layer 2 ′ and then diffusing the impurities,
A P ⁺ diffusion layer 21 is thinly formed on the back surface of the N ⁻ base layer 2 ′.

Next, prepare the P ⁺ substrate 22 and, as shown in FIG.
The surface of the P ⁺ substrate 22 and the P ⁺ diffusion layer 21 are bonded to each other, and the P ⁺ diffusion layer 21 and
Forming a P ⁺ collector layer 1 made of P ⁺ substrate 22. Note that P ⁺
As a method of bonding the diffusion layer 21 and the P ⁺ substrate 22, “UDC621,3
82,333,34,026,027,5 "Akio Nakagawa et al." Si
"Bipolar MOSFET using direct bonding technology", and the paper by Masanobu Ogino in the paper "EDD-89-42 SPC-89-51" by the Institute of Electrical Engineers, Electronic Devices, and Semiconductor Power Conversion Joint Study Material Adhesion methods and the like disclosed in “Current State of Application” and the like.

Since the subsequent manufacturing method is the same as the first manufacturing method, the description thereof will be omitted.

6A and 6B are cross-sectional views showing a third method of manufacturing the IGBT according to the above embodiment.

First, as shown in FIG. 6A, an N ⁺ diffusion region 24 is formed by selectively diffusing N-type impurities into a part of the surface region of the P ⁺ substrate 23.

Then, as shown in FIG. 6B, N ⁻ on the surface of the P ⁺ substrate 23.
The epitaxial layer 25 is epitaxially grown. When manufactured in this way, the N ⁻ epitaxial layer 25 and the N ⁺ diffusion region 24
As a result, the N ⁻ base layer 2 ′ of FIG. 1 is formed and the surface region of the P ⁺ substrate 23 where the N ⁺ diffusion region 24 is not formed becomes the P ⁺ collector region 20 of FIG. 1 and the remaining P ⁺ The region of the substrate 23 becomes the P ⁺ collector layer 1 in FIG.

Since the subsequent manufacturing method is the same as the first manufacturing method, description thereof will be omitted. In the IGBT manufactured by the third manufacturing method, the back surface region of the N ⁻ base layer 2 ′ has a high concentration, but this does not adversely affect the operation of the IGBT.

〔The invention's effect〕

As described above, according to the IGBT described in claim 1,
A bipolar transistor on an equivalent circuit, which is a component thereof, includes a first bipolar transistor including a first semiconductor region, a second semiconductor layer having no crystal defect, and a first semiconductor layer having a crystal defect, It can be regarded as equivalent to being configured by parallel connection with a second bipolar transistor including one semiconductor region, a second semiconductor layer having a crystal defect, and a first semiconductor layer having no crystal defect. .

The first bipolar transistor has a crystal defect in the first semiconductor layer but does not have a crystal defect in the second semiconductor layer, and thus has an advantage of low on-resistance and a disadvantage of long turn-off time. On the other hand, the second bipolar transistor has a crystal defect in the second semiconductor layer, and thus has a disadvantage that the on-resistance is high and an advantage that the turn-off time is short.

Therefore, by setting the concavo-convex joint surfaces of the first and second semiconductor layers so as to optimally compensate the disadvantages of the first bipolar transistor and the second bipolar transistor, it is possible to irradiate ionizing radiation such as an ion beam.
This has the effect of maximizing the trade-off relationship between on-resistance and turn-off time.

Further, according to the method for manufacturing an IGBT according to claim 2, the range of distribution of generated crystal defects is smaller than the thickness of the unevenness of the uneven bonding surface of the first and second semiconductor layers, Irradiation is performed from above the main surface on which the main electrode is formed so that the range is near the center of the concavo-convex joint surface. This allows
Crystal defects are formed on the concavo-convex joint surface of the first and second semiconductor layers. Therefore, similarly to the above insulated gate bipolar transistor, it is possible to equivalently configure a bipolar transistor on an equivalent circuit by parallel connection of the first and second bipolar transistors.

Therefore, by forming the concavo-convex joint surface of the first and second semiconductor layers so as to optimally compensate for the shortcomings of the first bipolar transistor and the second bipolar transistor, it is possible to turn on by ionizing radiation such as an ion beam. This has the effect of maximizing the trade-off relationship between resistance and turn-off time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an IGBT according to an embodiment of the present invention,
FIG. 2 is an equivalent circuit diagram thereof, FIG. 3 is a graph showing the relation between the range of hydrogen ions and helium ions, and the half value width of the defect distribution peak. FIG. 4 is the first graph of the IGBT shown in FIG. Sectional drawing showing the manufacturing method, FIG. 5 is a sectional view showing the second manufacturing method of the IGBT shown in FIG. 1, and FIG. 6 is shown in FIG.
FIG. 7 is a sectional view showing the third manufacturing method of the IGBT, and FIG.
FIG. 8 is a cross-sectional view showing BT, FIG. 8 is an equivalent circuit diagram thereof, and FIG. 9 is a graph showing a crystal defect distribution generated by ion irradiation. In the figure, 1 is a P ⁺ collector layer, 2 ′ is an N ⁻ base layer, 3
Is a P well region, 4 is an N ⁺ emitter region, 5 is a gate insulating film, 6 is a gate electrode, 7 is an emitter region, 8 is an insulating film,
Reference numeral 9 is a collector electrode, 20 is a P ⁺ collector region, and 50 is a light ion beam. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A first laminated structure in which a joint surface is uneven.
And first and second semiconductor layers of a second conductivity type, a first semiconductor region of a first conductivity type selectively formed on a surface of the second semiconductor layer, and the first semiconductor Second selectively formed on the surface of the region
An electrically conductive second semiconductor region, an insulating film formed on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region, and the insulating film A control electrode formed on the first and second semiconductor regions, a first main electrode formed over the first and second semiconductor regions, and a second main electrode formed on the back surface of the first semiconductor layer. The insulated gate bipolar transistor, wherein the first and second semiconductor layers have crystal defects within a range of the thickness of the unevenness on the joint surface of the unevenness. 2. A step of stacking a second semiconductor layer of a second conductivity type on a first semiconductor layer of a first conductivity type so that a bonding surface is uneven, and the second semiconductor layer. Selectively forming a first semiconductor region of a first conductivity type on the surface of the semiconductor, and selectively forming a second semiconductor region of a second conductivity type on the surface of the first semiconductor region. A step of forming an insulating film on the surface of the first semiconductor region sandwiched between the second semiconductor layer and the second semiconductor region; and a step of forming a control electrode on the insulating film. A step of forming a first main electrode over the first and second semiconductor regions, a step of forming a second main electrode on the back surface of the first semiconductor layer, From the main surface on which the main electrode is formed, the range is near the center of the concavo-convex joint surface of the first and second semiconductor layers. And a step of irradiating ionizing radiation so that the range of distribution of crystal defects generated at the time of irradiation is smaller than the thickness of the unevenness of the uneven bonding surface is a type of ionizing radiation. , Method for manufacturing insulated gate bipolar transistor.