JPH07321304A - Insulated gate bipolar transistor and its manufacture - Google Patents

Abstract

PURPOSE:To achieve a proper amount of injection of positive holes and a low ON voltage and a small amount of turn-off loss by specifying the total amount of impurity of a collector layer in NPT-type IBGT with a high breakdown voltage. CONSTITUTION:A Gate oxide film 6 is formed on the surface of FZ substrate which becomes n-base layer and then a gate electrode 7 is formed. With the oxide film and the gate electrode as masks, boron is selectively implanted into an n-base layer 3, thus forming a p-base region 4. An n<+>-emitter region 5 is formed by selectively introducing donor-type impurity into one portion of the p-base region 4. Phosphor glass is deposited on the gate electrode 7 as an insulation film 10, an alloy of Al and Si is deposited as an emitter electrode 9 on the surface, and then a p<+>-collector layer 1 is formed on the reverse side by implanting B ion. The total amount of impurity atom of the collector layer 1 is set to 1X10<14>-5X10<15>cm<-2>. Finally, a collector electrode 8 is formed on the surface for completion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) having a MOS structure gate and used as a voltage-driven switching element, and more particularly to its structure and manufacturing method.

[0002]

2. Description of the Related Art In recent years, attention has been paid to a MOSFET, a so-called IGBT, which uses conductivity modulation, as a switching element. Like the MOSFET, this IGBT has a high input impedance, and moreover, the ON resistance can be lowered like the bipolar transistor. Taking advantage of these advantages, the IGBT has been applied to drive a variable-speed motor and horizontal deflection of a television receiver in place of the conventional bipolar transistor, but further high frequency applications are required. There is. Switching semiconductor elements are
Ideally, the total loss including the steady loss and the switching loss is small. However, since the switching loss is proportional to the switching frequency, the higher the frequency is, the more the amount of heat generated by the element increases, and the safe operation area of the element itself becomes narrow.

FIG. 2 shows a sectional view of the basic structure of a punch-through type (hereinafter referred to as PT type) IGBT. Shown in the figure is a unit portion including one control electrode (hereinafter referred to as a cell), and the active region for switching the conduction and interruption of the main current of the IGBT has an extremely large number of such cells. Made of. In addition to such an active region, the IGBT has a breakdown voltage structure portion that shares a breakdown voltage with a peripheral portion surrounding the active region, but it is omitted because it is not a part related to the essence of the present invention. In the figure, n ⁺ is formed on the p ⁺ collector layer 1.
There is an n base layer 3 laminated via a buffer layer 2,
A p base region 4 is selectively formed on the surface layer of the n base layer 3. N ⁺ selectively in the p base region 4
The emitter region 5 is formed, and is made of polycrystalline silicon via the gate oxide film 6 on the surface of the channel region 11 sandwiched between the n base layer 3 of the p base region 4 and the n ⁺ emitter region 5, and the G terminal is formed. A gate electrode 7 connected to the. In addition, the n ⁺ emitter region 5 and the p base region 4
An emitter electrode commonly contacting both regions and connected to the E terminal is formed on the surface of the p ⁺ collector layer 1, and a C electrode is formed on the back surface of the p ⁺ collector layer 1.
Collector electrodes 8 connected to the terminals are respectively provided. In the figure, the emitter electrode 9 is extended on the gate electrode 7 via the insulating film 10.

The n base layer 3 of such an IGBT is p
⁺ Collector layer 1 and n ⁺ buffer layer 2 laminated thereon
It is formed by epitaxial growth on a substrate consisting of. The p base region 4 is first formed by introducing impurities using the previously formed gate electrode 7 as a mask, and the n ⁺ emitter region 5 is formed by introducing impurities using a photoresist (not shown) as a mask. It Then, in this element, when a predetermined voltage is applied between the E terminal and the C terminal, the depletion layer spreads in the n base layer 3,
Punch-through type IGBT because it reaches the n ⁺ buffer layer 2
Is called.

FIG. 1 shows a sectional view of the basic structure of another type of IGBT. The difference from the IGBT of FIG. 2 is that the n ⁺ buffer layer 2 is not provided on the p ⁺ collector layer 1 and the n base layer is in contact therewith. Such an n base layer 3 of the IGBT
Is a floating zone melting (FZ) crystal and pulling in a magnetic field (MC
Z) It is a crystal substrate, and the p ⁺ collector layer 1 portion is formed by ion-implanting acceptor type impurities into the substrate and diffusion heat treatment. The method for forming the p base region 4 and the n ⁺ emitter region 5 is the same as in FIG. Since this element does not have the n ⁺ buffer layer 4 of FIG. 1, when a predetermined voltage is applied between the E terminal and the C terminal, the depletion layer spreads in the n base layer 3.
Since it does not reach the p ⁺ substrate 1, it is called a non-punch through type (hereinafter abbreviated as NPT type) IGBT.

The switching operation of the PT type IGBT is performed as follows. When a voltage higher than the threshold value is applied to the gate electrode 7 with a positive voltage applied to the C terminal with respect to the E terminal, a channel is formed in the channel region 11 on the surface of the p base region 4 directly below the gate electrode 7. Through the channel from the n ⁺ emitter region 5 to the n base layer 3
Is injected into. Since the junction between the n ⁺ buffer layer 2 and the p ⁺ collector layer 1 is forward biased, the electron current injected into the n base layer 3 passes through the n ⁺ buffer layer 2 and the junction Through to the p ⁺ collector layer 1.
Then, holes are injected from the p ⁺ collector layer 1 into the n ⁺ buffer layer 2 and the n base layer 3, and as a result, conductivity modulation occurs in the n ⁺ buffer layer 2 and the star n base layer 3. That is, a pnp transistor having the p ⁺ collector layer 1, n ⁺ buffer layer 2, the n base layer 3, and the p base region 4 as an emitter, a base, and a collector operates, and the hole current injected into the n base layer 3 is generated. This means that the IGBT enters the p base region 4, flows just below the n ⁺ emitter region 5, and escapes to the emitter electrode 9 to turn on the IGBT. In order to turn off this IGBT, the voltage of the gate electrode 7 is removed. Since the emitter electrode 9 short-circuits the p base region 4 and the n ⁺ emitter region 5, the emitter electrode 9 is formed in the channel region 11 immediately below the gate electrode 7. The existing channel disappears, n ⁺
The injection of electrons from the emitter region 5 is stopped, and the operation of the four-layer thyristor including the p ⁺ collector layer 1, the n ⁺ buffer layer 2 and the n base layer 3, the p base region 4 and the n ⁺ emitter region 5 is blocked. , The element can be turned off. NPT type I
The GBT operation is performed in the same manner.

In the PT type IGBT, the n base layer can generally be made thin, so that the switching characteristics are excellent. However, in a high breakdown voltage element, the required thickness of the n base layer 3 becomes large, and it becomes difficult to form the thick n base layer 3 by epitaxial growth. Therefore, the cost of the wafer on which the thick epitaxial layer is formed is high, and as a result, the cost of the device is inevitably high.

On the other hand, in the NPT type IGBT using the FZ and MCZ wafers, the price of the wafer does not increase so much even if the thickness of the wafer increases. Therefore, the cost of the element can be kept low and the withstand capability of the element can be expected to be improved. Therefore, it is considered that the NPT type structure is suitable especially for an element having a high breakdown voltage.

[0009]

[Problems to be Solved by the Invention] Conventional NPT type IGBT
In this case, after forming the p ⁺ collector layer 1 having a sufficient thickness of, for example, 10 μm or more, a lifetime killer such as electron beam irradiation is introduced to adjust the on-voltage and turn-off time. However, the ON voltage of the NPT-type IGBT is controlled by the channel length in the channel region 11 and p ⁺ without controlling by the lifetime killer.
It was found that it can be adjusted by the impurity concentration of the collector layer 1.

When the impurity concentration of the p ⁺ collector layer 1 is increased, the on-voltage is decreased and the turn-off time is increased. On the contrary, if the impurity concentration of the p ⁺ collector layer is lowered,
The on-voltage increases and the turn-off time decreases. In consideration of this trade-off, it is necessary to determine the impurity concentration of the p ⁺ collector layer. The NPT type IGBT is
Since the thickness of the silicon wafer to be used changes depending on the intended breakdown voltage, it is necessary to study the impurity concentration of the p ⁺ collector layer 1 according to the breakdown voltage, that is, according to the specifications of the silicon wafer. In particular, for an element that requires a high breakdown voltage such as 1700 V or higher, the silicon wafer becomes thicker, so it is more important to study the impurity concentration.

In view of the above problems, an object of the present invention is to determine the conditions of the p ⁺ collector layer for obtaining an NPT type IGBT element which is a high breakdown voltage element and has a low on-voltage and a short turn-off time. is there.

[0012]

[Means for Solving the Problems] p ^{+ of} NPT type IGBT
In order to change the impurity concentration of the collector layer, the amount of boron ions implanted was changed. That is, the second conductivity type base region is selectively formed on a part of the surface layer of one main surface of the first conductivity type semiconductor substrate, and is selectively formed on the surface layer of the second conductivity type base region. A first conductive type emitter region, a gate electrode provided on the surface of the second conductive type base region sandwiched between the semiconductor substrate and the first conductive type emitter region via a gate insulating film, and the second electrode. An emitter electrode commonly contacting the surfaces of the conductivity type base region and the first conductivity type emitter region, a second conductivity type collector layer formed on the other main surface of the semiconductor substrate, and provided on the surface of the collector layer. And a collector electrode, the total amount of impurity atoms in the second-conductivity-type collector layer is 1 × 10 ¹⁴ to 1 × 1.
It shall be 0 ¹⁵ cm ^-2 .

Further, preferably, the second conductivity type collector
The total amount of impurity atoms in the data layer is 5 × 10 ¹⁴~ 1 x 10¹⁵cm
^-2And The distribution of impurities in the second conductivity type collector layer
The maximum impurity concentration is 1 × 10 ¹⁹~ 5 x 10²⁰cm^-3
Then, the thickness is preferably 0.1 to 1 μm. Especially the second
The impurity of the conductivity type collector layer is preferably boron.

For this purpose, the collector layer is formed by 1 × 1.
Ion implantation of boron with a dose of 0 ¹⁴ to 1 × 10 ¹⁵ cm ^-2 may be performed.

[0015]

By optimizing the amount of implanted impurities in the above range, the amount of carriers injected from the second conductivity type collector layer is controlled, and the crystal defects at the time of ion implantation are utilized as a lifetime killer to achieve a high breakdown voltage. Even in an NPT type IGBT using a thick silicon wafer with specifications, it is possible to obtain an element having a low ON voltage at a large current, a short turn-off time of the same level as that of the PT type IGBT, and a low turn-on loss.

[0016]

Embodiments of the present invention will be described below with reference to the drawings in which the same parts as those in FIG. FIG. 1 shows a partial cross-sectional view of an NPT-type IGBT having a high withstand voltage specification of 1700 V or higher as an embodiment of the present invention. Figure 3
The difference from the conventional example is that the implantation amount of boron ions at the time of forming the p ⁺ collector layer 1 is optimized.

That is, the p base region 4 is selectively formed in the surface layer on one side of the n base layer 3 made of an FZ or MCZ wafer, and the n ⁺ emitter region is selectively formed in the p base region 4. 5 is formed on the surface of the channel region 11 sandwiched between the n base layer 3 of the p base region 4 and the n ⁺ emitter region 5, and is made of polycrystalline silicon via the gate oxide film 6 to the G terminal. The gate electrode 7 to be connected is provided, the p ⁺ collector layer 1 is formed on the side of the n base layer 3 opposite to the side on which the p base region 4 is formed, and further on the surface of the p ⁺ collector layer 1. Similar to the conventional example, the collector electrode 8 is provided with the source electrode 9 which is commonly contacted with the n ⁺ emitter region 5 and the p base region 4 and is connected to the S terminal.

Such an IGBT is manufactured by the following steps. First, the gate oxide film 6 is formed on the surface of the FZ substrate to be the n base layer 3, and then, after depositing polycrystalline silicon, the gate electrode 7 is formed by the photoetching technique. The gate electrode 7 and the gate oxide film 6
Using the as a mask, boron is selectively ion-implanted into the n base layer 3 to form the p base region 4. p base region 4
By selectively introducing a donor type impurity into a part of the surface layer of n
⁺ Emitter region 5 is formed. Phosphorus glass (PSG) is deposited on the gate electrode 7 to form the insulating film 10, and then an alloy of aluminum and silicon is vapor-deposited on the surface to form the emitter electrode 9. Next, the p ⁺ collector layer 1 is formed on the back surface side by implanting boron ions. Finally, the collector electrode 8 is formed on the surface of the p ⁺ collector layer 1 for completion.

As the conditions for forming the p ⁺ collector layer 1 shown in FIG. 3, the acceleration voltage is 50 keV and the boron ion dose amount is 5 × 10 ¹⁴ cm ^-2, and the maximum concentration is 5 × 10 ^19. It was cm ⁻³ and the thickness was about 0.3 μm.
FIG. 4 illustrates the relationship between the boron ion implantation amount and the on-voltage when the boron ion implantation amount is changed. Since the on-voltage is higher at high temperature, only high temperature results are shown.

Boron ion implantation amount is 1 × 10 ¹² to 1 × 1
In the range of 0 ¹³ cm ^-2 , the on-voltage is as large as 6 V or more,
Not suitable for practical use. Boron ion implantation amount is 1 × 10 ¹⁴ c
At m ⁻² , the on-voltage is 4.5 V, 1 × 10 ¹⁵ cm ⁻²
Then, it turns out that it becomes as low as 3.5V. It is considered that when the amount of implanted boron ions is small, the amount of holes injected from the p ⁺ collector layer 1 to the n base layer 2 is small.

From the above results, when viewed from the ON voltage, 1
For an IGBT with a high withstand voltage of 700 V or higher, p ⁺
The amount of boron ions implanted when the collector layer 1 is formed is 1 × 1.
It means that more than 0 ¹⁴ cm ^-2 is required. Furthermore, 1 × 1
Since the value of ON voltage of 4.5 V at 0 ¹⁴ cm ^-2 is slightly high, it is considered that the boron ion implantation amount of 5 × 10 ¹⁴ cm ^-2 or more is desirable.

In boron ion implantation, almost all the implanted atoms are ionized, so it can be considered that the dose amount is the same as the total amount of impurity atoms per unit area. Therefore, the above value is the optimum total amount of impurity atoms. FIG. 5 is a graph showing the relationship between the boron ion implantation amount and turn-off loss in an NPT type IGBT with a high withstand voltage specification of 1700 V or higher.

When the boron ion implantation amount is more than 5 × 10 ¹⁵ , the turn-off loss is 70 millijoule (mJ).
It is too big and not suitable for practical use. Turn-off loss is 60m when the boron ion implantation amount is 1 × 10 ¹⁵ cm ^-2.
It can be seen that when J is 1 × 10 ¹⁴ cm ^-2 , it is as low as about 40 mJ. From the result of the turn-off loss in FIG. 5, it is desirable that the boron ion implantation amount when forming the p ⁺ collector layer 1 is 5 × 10 ¹⁵ cm ⁻² or less. More preferably, the boron ion implantation amount is 1 × 10 ¹⁵ cm ⁻² or less. Then, as described above, this optimum amount of ion implantation is the optimum total amount of impurity atoms in the p ⁺ collector layer 1.

That is, in the case of an NPT type IGBT using a silicon wafer having a withstand voltage specification of 1700 V or more, the total amount of boron atoms in the p ⁺ collector layer 1 is 1 × 10 ^{14 to} 5 × 10 5.
A range of ¹⁵ cm ^-2 is suitable. . More preferably, it can be said that the optimum range is 5 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . When the range of the total amount of appropriate impurity atoms in the p ⁺ collector layer 1 is converted into the impurity concentration and the thickness of the same layer, the maximum concentration is 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ , and the thickness is Was 0.3 to 0.5 μm. Accelerating voltage is 100 ke
Even with V, the penetration depth of the impurity atoms was slightly increased, but the characteristics did not change much. However, if the thickness is too thick, the hole injection efficiency changes.
It turns out that m is appropriate.

In order to realize the p ⁺ collector layer 1 as described above, the boron ion implantation amount of the p ⁺ collector layer 1 is set to 1.
It is suitable to set it in the range of x10 ^{14 to} 5 x 10 ¹⁵ cm ^-2 . More preferably, it can be said that the optimum range is 5 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . FIG. 6 is a diagram showing a trade-off relationship between the on-voltage and the turn-off loss. 1 x 10
The experimental values from ¹² to 1 × 10 ¹⁵ cm ^-2 are shown as △,
The symbols are changed in the order of ▲, □, ○, ●. The figure simultaneously shows the trade-off relationship between two types of epitaxial wafer PT-type IGBTs. PT needs attention
The type IGBT uses titanium as a contact metal between the back surface p ⁺ collector layer 1 and the electrode, whereas the NPT type IGBT uses aluminum, which is different in contact property. Strict analysis requires examination of the difference between the two,
As a simple characteristic comparison, it can be done as it is. The relationship between the on-voltage and the turn-off loss in the NPT type IGBT is
It can be seen that it is within the same relationship in the PT type IGBT. That is, the trade-off relationship between the ON voltage and the turn-off loss of the NPT type IGBT is not inferior to that of the PT type IGBT.

The boron ion implantation amount is 1 × 10 ¹² to
In the range of 1 × 10 ¹³ cm ^-2 , the turn-off loss is suppressed to a low level, but the on-voltage is high as described above, which is not suitable for practical use. On the other hand, if the boron ion implantation amount is too high,
The turn-off loss increases and the tail current also increases, which is not good in terms of characteristics. In order to realize the p ⁺ collector layer 1 as described above, it is appropriate to set the boron ion implantation amount of the p ⁺ collector layer 1 in the range of 1 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² . More preferably, 5 × 10 ¹⁴ to 1 × 10 ¹⁵ c
It can be seen from this figure that the optimum value is m ^-2 .

The FZ wafer used is a conventional PT type IGB.
Compared with the epitaxial wafer used for T, it is advantageous in that it is not only inexpensive, but also has high crystal perfection, so that the breakdown resistance of the semiconductor element formed therefrom is large. Also,
Since the p ⁺ collector layer 1 is formed only by ion implantation, there is no need for a high-temperature heat treatment for a thick diffusion layer and a process for introducing a lifetime killer, which is required in the prior art, the process can be shortened, and the control is extremely controlled. Another feature is that it is easy to remove.

[0028]

As described above, according to the present invention,
In the high breakdown voltage NPT type IGBT, the total amount of impurity atoms in the second conductivity type collector layer is set to 1 × 10 ^{14 to} 5 × 10 ^15.
By setting the range of cm ⁻² , the optimal hole injection amount can be achieved, a low on-voltage and a low turn-off loss can be realized, and an PT type IGB using an expensive epitaxial wafer is used.
It is possible to obtain an NPT type IGBT having a tradeoff equivalent to that of T.

In particular, an FZ wafer or M having a high crystal perfection is used.
By using a CZ wafer, a device having a high breakdown resistance can be obtained. Moreover, since only ion implantation is required, the process is easy, and in particular, there is a great advantage in practical application of a high breakdown voltage, large capacity IGBT.

[Brief description of drawings]

FIG. 1 is a partial sectional view of an IGBT according to an embodiment of the present invention.

FIG. 2 is a partial sectional view of a conventional PT-type IGBT.

FIG. 3 is a partial cross-sectional view of a conventional NPT type IGBT.

FIG. 4 is a diagram showing a relationship between a boron ion implantation amount and an on-voltage.

FIG. 5 is a diagram showing a relationship between on-voltage and turn-off loss.

FIG. 6 is a diagram showing a trade-off relationship between on-voltage and turn-off loss.

[Explanation of symbols]

1 p ⁺ collector layer 2 n ⁺ buffer layer 3 n base layer 4 p base region 5 n ⁺ emitter region 6 gate oxide film 7 gate electrode 8 collector electrode 9 emitter electrode 10 insulating film 11 channel region

Claims (5)

[Claims] 1. A second conductivity type base region selectively formed on a part of a surface layer of one main surface of a first conductivity type semiconductor substrate, and a surface layer of the second conductivity type base region. And a gate electrode provided on the surface of the second conductivity type base region sandwiched between the semiconductor substrate and the first conductivity type emitter region via a gate insulating film. An emitter electrode commonly contacting the surfaces of the second conductivity type base region and the first conductivity type emitter region, and a second conductivity type collector layer formed on the other main surface of the semiconductor substrate,
An insulated gate bipolar transistor having a collector electrode provided on the surface of the collector layer, wherein the total amount of impurity atoms in the collector layer is 1 × 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 . 2. The insulated gate bipolar transistor according to claim 1, wherein the total amount of impurity atoms in the second-conductivity-type collector layer is 5 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² . 3. The maximum impurity concentration of the second conductivity type collector layer is 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ , and the thickness is 0.1 to 10.
The insulated gate bipolar transistor according to claim 1, wherein the insulated gate bipolar transistor has a thickness of 1 μm. 4. The insulated gate bipolar transistor according to claim 1, wherein the impurity of the second conductivity type collector layer is boron. 5. The formation of the collector layer of the second conductivity type is 1 ×
The method for producing an insulated gate bipolar transistor according to claim 1, wherein the ion implantation is performed with a dose amount of 10 ^{14 to} 5 × 10 ¹⁵ cm ^-2 .