JP2002299346A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent breakdown voltage from lowering and contact resistance increase, while increasing the ion activation coefficient in an ion implanted layer and reducing on-voltage. SOLUTION: Cooled ion implantation 12 of BF2 is carried out on a back-side face 11 of a back-lapped semiconductor wafer (FZ n-type wafer 1) to form an ion-implanted layer 13 Fig. (b)}. Then, heat treatment is carried out, to form a high-concentration p-type collector layer 8 (p<+> diffused layer) Fig. (c)}. This ion implantation is a cooled ion implantation, in which the ions are implanted into the substrate (FZ n-type wafer 1) which is cooled at liquid nitrogen temperature (-196 deg.C), where the dose quantity is set at 3×10<13> cm<-2> or higher.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor).
In Bicolor Transistor,
IGBT) and insulated gate thyristors.

[0002]

2. Description of the Related Art In recent years, an important part of a computer or a communication device is integrated with a large number of transistors, resistors and the like so as to constitute an electric circuit, and is integrated on one chip to form an integrated circuit (hereinafter referred to as an IC). Is often used. Among such ICs, those that include a power semiconductor element are called power ICs.

An IGBT is a power semiconductor device in which the high-speed switching and voltage driving characteristics of a MOSFET and the low on-voltage characteristics of a bipolar transistor are formed on a single chip. The application of IGBTs to industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), and switching power supplies, as well as consumer electronics such as microwave ovens, rice cookers, and strobes has been expanding. Furthermore, development to the next generation is progressing, and a device with a lower on-voltage using a new chip structure has been developed, and a reduction in loss and a higher efficiency of an application device have been achieved.

The IGBT has a punch-through type, a non-punch-through type, a field stop type, and the like. Almost all IGBTs currently mass-produced have an n-channel vertical double diffusion structure except for a part of a p-channel type for an audio power amplifier. Hereinafter, each structure will be described using an n-channel IGBT as an example.

In the punch-through type, an n ⁺ layer (n ⁺ n) is provided between ap ⁺ epitaxial substrate (p ⁺ substrate) and an n ^- layer (n active layer).
A buffer layer is provided, and a depletion layer in the n active layer reaches the n buffer. The IGBT has a mainstream substrate structure. For example, for a 600 V breakdown voltage system, the thickness of the n active layer is about 100 μm is sufficient, but the total thickness is 300 to 400 μm including the p ⁺ substrate portion. Therefore, instead of using an epitaxial substrate, an inexpensive FZ substrate (a semiconductor substrate manufactured by a floating zone method) is used, and a low dose shallow p ⁺
Non-punch-through and field stop types having a collector layer have been developed.

FIG. 10 shows a cross-sectional structure of a non-punch-through (NPT) type IGBT employing a low dose shallow p ⁺ collector layer. Low dose shallow p-type collector layer 58
The non-punch-through type adopting the (low implantation p ⁺ collector layer) does not use a p ⁺ substrate like an epitaxial growth substrate, so that the total substrate thickness is much smaller than the punch-through type. In this structure, the hole injection efficiency can be controlled by the concentration of the p-type collector layer 58, so that high-speed switching is possible without performing lifetime control. Since it depends on the thickness and the specific resistance of the FZ-n substrate 51) sandwiched between the P-type collector layer 58 and the p-type collector layer 58, the value is slightly higher. However, as described above, since an inexpensive FZ substrate is used without using an expensive p ⁺ epitaxial substrate, the cost of a chip can be reduced.

In the figure, 53 is an n-type emitter layer, 54 is a gate oxide film, 55 is a gate electrode, 56 is an interlayer insulating film,
57 is an emitter electrode, and 59 is a collector electrode. FIG.
1 is a sectional structure of a field stop (FS) type IGBT. The basic structure is the same as that of the punch-through IGBT, but without using the p ⁺ epitaxial substrate,
Using the Zn substrate 51, the total thickness of the substrate is 150 μm to 2 μm.
It is set to 00 μm. As with the punch-through type, the n active layer (p type base layer 52 and n type field stop layer 60)
FZ-n substrate 1) sandwiched between
It is about 00 μm and depleted. Therefore, n
An n ⁺ layer (n-type field stop layer 60) is formed under the active layer.
, Which performs the same function as the n-type buffer layer). On the collector side, a shallow p ⁺ diffusion layer having a low dose is used as a low-implantation p-type collector layer 58. This eliminates the need for lifetime control as in the non-punch-through type.

In order to reduce the on-voltage, a trench IGBT having a narrow and deep groove formed on the chip surface and a channel formed on the side surface is formed by a non-punch-through type I / O.
Some have a structure combining a GBT and a field stop IGBT. FIG. 12 shows a conventional NPT-IGBT.
FIGS. 3A to 3D are cross-sectional views of a main part of a main process. (1) A gate oxide film 54 is formed on the front side of the FZ-n substrate 51a.
And a gate electrode 55 made of polycrystalline silicon are deposited and processed, and an interlayer insulating film 56 is deposited and processed on the surface thereof to form an insulated gate structure. (2) After forming a p-type base layer 52 on the FZ-n substrate 51a, an n-type emitter layer 5 is formed in the p-type base layer 52.
Form 3 (3) An emitter electrode 57 made of an aluminum / silicon film is formed so as to be in contact with the n-type emitter layer 53. Aluminum·
The silicon film is formed to have a stable bonding property to realize a low-resistance wiring, and then is subjected to a heat treatment. Further, although not shown, an insulating protective film made of a polyimide film is formed so as to cover the emitter electrode 57. (4) Next, the FZ-n substrate is back-wrapped from the back side to a desired thickness (FIG. 7A). (5) Next, a high concentration p-type collector layer (p ⁺ diffusion layer)
In order to form, a normal room temperature ion implantation 71 of boron is performed from the back surface 61 (FIG. 3B), and thereafter, a heat treatment is performed (FIG. 3C). (6) Thereafter, a collector electrode 59 is formed on the p-type collector layer 58 by using a back electrode film composed of four layers of an aluminum layer, a titanium layer, a nickel layer, and a gold layer (FIG. 4D). Finally, although not shown, (7) an aluminum wire is fixed on the surface of the emitter electrode 57 by an ultrasonic wire bonding apparatus, and the other collector electrode 59 is connected to a fixing member via a solder layer. .

However, in order to obtain desired characteristics in a thin IGBT structure using these FZ substrates, heat treatment and diffusion steps are important technologies. Hereinafter, the aluminum / silicon film of (3) and the back surface ion implantation and heat treatment of (5) related to the heat treatment and diffusion steps will be described. First, regarding the process (3), the emitter electrode 57
The aluminum-silicon film (having a silicon content of 1% or less) is used to form a substrate temperature of 150% by a sputtering method.
C., and the film thickness was 5 μm. afterwards,
The heat treatment is performed in an electric furnace at 420 ° C. for 80 minutes.
When the heat treatment is performed at a high temperature exceeding 500 ° C., silicon atoms in the aluminum / silicon precipitate between the interlayer insulating film 56 and the interlayer insulating film 55 is broken by a pressing force at the time of wire bonding starting from silicon precipitates. Then, if the breakdown voltage between the gate electrode 55 and the emitter electrode 57 is reduced, or if the pressing force at the time of wire bonding is reduced in order to prevent the breakdown voltage, the wire and the emitter electrode 57 may be degraded.
Inconvenience that the adhesiveness with the adhesive decreases.

FIG. 13 shows a silicon deposition state when heat treatment is performed at a high temperature exceeding 500 ° C. 75 in the figure
Are silicon precipitates. FIG. 14 is a diagram showing a state in which wire bonding is performed in the state of FIG. 12, a crack occurs in the interlayer insulating film, and a short circuit between the gate and the emitter occurs. The pressure applied during the wire bonding is locally applied to the interlayer insulating film 55 by the silicon precipitate particles 75, and a crack 76 is generated.

FIG. 15 shows the relationship between the silicon precipitation grain size and the breakdown voltage ratio, and FIG. 16 shows the relationship between the heat treatment temperature of the aluminum / silicon film and the silicon precipitation grain size. When the silicon precipitation particle size is increased, the pressure resistance failure increases, and in order to reduce the silicon precipitation particle size to 1 μm or less, the heat treatment temperature must be set at 500 μm or less.
It is understood that the temperature needs to be lower than or equal to ° C. Next, in the step (5), the p-type diffusion layer (here, the impurity is boron), which is the p-type collector layer 58, allows holes to be efficiently injected, and further, the collector electrode formed in the step (6). In order to form a good contact with the back electrode, which is 59, it is necessary to be shallow and have a high concentration. Here, the ion implantation is performed at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 45 keV, and the heat treatment is performed at 420 ° C. in an electric furnace at a low temperature for 1 hour. This temperature is determined in step (3).

FIG. 17 shows the concentration distribution of the p-type collector layer obtained by the spread resistance method. In an electric furnace heat treatment (electric furnace annealing) at 420 ° C. for 1 hour, the peak concentration was also 5 × 1.
0 ¹⁷ cm ^-3 or less, not shown, 900 ° C, 30m
The ion activation rate is very low, 2%, as compared with a sample (ion activation rate: 80%) which is sufficiently activated by heat treatment (annealing) in an electric furnace in.

[0013]

Next, the problems of the above-mentioned prior art will be described. (1) The annealing temperature of a film containing aluminum as a main component such as an aluminum / silicon film is set to a high temperature (> 500
℃), the withstand voltage is degraded due to silicon precipitates, or the contact resistance is increased. (2) When annealing at a low temperature of 500 ° C. or less to avoid (1), the ion activation rate of the back surface diffusion layer (p layer in this case) is about 1 to 2% (boron dose is 1 × 10 ¹⁵ c).
(in the case of m ⁻² implantation), it is impossible to obtain a device having good characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to increase the ion activation rate of an ion implantation layer to lower the on-state voltage, and to prevent a decrease in breakdown voltage and an increase in contact resistance. Is to provide.

[0015]

In order to achieve the above object, after a first main electrode is formed on one surface of a semiconductor substrate, an ion implantation layer is formed on the other surface of the semiconductor substrate. In the method for manufacturing a semiconductor device in which a second main electrode is formed on an ion-implanted layer, the method may include forming the ion-implanted layer by cooling ion implantation and performing low-temperature annealing after the cooling ion implantation.

Further, the first main electrode is formed of a metal film containing aluminum as a main component. The dose of the ion-implanted layer is set to 3 × 10 ¹³ cm ⁻² or more. The dose of the ion-implanted layer is 1 × 10 ¹⁴
cm ⁻² or more and less than 1 × 10 ¹⁵ cm ⁻² .

Further, the temperature of the semiconductor substrate at the time of the cooling ion implantation is set to be lower than room temperature and the temperature of liquid nitrogen (−196 ° C.)
The above high temperature is set. Further, the low-temperature annealing temperature is set to 300 ° C. or more and 500 ° C. or less. Further, the ion implantation layer is made of boron (element symbol: B) or BF ₂
May be formed by cooling ion implantation.

As described above, cooling ion implantation is used for forming the ion implantation layer on the back surface, and then low-temperature annealing is performed. In the cooling ion implantation, a layer having few defects can be formed at the time of ion implantation, and by performing low-temperature annealing on the layer, the layer formed on the silicon surface side is not affected, that is, an interlayer insulating film is not formed at the time of wire bonding. The rear surface diffusion layer can be activated without causing a problem such as destruction (short between the gate and the emitter).

[0019] formation of the back surface of the ion-implanted layer by ion implantation of boron or BF _2, then, carried out using a low-temperature annealing. In the boron ion implantation, a continuous amorphous layer can be formed at the time of cooling ion implantation, and the low-temperature annealing is performed on the amorphous layer without affecting the silicon front-side formed layer, thereby reducing the activation of the backside diffusion layer. Can be achieved.

In the case of BF _{2 having} a large mass, a continuous amorphous layer is formed even by ion implantation at room temperature, but the amorphous layer is formed thinner by cooling ion implantation.
In the case of BF ₂ , the thickness of the ion-implanted layer is smaller and the ion activation rate can be higher than in the case of boron.

[0021]

1A to 1D show a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS. 1A to 1D are cross-sectional views of main parts of main steps. . This semiconductor device is an NPT-IGBT. (1) On the front side of the semiconductor substrate (FZ-n substrate 1a) before backlap, a gate oxide film 4 (here, Si
O ₂ ) and polycrystalline silicon (here, Poly-Si)
Is deposited and processed, and an interlayer insulating film 6 (here, BPSG: boron phosphorus glass) is deposited and processed on the surface thereof to form an insulated gate structure. (2) After forming the p-type base layer 2 (p ⁺ ) on the FZ-n substrate 1a, and then forming the p-type base layer 2,
An n-type emitter layer 3 (n ⁺ ) is formed in the mold base layer 2. (3) A surface electrode (emitter electrode 7) made of an aluminum / silicon film is formed in contact with the n-type emitter layer 3.
The aluminum / silicon film is thereafter subjected to a heat treatment in order to realize stable bonding and low-resistance wiring. Further, although not shown, an insulating protective film made of a polyimide film is formed so as to cover the emitter electrode 7. (4) Next, from the back side, the FZ-n substrate 1 is formed to a desired thickness.
a is back-wrapped (FIG. 7A). (5) Next, the back-wrapped semiconductor substrate (FZ-n
From the back surface 11 of the substrate 1), boron ion implantation 12 of boron is performed.
To form an ion-implanted layer 13 (FIG. 2B). Thereafter, heat treatment is performed to form a high-concentration p-type collector layer 8 (p
⁺ Diffusion layer). (Figure (c)).

This ion implantation is cooling ion implantation, and the temperature of the semiconductor substrate (FZ-n substrate 1) is raised to the liquid nitrogen temperature (-1).
96 ° C.), and the dose is set to 3 × 10 ¹³ or more as described later. Preferably, 1 × 1
It is good to be more than 0 ^{14 and} less than 1 × 10 ¹⁵ cm ⁻² . Also,
The heat treatment is performed by electric furnace annealing as described later. The temperature may range from 300 ° C. to 500 ° C., the time may range from 10 minutes to 5 hours, and more preferably, the temperature is from 400 ° C. to 450 ° C., and the time is from 30 minutes to 1.5 hours. (6) Thereafter, on the p-type collector layer 8, a collector electrode 9 which is a back electrode film composed of four layers of an aluminum layer, a titanium layer, a nickel layer, and a gold layer is formed (FIG. 4D).

Finally, although not shown, (7) an aluminum wire is fixed on the surface of the front electrode film (emitter electrode 7) by an ultrasonic wire bonding apparatus, and the other back electrode film (collector electrode 8). Are connected to a fixing member via a solder layer. Since the steps (1) to (4) and the steps (6) and (7) have the same contents as those described in the related art, description thereof will be omitted. The above (5)
Is a manufacturing process of the present invention, and details thereof will be described below.

The ion implantation process is performed not in a normal implantation at room temperature but in a cooled state. In the low-temperature annealing, electric furnace annealing (420 ° C., 1 hour) is performed. Here, the liquid nitrogen temperature (−196 ° C .:
The ion implantation (cooling ion implantation) at an absolute temperature of 77K and annealing at 420 ° C. for 1 hour in an electric furnace will be compared with a conventional example in which ion implantation is performed at room temperature (room temperature ion implantation).

Boron ion implantation by cooling ion implantation 12
Layer 13 (p layer) is dosed at 3 × 10 ¹³cm^-2~ 1 × 10
¹⁵cm^-2Formed under the condition of an acceleration voltage of 45 keV
Then, electric furnace annealing was performed at 420 ° C. for 1 hour.
Make a sample. Normal ion implantation (room temperature ion implantation)
Implantation) to a boron ion implantation layer (p layer) with a dose of 1 ×
10¹³cm^-2~ 1 × 10¹⁵cm^-2Acceleration voltage 4
The film was formed under the condition of 5 keV, and then the electric furnace annealing was performed for 4 hours.
A sample is prepared at 20 ° C. for 1 hour.

These samples were subjected to the spread resistance method (SR method).
Measure the concentration distribution more. Dose is 5 × 10¹³cm^-2Less than
Above, the cold ion implantation is faster than the room temperature ion implantation.
High density. The diffusion depth depends on the cooling ion injection.
The implantation can be shallower than room temperature ion implantation. FIG.
Ron's dose is 3 × 10¹⁴cm^-2Concentration distribution diagram in case of
It is. A is for cold ion implantation, and B is for room temperature ion implantation.
Is on. This figure shows that the dose amount is 1 × 10¹³cm
^-2~ 1 × 10¹⁵cm^-2Of the ranges, 3 ×
10 ¹⁴cm^-2I mentioned the case. Peak concentration C of A_PAWho
Is the peak concentration C of B_PBHigher than the peak concentration,
It is shown that the diffusion depth of A is shallower.

FIG. 3 is a graph showing the relationship between the boron implantation dose and the peak concentration. C is a cooling ion implantation and D is a room temperature ion implantation. The cooling ion implantation (C) can increase the peak concentration at an implantation dose of 3 × 10 ¹³ cm ⁻² or more than the room temperature ion implantation (D).
FIG. 4 is a graph showing the relationship between the dose of boron implantation and the sheet resistance. C is a cooling ion implantation and D is a room temperature ion implantation. This figure corresponds to FIG.
The cooling ion implantation (C) can achieve lower resistance than the room temperature ion implantation (D) at an implantation dose of 3 × 10 ¹³ cm ⁻² or more.

FIG. 5 is a graph showing the relationship between the ion implantation rate and the boron implantation dose. C is a cooling ion implantation and D is a room temperature ion implantation. The ion activation rate of the cooled ion implantation (C) can be larger than that of the room temperature ion implantation (D) at an implantation dose of 3 × 10 ¹³ cm ⁻² or more. In the cooling ion implantation (C), when the dose is set to 1 × 10 ¹⁴ cm ⁻² or more and less than 1 × 10 ¹⁵ cm ⁻² , the ion activation rate can be set to 15% or more.

As described above, by using the cooling ion implantation method, the ion activation rate of the ion implantation layer forming the p-type collector layer 8 can be increased at a dose of 3 × 10 ¹³ cm ⁻² or more.
It can be higher than room temperature ion implantation. Further, by setting the dose to 1 × 10 ¹⁴ cm ⁻² or more and less than 1 × 10 ¹⁵ cm ⁻² , the ion activation rate can be 15% or more.

As described above, the p-type collector layer 8 having a high peak concentration can be formed by the high activation of the p-type collector layer 8. As a result, the efficiency of hole injection from the p-type collector layer 8 can be increased, and the on-voltage can be reduced. In addition, a high ion activation rate can be obtained by the cooling ion implantation, so that the annealing temperature can be lowered, and silicon precipitation particles are not formed on the aluminum / silicon film forming the emitter electrode 7, so that the wire bonding time is reduced. Of the interlayer insulating film 6 and occurrence of cracks or the like can be prevented.

Further, the ohmic property of the p-type collector layer 8 and the collector electrode 9 of the IGBT can be improved with a low dose and a low annealing temperature due to the high ion activation rate. When the dose is the same as the conventional dose, a high-concentration p-type collector layer 8 can be formed, and holes from the p-type collector layer 8 to the base layer (FZ-n substrate 1) can be formed. The injection efficiency can be increased, and the trade-off between the ON characteristics and the switching characteristics of the IGBT can be improved.

Further, the above-mentioned electric furnace annealing (heat treatment)
Temperature ranges from 300 ° C to 500 ° C for a time of 10
It may be determined by a combination of minutes to 5 hours. 500
If the temperature exceeds ℃, silicon precipitate particles are generated on the collector electrode 9, which is not preferable. If the temperature is lower than 300 ° C., the annealing effect is weak, and the contact resistance between the p-type collector layer 8 and the collector electrode 9 increases (the ohmic property is not good), which is not preferable.

The temperature and time range from 400 ° C. to 450
When the temperature and the temperature are determined in the range of 30 minutes to 1.5 hours, it is more preferable to obtain the above-mentioned high ion activation rate.
6A to 6C show a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS. 6A to 6C are cross-sectional views of main parts of main steps. This semiconductor device is an FS-IGBT
(Field stop type IGBT), and the content described here is the step (5) in FIG.

A phosphorus ion implantation layer 15 serving as an n-type field stop layer 10 is formed on the back surface 11 of the FZ-n substrate 1 by room-temperature ion implantation 14 (FIG. 1A). Then, a boron ion-implanted layer 17 to be the p-type collector layer 8 is formed (FIG. 3B), and thereafter, annealing is performed in an electric furnace to form the n-type field stop layer 10 and the p-type collector layer 8 (FIG. Figure (c). Thereby, the FS-IGB having the n-type field stop layer
T.

Next, the optimum dose of the cooling ion implantation 17 will be described. In order to apply to the FS-IGBT (field stop type IGBT), first, in order to form an n type field stop layer, phosphorus (n layer)
At room temperature with a dose of 1 × 10 ¹³ cm ^-2 ,
At an acceleration voltage of 240 keV and room temperature (RT),
In order to form a p-type collector layer by cooling ion implantation,
Boron ion-implanted layer (p-layer) with a dose of 3 × 10 ¹³ c
The acceleration voltage is 45 keV in the range of m ⁻² to 1 × 10 ¹⁵ cm ^−2.
At 420 ° C. for 1 hour by electric furnace annealing
A sample is manufactured. Further, a sample in which normal room temperature ion implantation is performed after phosphorus is implanted under the same conditions is manufactured.

Comparison between the two shows that the cooling ion implantation is
But 3 × 10 better than room temperature ion implantation ¹³cm^-2Dose of
Improve boron (p-layer) peak concentration above the amount
Can be activated. From this, the second real
Also in the case of the embodiment, there is a range of the dose amount in the case of the first embodiment.
It is effective. In addition, cooling ion implantation temperature, low temperature annealing temperature
The degree, time and thickness of the p-type collector layer are also the first.
The same range as in the embodiment is effective.

FIG. 7 shows that the dose of boron is 3 × 10 ¹⁴ c
It is a density distribution figure in the case of m- ² . Here, a case where the dose is 3 × 10 ¹⁴ cm ⁻² as a typical example in the range of the dose 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² is described.
E is a cooling ion implantation and F is a room temperature ion implantation. Towards the peak concentration C _PA of E is than the peak concentration C _PB of F, becomes high peak concentration, a diffusion depth has been shown towards the E becomes shallow.

Although the first and second embodiments have been described in connection with the case where the ion species is boron, the dose, the cooling ion implantation temperature, and the low-temperature annealing temperature can also be obtained when the BF ₂ having a large mass is substituted. The same effect can be expected in the same range with respect to time. However, since BF ₂ has a larger mass number than boron, the acceleration energy is 60
keV.

FIG. 8 is a diagram showing the relationship between the impurity concentration and the diffusion depth when BF ₂ is implanted with cooling ions under the conditions of FIG. The diffusion depth is 0.4 for boron shown in FIG.
It becomes shallower to 0.2 μm than μm. Further, the impurity concentration is higher than in the case of boron, and the ion activation rate is higher. For reference, the impurity profile at the time of room temperature ion implantation is shown by a dotted line.

FIGS. 9A and 9B show the state of the ion implantation layer when boron ions are implanted. FIG. 9A shows the case of room temperature ion implantation, and FIG. 9B shows the case of cooling ion implantation. In the room temperature ion implantation 21 of boron, an ion implantation layer 22 having many point defects is formed to a deep portion at the time of ion implantation. Since there are many point defects, an impurity layer is formed at a very low ion activation rate of several percent in the subsequent low-temperature annealing.

On the other hand, in the cooling ion implantation, a continuous amorphous layer 24 having a small number of point defects can be formed at the time of ion implantation.
4 changes into an impurity layer at a high ion activation rate. The continuous amorphous layer 24 can be obtained at a dose of 3 × 10 ¹³ cm ⁻² or more, and is particularly remarkable at a dose of 1 × 10 ¹⁴ cm ⁻² or more.

When the dose increases, the amorphous layer 24 tends to be formed on the surface layer like the amorphous layer 25. Therefore, the diffusion of the impurity profile increases as the dose increases. The depth decreases. This does not tend to be seen with room temperature ion implantation. In the case of BF _{2 having} a large mass, a continuous amorphous layer is formed even at room temperature ion implantation. However, with cooling ion implantation, the amorphous layer is formed on the surface layer and the thickness of the amorphous layer is reduced. Is thinner than at room temperature. The ion activation rate in the low temperature annealing is also higher than that of boron, so that the peak concentration is higher than that of boron. These are shown in FIG.

The first embodiment and the second embodiment are summarized as follows. (1) According to the mechanism described with reference to FIG. 9, when boron is cooled and ion-implanted at a temperature lower than room temperature, a high ion activation rate can be obtained. Therefore, at this stage, a remarkable effect is obtained at the liquid nitrogen temperature (−196 ° C.).
There is a possibility that a high activation rate can be obtained even at about ° C or lower.
Therefore, the temperature of the cooling ion implantation is lower than room temperature,
The temperature is set to a high temperature of 196 ° C. or higher. Preferably, -30 ° C
Below, -196 degreeC or more is good. (2) An annealing effect appears when the temperature of the electric furnace annealing is 300 ° C. or more, and when it exceeds 500 ° C., silicon of the emitter electrode 7 is deposited and the withstand voltage starts to decrease. Therefore, the annealing temperature is set to 300 ° C. or more and 500 ° C. or less. Preferably, the temperature is 400 ° C. or higher and 450 ° C. or lower. (3) Unless the annealing time is set to a shorter time as the annealing temperature is higher, the breakdown voltage also decreases due to precipitation.
Therefore, when the annealing temperature is 350 ° C., the time is preferably within 5 hours. In the case of 500 ° C., if the annealing time is less than 10 minutes, the annealing effect is weak, and it takes 10 minutes or more. Therefore, the annealing time is 10 minutes or more and 5 hours or less. Preferably, it is 30 minutes or more and 1.5 hours or less. (4) By combining the conditions of (1) to (3),
The thickness of the p-type collector layer 8 is 0.3 μm to 0.5 μm.
Is obtained. (5) In the case of cooling ion implantation of BF ₂ , the same effect can be expected in the range of items (1) to (3), similarly to the case of cooling ion implantation of boron.

Although not described in detail here, instead of electric furnace annealing, a XeCl excimer laser (wavelength 308 nm, half width 49 ns), a XeF excimer laser (wavelength 351 nm, half width 14 ns), KrF
By using an excimer laser (wavelength 248, laser using the second harmonic of YAG (wavelength 532 nm), laser using the third harmonic of YAG (wavelength 355 nm), etc., the activation rate can be improved. Of course.

[0045]

According to the present invention, 3 × 10 ¹³ cm ⁻² or more (preferably 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ^−2).
By performing the cold ion implantation of boron (B) or BF ₂ at a dose of less than about 1), a high ion activation rate can be obtained. Due to the high ion activation rate, the ohmic properties of the collector layer and the collector electrode of the IGBT can be improved with a small dose and a low annealing temperature.

Further, the annealing temperature can be lowered by the cooling ion implantation, and silicon precipitation particles are not formed on the aluminum / silicon film forming the emitter electrode.
It is possible to prevent the destruction of the interlayer insulating film and the occurrence of cracks and the like during wire bonding. When the dose is the same as the conventional dose, a high-concentration collector layer can be formed, the efficiency of injecting holes from the collector layer into the base layer is increased, and the ON characteristics and the switching characteristics of the IGBT are improved. Trade-offs can be improved.

By performing cooling ion implantation (and low-temperature annealing) on the diffusion of the ion implantation layer on the back surface, holes can be efficiently implanted without affecting the front side, and
Good contactor formation with the collector electrode (backside electrode) can be performed. Thus, a power semiconductor element requiring a back surface process can be manufactured with high productivity.

[Brief description of the drawings]

FIGS. 1A to 1D show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which FIGS.

FIG. 2 is a concentration distribution diagram when the dose amount of boron is 3 × 10 ¹⁴ cm ⁻² .

FIG. 3 is a graph showing a relationship between a peak concentration and an implantation dose of boron.

FIG. 4 is a graph showing the relationship between the dose of boron and the sheet resistance.

FIG. 5 is a diagram showing a relationship between an activation dose and an implantation dose of boron.

6 (a) to 6 (c) are cross-sectional views of main steps of a main step of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a graph showing a concentration distribution when a p-layer and an n-layer are superimposed when the boron dose is 3 × 10 ¹⁴ cm ⁻² ;

8 is a diagram showing the relationship between the impurity concentration and the diffusion depth when BF ₂ is implanted with cooling ions under the conditions of FIG. 2;

FIGS. 9A and 9B are views showing the state of an ion implantation layer when cooling ion implantation is performed. FIG. 9A is a diagram showing room temperature ion implantation, and FIG. 9B is a diagram showing cooling ion implantation.

FIG. 10 is a sectional structural view of a non-punch-through (NPT) type IGBT employing a low dose shallow p ⁺ collector layer;

FIG. 11 is a sectional structural view of a field stop (FS) type IGBT;

FIG. 12 shows a conventional method for producing an NPT-IGBT,
(A) to (d) are cross-sectional views of main processes of main processes.

FIG. 13 is a diagram showing a silicon deposition state when heat treatment is performed at a high temperature exceeding 500 ° C.

FIG. 14 is a diagram in which cracks have occurred in an interlayer insulating film.

FIG. 15 is a diagram showing a relationship between a silicon deposition particle size and a breakdown voltage failure rate.

FIG. 16 is a diagram showing the relationship between the heat treatment temperature of an aluminum / silicon film and the grain size of silicon deposition.

FIG. 17 is a concentration distribution diagram of a p-type collector layer obtained by a spreading resistance method.

[Explanation of symbols]

 Reference Signs List 1 FZ-n substrate (after backlap) 1a FZ-n substrate (before backlap) 2 p-type base layer 3 n-type emitter layer 4 gate oxide film 5 gate electrode 6 interlayer insulating film 7 emitter electrode 8 p-type collector layer 9 Collector electrode 10 n-type field stop layer 11 back surface 12 cooling ion implantation 13 ion implantation layer 14 room temperature ion implantation (phosphorus) 15 ion implantation layer (phosphorus) 16 cooling ion implantation (boron) 17 ion implantation layer (boron) A, C, E Cooled ion implanted products B, D, F Room temperature ion implanted products

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 655 H01L 29/74 601B (72) Inventor Masanobu Nozawa 1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kawasaki, Kanagawa Prefecture No.1 Fuji Electric Co., Ltd. F term (reference) 4M104 AA01 BB01 BB02 BB03 CC01 DD22 DD26 DD78 EE03 EE05 EE15 EE16 FF13 HH06 HH15 5F005 AB03 AD02 AE09 AH01 GA01

Claims (7)

[Claims] 1. A semiconductor comprising: a first main electrode formed on one surface of a semiconductor substrate; an ion implantation layer formed on the other surface of the semiconductor substrate; and a second main electrode formed on the ion implantation layer. In the method for manufacturing a device, a method for manufacturing a semiconductor device, wherein the ion-implanted layer is formed by cooling ion implantation and performing low-temperature annealing after the cooling ion implantation. 2. The method according to claim 1, wherein the first main electrode is formed of a metal film containing aluminum as a main component. 3. The ion implantation layer has a dose of 3 × 10
3. The method according to claim 1, wherein the ^{thickness is 13} cm ^-2 or more.
13. The method for manufacturing a semiconductor device according to item 5. 4. The method according to claim 1, wherein the dose of said ion-implanted layer is 1 × 10
^{4. The} method for manufacturing a semiconductor device according to claim 3, wherein the ^{thickness is 14} cm ^-2 or more and less than 1 × 10 ¹⁵ cm ^-2 . 5. The method according to claim 1, wherein the temperature of the semiconductor substrate at the time of the cooling ion implantation is lower than room temperature and higher than liquid nitrogen temperature. 6. A low-temperature annealing temperature of 300 ° C. or more,
6. The temperature is set to 500 ° C. or lower.
The method of manufacturing a semiconductor device according to any one of. 7. The method for manufacturing a semiconductor device according to claim 1, wherein said ion-implanted layer is formed by implanting boron or BF ₂ with cooling ions.