JPH05275501A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH05275501A
JPH05275501A JP4070998A JP7099892A JPH05275501A JP H05275501 A JPH05275501 A JP H05275501A JP 4070998 A JP4070998 A JP 4070998A JP 7099892 A JP7099892 A JP 7099892A JP H05275501 A JPH05275501 A JP H05275501A
Authority
JP
Japan
Prior art keywords
silicon
aluminum
electrode
wire
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4070998A
Other languages
Japanese (ja)
Inventor
Takafumi Tsuchiya
尚文 土屋
Akira Nakamura
明 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4070998A priority Critical patent/JPH05275501A/en
Publication of JPH05275501A publication Critical patent/JPH05275501A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the stripping off of a bonding wire by constituting a bonding pad in a two-layer structure. CONSTITUTION:After forming an aluminum-silicon electrode layer 17 on a semiconductor substrate 12, a pure aluminum electrode layer 19 is formed on the layer 17 as a bonding pad. Then bonding wires 21 are bonded to the surface of the layer 19 by the ultrasonic wire bonding method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はワイヤボンド剥がれを防
止できるボンディングパッド構造を有する半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bonding pad structure capable of preventing wire bond peeling.

【０００２】[0002]

【従来の技術】半導体チップをモ−ルドした半導体装置
においては、チップを外部接続するために、チップ上に
形成した電極パッドと外部接続リードとをボンディング
ワイヤで接続している。前記電極パッドの構造を第５図
に示す。同図において、（１）は半導体基板、（２）は
基板（１）表面を被覆する絶縁膜、（３）は絶縁膜
（２）上に形成した外部接続用の電極パッド、（４）は
電極パッド（３）に接続したボンディングワイヤである
（例えば、特開昭６３−１０８７３５号）。2. Description of the Related Art In a semiconductor device in which a semiconductor chip is molded, in order to externally connect the chip, an electrode pad formed on the chip and an external connection lead are connected by a bonding wire. The structure of the electrode pad is shown in FIG. In the figure, (1) is a semiconductor substrate, (2) is an insulating film covering the surface of the substrate (1), (3) is an electrode pad for external connection formed on the insulating film (2), and (4) is This is a bonding wire connected to the electrode pad (3) (for example, JP-A-63-108735).

【０００３】ところで、半導体素子の電極材料として
は、素子の微細化によって接合深さが浅くなると共に純
粋なアルミニウムよりシリコンを数重量％含有するアル
ミニウム−シリコンが多用されている。アルミニウム−
シルコンは、純粋なアルミニウムよりスパイクの発生が
少ないので、素子のＰＮ接合を貫通しないで済むという
特徴を持つ。従って、素子の電極形成と同時的に形成す
る電極パッド（３）の材料にもアルミニウム−シリコン
が多用されている。By the way, as an electrode material for semiconductor elements, aluminum-silicon, which has a shallower junction depth due to element miniaturization and contains several wt% of silicon than pure aluminum, is often used. Aluminum −
Since silicon has fewer spikes than pure aluminum, it does not have to penetrate the PN junction of the device. Therefore, aluminum-silicon is often used as a material for the electrode pads (3) formed at the same time when the electrodes of the device are formed.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、電極材
料としてのアルミニウム−シリコンは、材料を蒸着した
後に各種熱処理を加えると、材料中に含まれるシリコン
が析出して硬い粒状のシリコンノジュール（５）を形成
するという欠点がある。その直径は１μ程にも成長する
ことがあり、このようなシリコンノジュール（５）が形
成されると、組立工程のワイヤボンド工程において超音
波振動圧力により半導体基板（１）に局部的な圧力を加
え、場合によっては基板（１）に亀裂（６）を発生させ
ることがある。このような亀裂（６）が発生すると、特
にＳＯＰ、ＱＦＰ、ＰＬＣＣなどの耐湿性に劣る半導体
装置において、モ−ルド工程後にボンディングワイヤ
（４）が電極パッド（３）材料や基板（１）素材を付着
させたまま亀裂（６）から剥がれるという、所謂エグレ
不良が多発する欠点があった。However, when aluminum-silicon as an electrode material is subjected to various heat treatments after vapor deposition of the material, silicon contained in the material precipitates to form hard granular silicon nodules (5). It has the drawback of forming. The diameter of the silicon nodule may grow up to about 1 μ, and when such a silicon nodule (5) is formed, a local pressure is applied to the semiconductor substrate (1) by ultrasonic vibration pressure in the wire bonding process of the assembly process. In addition, cracks (6) may be generated in the substrate (1) in some cases. When such a crack (6) occurs, the bonding wire (4) is used as a material for the electrode pad (3) or the substrate (1) after the molding process, especially in a semiconductor device having poor moisture resistance such as SOP, QFP and PLCC. There was a drawback that so-called Egure defects frequently occurred, that is, peeling from the cracks (6) while adhering to.

【０００５】[0005]

【課題を解決するための手段】本発明は上記従来の欠点
に鑑み成されたもので、電極パッドをシリコンを含むア
ルミニウム層とシリコンを含まないアルミニウム層との
積層構造とし、前記シリコンを含まないアルミニウム層
の表面にワイヤボンドすることによって従来の不良発生
を防止した半導体装置を提供するものである。The present invention has been made in view of the above-mentioned drawbacks of the prior art. The electrode pad has a laminated structure of an aluminum layer containing silicon and an aluminum layer not containing silicon, and does not contain the silicon. It is intended to provide a conventional semiconductor device in which the occurrence of defects is prevented by wire bonding to the surface of an aluminum layer.

【０００６】[0006]

【作用】シリコンを含むアルミニウム層に比べ、シリコ
ンを含まないアルミニウム層はシリコンノジュールが発
生せず、しかも硬さが柔らかい。そのため、ワイヤボン
ド工程の超音波振動圧力をシリコンを含まないアルミニ
ウム層の弾力性によって吸収できる。In comparison with the aluminum layer containing silicon, the aluminum layer containing no silicon does not generate silicon nodules and is soft in hardness. Therefore, the ultrasonic vibration pressure in the wire bonding process can be absorbed by the elasticity of the aluminum layer containing no silicon.

【０００７】[0007]

【実施例】以下に本発明の一実施例を、ＰＯＷＥＲ Ｍ
ＯＳ ＦＥＴを例に詳細に説明する。図１はＰＯＷＥＲ
ＭＯＳ ＦＥＴのパッド部分を示す断面図、図２はそ
のチップの平面図である。図１を参照して、裏面にＮ＋
型層（１１）を有する半導体基板（１２）の表面にＰ型
拡散領域（１３）とＮ＋型拡散領域（１４）を形成し、
その上に１０００Å厚のゲート酸化膜を形成し、その上
に０．５〜０．８μ厚のポリシリコンゲート電極（１
５）を形成して単位トランジスタを構成し、この単位ト
ランジスタを多数並列接続することでＰＯＷＥＲ ＭＯ
Ｓ ＦＥＴを構成している。（１６）はゲート電極（１
５）を被覆する１〜２μ厚のＰＳＧ絶縁膜、（１７）は
電極パッド（１８）を形成する３〜４μ厚のシリコンを
数重量％含むアルミニウムーシリコン電極層、（１９）
は同じく３〜４μ厚のシリコンを含まない純粋なアルミ
ニウム電極層、（２０）はパッシベ−ション膜、（２
１）はボンディングワイヤである。EXAMPLE An example of the present invention will be described below with POWER M.
The OS FET will be described in detail as an example. Figure 1 is POWER
FIG. 2 is a cross-sectional view showing the pad portion of the MOS FET, and FIG. 2 is a plan view of the chip. Referring to FIG. 1, the back surface is N +
Forming a P type diffusion region (13) and an N + type diffusion region (14) on the surface of the semiconductor substrate (12) having the type layer (11),
A 1000 Å thick gate oxide film is formed on top of this, and a 0.5 to 0.8 μ thick polysilicon gate electrode (1
5) is formed to form a unit transistor, and a large number of the unit transistors are connected in parallel to make a POWER MO
It constitutes an S FET. (16) is the gate electrode (1
5) a PSG insulating film having a thickness of 1-2 μm, (17) an aluminum-silicon electrode layer containing a few% by weight of silicon having a thickness of 3-4 μm forming an electrode pad (18), (19)
Is a pure aluminum electrode layer having a thickness of 3 to 4 μm and containing no silicon, (20) is a passivation film, and (2)
1) is a bonding wire.

【０００８】単位トランジスタは、チップの外周部を除
きほぼ全面に一様に形成される。ドレインは基板（１
２）を共通ドレインとすることにより共通接続される。
ゲ−トは前記ポリシリコン層をそれ自身またはアルミ電
極（素子電極）で電気接続することにより共通接続され
る。ソースはＰ型拡散領域（１３）とＮ＋型拡散領域
（１４）の両方にオ−ミックコンタクトするアルミ電極
によって共通接続される。ドレインの外部接続は基板
（１２）の裏面側に設けたドレイン電極によって成され
る。ゲートとソースの外部接続は基板（１２）の表面に
図２に示したように形成した電極パッド（１８）によっ
て成される。The unit transistors are uniformly formed on almost the entire surface of the chip except the outer peripheral portion. The drain is the substrate (1
By using 2) as a common drain, they are commonly connected.
The gates are commonly connected by electrically connecting the polysilicon layer with itself or with an aluminum electrode (element electrode). The sources are commonly connected to both the P type diffusion region (13) and the N + type diffusion region (14) by an aluminum electrode which makes ohmic contact. The external connection of the drain is made by the drain electrode provided on the back surface side of the substrate (12). The external connection between the gate and the source is made by the electrode pad (18) formed on the surface of the substrate (12) as shown in FIG.

【０００９】ソースの電極パッド（１８）は、図１から
明らかなように前記ソ−スを共通接続するアルミ電極の
一部であり、単位トランジスタを形成した領域上のパッ
シベ−ション膜（２０）を除去することによって形成さ
れている。電極パッド（１８）を形成する領域以外の領
域も、同じ構造で延在して単位トランジスタを並列接続
する。ゲートの電極パッド（１８）は、ソースの電極パ
ッド（１８）とは分離されてＰＳＧ絶縁膜（１６）の上
を延在し、スルーホールを介してその下のゲートポリシ
リコンに接続されている。As is apparent from FIG. 1, the source electrode pad (18) is a part of the aluminum electrode commonly connected to the source, and the passivation film (20) on the region where the unit transistor is formed. Are formed by removing. The region other than the region where the electrode pad (18) is formed also extends in the same structure to connect the unit transistors in parallel. The gate electrode pad (18) is separated from the source electrode pad (18), extends over the PSG insulating film (16), and is connected to the gate polysilicon thereunder through the through hole. ..

【００１０】前記アルミ電極は、アルミニウムーシリコ
ン電極層（１７）と純粋なアルミニウム電極層（１９）
との積層構造からなり、下に拡散領域とオーミックコン
タクトするアルミニウムーシリコン電極層（１７）、上
にボンディングワイヤ（２１）がワイヤボンドされる純
粋なアルミニウム電極層（１９）が形成される。両者
は、ともに蒸着またはスパッタにより順次形成される。
ボンディングワイヤ（２１）は、直径が数十μの金製ま
たはアルミ製の金属細線であり、それぞれ超音波併用熱
圧着法または超音波法によってワイヤボンドされる。ア
ルミニウムーシリコン電極層（１７）には、蒸着後の各
種熱処理（アニ−ル等）によって従来と同様にシリコン
ノジュールが析出されていると考えられる。The aluminum electrode comprises an aluminum-silicon electrode layer (17) and a pure aluminum electrode layer (19).
And a pure aluminum electrode layer (19) on which a bonding wire (21) is wire-bonded is formed. Both are sequentially formed by vapor deposition or sputtering.
The bonding wire (21) is a metal thin wire made of gold or aluminum having a diameter of several tens of μm, and is wire-bonded by a thermocompression bonding method using ultrasonic waves or an ultrasonic wave method, respectively. It is considered that silicon nodules are deposited on the aluminum-silicon electrode layer (17) by various heat treatments (annealing or the like) after vapor deposition as in the conventional case.

【００１１】単位トランジスタを形成した基板（１２）
は、図示せぬリードフレームのダイ部に前記ドレイン電
極を接着する。ボンディングワイヤ（２１）は、リード
フレームの外部接続リードに他端が接続される。そし
て、周囲を樹脂モールドして半導体装置が製造される。
以上に説明した本発明の構造によれば、アルミニウムー
シリコン電極層（１７）の上を硬さが柔らかい純粋なア
ルミニウム電極層（１９）で被覆するので、超音波ボン
ディング工程において、その圧力が純粋なアルミニウム
電極層（１９）で吸収される。そのため、アルミニウム
ーシリコン電極層（１７）内に析出したシリコンノジュ
−ルに前記圧力が直接伝わらず、基板（１２）への圧力
も弱まるので、基板（１２）への亀裂発生を防止でき
る。よって、組立工程終了後にボンディングワイヤが剥
がれる不良発生を防止できる。Substrate (12) on which unit transistors are formed
Adheres the drain electrode to a die portion of a lead frame (not shown). The other end of the bonding wire (21) is connected to the external connection lead of the lead frame. Then, the periphery is resin-molded to manufacture a semiconductor device.
According to the structure of the present invention described above, the aluminum-silicon electrode layer (17) is covered with the pure aluminum electrode layer (19) having a soft hardness, so that the pressure in the ultrasonic bonding process is pure. It is absorbed by the transparent aluminum electrode layer (19). Therefore, the pressure is not directly transmitted to the silicon nodules deposited in the aluminum-silicon electrode layer (17) and the pressure on the substrate (12) is weakened, so that the generation of cracks on the substrate (12) can be prevented. Therefore, it is possible to prevent the occurrence of defects in which the bonding wire is peeled off after the assembly process is completed.

【００１２】尚、純粋なアルミニウム電極層（１９）は
電極パッド（１８）部分に選択的に設けてもよく、図１
のように素子電極全てを同じ積層構造としてもよい。後
者はホトレジスト工程が１回少なくて済み、マスク数を
低減できるメリットがある。また、純粋なアルミニウム
電極層（１９）の膜厚は、前記ボンディング時の圧力を
吸収できる厚みがあれば足り、概ねアルミニウムーシリ
コン電極層（１７）と同程度の厚みがあれば良い。The pure aluminum electrode layer (19) may be selectively provided on the electrode pad (18), as shown in FIG.
As described above, all the device electrodes may have the same laminated structure. The latter has the advantage that the number of masks can be reduced because the number of photoresist steps can be reduced once. Further, the pure aluminum electrode layer (19) need only have a thickness capable of absorbing the pressure during the bonding, and may have a thickness substantially the same as that of the aluminum-silicon electrode layer (17).

【００１３】図３と図４は小信号トランジスタの例であ
る。素子電極が絶縁膜（２２）上に引き出され、基板
（１２）の周辺部に電極パッド（１８）が形成されてい
る。絶縁膜（２２）として硬いシリコン熱酸化膜が使わ
れることが多いので、このように電極パッド（１８）が
引き出された半導体装置においても、本願はワイヤはが
れを防止できる効果を有する。3 and 4 show examples of small signal transistors. The device electrode is drawn out on the insulating film (22), and the electrode pad (18) is formed on the peripheral portion of the substrate (12). Since a hard silicon thermal oxide film is often used as the insulating film (22), the present invention has an effect of preventing wire peeling even in a semiconductor device in which the electrode pad (18) is drawn out.

【００１４】[0014]

【発明の効果】以上、ディスクリ−ト半導体素子を例に
説明した本発明の構成によれば、電極パッド（１８）を
純粋なアルミニウム電極層（１９）で被覆することによ
り、ボンディング時の圧力を吸収し、基板（１２）への
ダメージを軽減してボンディングワイヤ（２１）の剥が
れ不良を防止できる利点を有する。As described above, according to the structure of the present invention described by taking the discrete semiconductor device as an example, by covering the electrode pad (18) with the pure aluminum electrode layer (19), the pressure during bonding is increased. Has the advantage that it is possible to reduce the damage to the substrate (12) and prevent the peeling failure of the bonding wire (21).

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例を説明するための断面図
である。FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

【図２】本発明の第１の実施例を説明するための平面図
である。FIG. 2 is a plan view for explaining the first embodiment of the present invention.

【図３】本発明の第２の実施例を説明するための断面図
である。FIG. 3 is a sectional view for explaining a second embodiment of the present invention.

【図４】本発明の第２の実施例を説明するための平面図
である。FIG. 4 is a plan view for explaining a second embodiment of the present invention.

【図５】従来例を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】半導体チップの表面に形成した電極パッド
と外部の接続リードとを金属細線でワイヤボンドし、主
要部をパッケージングした半導体装置において、 前記電極パッドが、シリコンを含むアルミニウム層とシ
リコンを含まないアルミニウム層との積層構造であり、
超音波振動を伴った方法によって前記シリコンを含まな
いアルミニウム層の表面に前記金属細線がワイヤボンド
されていることを特徴とする半導体装置。1. A semiconductor device in which an electrode pad formed on the surface of a semiconductor chip and an external connection lead are wire-bonded with a fine metal wire and a main part is packaged, wherein the electrode pad includes an aluminum layer containing silicon and silicon. It is a laminated structure with an aluminum layer that does not include
A semiconductor device, wherein the thin metal wire is wire-bonded to the surface of the aluminum layer not containing silicon by a method involving ultrasonic vibration. 【請求項２】前記半導体チップ上の素子電極と前記電極
パッドとが同じく前記積層構造を有することを特徴とす
る請求項第１項に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the element electrode and the electrode pad on the semiconductor chip have the same laminated structure.
JP4070998A 1992-03-27 1992-03-27 Semiconductor device Pending JPH05275501A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4070998A JPH05275501A (en) 1992-03-27 1992-03-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4070998A JPH05275501A (en) 1992-03-27 1992-03-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05275501A true JPH05275501A (en) 1993-10-22

Family

ID=13447743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4070998A Pending JPH05275501A (en) 1992-03-27 1992-03-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05275501A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299346A (en) * 2001-04-02 2002-10-11 Fuji Electric Co Ltd Method of manufacturing semiconductor device
JP2003007976A (en) * 2001-06-25 2003-01-10 Mitsubishi Electric Corp Semiconductor device and module device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299346A (en) * 2001-04-02 2002-10-11 Fuji Electric Co Ltd Method of manufacturing semiconductor device
JP2003007976A (en) * 2001-06-25 2003-01-10 Mitsubishi Electric Corp Semiconductor device and module device

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