JPH09330992A - Semiconductor device mounting body and its manufacture - Google Patents
Semiconductor device mounting body and its manufactureInfo
- Publication number
- JPH09330992A JPH09330992A JP8171750A JP17175096A JPH09330992A JP H09330992 A JPH09330992 A JP H09330992A JP 8171750 A JP8171750 A JP 8171750A JP 17175096 A JP17175096 A JP 17175096A JP H09330992 A JPH09330992 A JP H09330992A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- ball
- gold ball
- gold
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置チップの
パッケージング技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packaging technology for semiconductor device chips.
【０００２】[0002]
【従来の技術】半導体装置（以下、ＩＣという）のパッ
ケージング技術の１つに樹脂封止法があるが、樹脂封止
法ではＩＣチップをリ−ドフレ−ムにダイボンディング
し、チップの電極とリ−ドフレ−ムとの間をワイヤ−に
よるボンディング接続を行なった後、チップとワイヤ−
を樹脂により封止している。そのため、チップが小型化
したり、ワイヤ−の本数が多くなってくると、ワイヤ−
どおしが接触するワイヤ−干渉の問題や、ワイヤ−ル−
プ分だけパッケージの厚みが厚くなって薄型化が困難に
なるという問題が生じる。2. Description of the Related Art A resin encapsulation method is one of the packaging techniques for semiconductor devices (hereinafter referred to as ICs). In the resin encapsulation method, an IC chip is die-bonded to a lead frame to form a chip electrode. After connecting the wire and the lead frame with a wire, the chip and the wire are connected.
Is sealed with resin. Therefore, if the chip becomes smaller and the number of wires increases,
Wires contacting each other-problems of interference, wire-
As a result, the package becomes thicker by an amount corresponding to the number of parts, making it difficult to reduce the thickness.
【０００３】[0003]
【発明が解決しようとする課題】本発明はワイヤ−ル−
プを存在させないことによってパッケージの薄型化及び
小型化を図ることを目的とするものである。SUMMARY OF THE INVENTION The present invention is a wire reel.
The purpose of the present invention is to reduce the thickness and size of the package by eliminating the package.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体装置実装
体では、ＩＣチップの電極部に金ボ−ルが接合してお
り、そのＩＣチップ及び金ボ−ルの周囲が樹脂封止さ
れ、金ボ−ルの表面の一部が封止樹脂表面に露出してい
る。金ボ−ルは一重のものでもよいが、チップ側に小さ
いボ−ルが形成され、その上に重ねて大きいボ−ルが形
成された二重構造になっているものの場合には、実装電
極部の端子面を広くすることができて好都合である。In the semiconductor device mounting body of the present invention, a gold ball is joined to the electrode portion of the IC chip, and the periphery of the IC chip and the gold ball is resin-sealed, Part of the surface of the gold ball is exposed on the surface of the sealing resin. The gold ball may be a single layer, but in the case of a double structure in which a small ball is formed on the chip side and a large ball is formed on top of it, the mounting electrode This is convenient because the terminal surface of the part can be widened.
【０００５】本発明の製造方法は、以下の工程（Ａ）か
ら（Ｅ）を含んでいる。 （Ａ）半導体素子が形成されたウエハの裏面側を支持板
に接着する工程、（Ｂ）支持板に接着されたウエハをチ
ップごとに分離し、かつ支持板の厚みの一部の深さまで
切り込みを入れるダイシング工程、（Ｃ）ダイシング工
程の前又は後で、ウエハの電極部にワイヤ−ボンディン
グ法により金ボ−ルを形成する工程、（Ｄ）工程（Ｂ）
及び（Ｃ）に後、トランスファモールド法により、金ボ
−ルの表面の一部が露出するように、チップ及び金ボ−
ルの周囲を封止する樹脂封止工程、（Ｅ）その後、支持
板をチップごとに切り離す工程。The manufacturing method of the present invention includes the following steps (A) to (E). (A) A step of adhering the back surface side of the wafer on which the semiconductor element is formed to a supporting plate, (B) separating the wafer adhered to the supporting plate into chips, and cutting to a part of the thickness of the supporting plate And (C) a step of forming a gold ball on the electrode portion of the wafer by a wire bonding method, (D) step (B)
After the steps (C) and (C), the chip and the gold ball are exposed by a transfer molding method so that a part of the surface of the gold ball is exposed.
Resin encapsulation step of encapsulating the periphery of the chip, (E) then, the step of separating the support plate into chips.
【０００６】支持板をチップごとに切り離した後、金ボ
−ルが形成されている側の表面を研磨する工程をさらに
含んでいてもよい。この場合も実装電極部の端子面を広
くすることができて好都合である。The method may further include a step of polishing the surface on the side where the gold balls are formed after separating the support plate into chips. Also in this case, the terminal surface of the mounting electrode portion can be widened, which is convenient.
【０００７】ウエハに金ボ−ルを形成する方法として
は、通常用いられているワイヤ−ボンダーやボ−ルボン
ダーに条件を設定することによりボ−ルを形成すること
ができる。また、ワイヤ−ボンダ−により金ボ−ルを形
成した後、キャピラリ−を動作させて金ボ−ルとワイヤ
−との境界部分に応力集中等を生じさせて切り離すこと
によっても金ボ−ルを形成することができる（特開昭６
２−２１１９３７号公報参照）。As a method of forming a gold ball on a wafer, the ball can be formed by setting conditions on a wire bonder or a ball bonder which is usually used. Further, after the gold ball is formed by the wire bonder, the capillary is operated to cause stress concentration or the like at the boundary portion between the gold ball and the wire to separate the gold ball, thereby separating the gold ball. Can be formed (Japanese Patent Application Laid-Open No. Sho 6
(See Japanese Patent Laid-Open No. 2-111937).
【０００８】[0008]
【実施例】図１は一実施例のパッケージを表わす。半導
体素子が形成されたＩＣチップ２がその裏面側で銀ペ−
スト接着剤４により支持板のガラス板６に接着されてい
る。ＩＣチップ２の表面側の電極部２ａには金ボ−ル８
が接合されている。ＩＣチップ２及び金ボ−ル８の周囲
は封止用樹脂１０により封止されており、金ボ−ル８の
表面の一部が樹脂１０の表面から露出している。金ボ−
ル８の露出した表面がこのパッケージを実装する基板の
電極と半田付け接合される実装電極部の端子面となる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 represents a package of one embodiment. The IC chip 2 on which the semiconductor element is formed has a silver paste on the back side.
It is adhered to the glass plate 6 of the support plate by the strike adhesive 4. A gold ball 8 is provided on the electrode portion 2a on the front surface side of the IC chip 2.
Are joined. The periphery of the IC chip 2 and the gold ball 8 is sealed with a sealing resin 10, and a part of the surface of the gold ball 8 is exposed from the surface of the resin 10. Money box
The exposed surface of the module 8 serves as a terminal surface of a mounting electrode portion which is soldered and bonded to an electrode of a substrate on which this package is mounted.
【０００９】次に、この実施例を製造する方法について
図２を参照して説明する。 （Ａ）半導体素子が形成されたシリコンウエハ２０をそ
の裏面側で銀ペ−スト接着剤により絶縁性のシ−ト又は
ガラス板などの支持板２２に貼り付け、支持板２２を介
してウエハリング２４に固定する。この状態でワイヤ−
ボンディング法によりウエハ２０の電極部に金ボ−ルを
形成する。金ボ−ルの形成方法として、従来のボ−ルボ
ンダーを用い、その一次側及び二次側を同一とし、ワイ
ヤ−ル−プ高さを０設定とし、パワ−及びタイムを一次
側のみ設定し、二次側を０にするか又は一次側より小さ
くしてボンディングすることにより、ル−プのない金ボ
−ルを形成することができる。用いるワイヤ−は、細線
用ワイヤ−ボンダ−の場合は直径が２０〜４０μｍ、太
線用ボ−ルボンダ−の場合は直径４０〜１２７μｍであ
る。Next, a method for manufacturing this embodiment will be described with reference to FIG. (A) A silicon wafer 20 on which a semiconductor element is formed is attached on the back surface side thereof to a supporting plate 22 such as an insulating sheet or a glass plate with a silver paste adhesive, and the wafer ring is attached via the supporting plate 22. Fix at 24. In this state, the wire
Gold balls are formed on the electrode portions of the wafer 20 by the bonding method. As a method of forming the gold ball, a conventional ball bonder is used, the primary side and the secondary side thereof are the same, the wire loop height is set to 0, and the power and time are set only on the primary side. , The secondary side is set to 0 or smaller than the primary side to perform bonding, whereby a gold ball without a loop can be formed. The wire used has a diameter of 20 to 40 μm in the case of a thin wire bonder, and has a diameter of 40 to 127 μm in the case of a thick wire ball bonder.
【００１０】（Ｂ）金ボ−ル８を形成した後、ウエハ２
０をＩＣチップに分離するダイシングを行なう。ダイシ
ングではウエハ２０をチップごとに完全に切り離し、支
持板２２はその厚みの一部まで切り込む。 （Ｃ）ウエハ２０をトランスファ−モ−ルド法の型２６
に入れ、樹脂１０を注入することにより封止する。(B) After forming the gold ball 8, the wafer 2
Dicing is performed to separate 0 into an IC chip. In dicing, the wafer 20 is completely separated into chips, and the support plate 22 is cut to a part of its thickness. (C) The wafer 20 is transferred to the mold 26 of the transfer mold method.
Then, the resin 10 is injected and sealed.
【００１１】（Ｄ）支持板２２を切断し、ＩＣチップご
とに分離する。その後、切断面を研磨し、さらに金ボ−
ル８が形成されている樹脂面も研磨して金ボ−ル８の一
部も研磨する。それにより、金ボ−ル８の露出面が大き
くなる。樹脂封止された状態で金ボ−ル８が樹脂１０の
表面に露出するようにしてもよく、十分に露出していな
くても、研磨することにより金ボ−ル８の表面を十分に
露出させることができる。図２の製造工程において、金
ボ−ルを形成する工程とダイシング工程とを逆にしても
よい。(D) The support plate 22 is cut and separated into IC chips. After that, the cut surface is polished, and gold
The resin surface on which the ball 8 is formed is also polished to partially polish the gold ball 8. As a result, the exposed surface of the gold ball 8 becomes large. The gold ball 8 may be exposed on the surface of the resin 10 in a resin-sealed state. Even if the gold ball 8 is not sufficiently exposed, the surface of the gold ball 8 is sufficiently exposed by polishing. Can be made. In the manufacturing process of FIG. 2, the process of forming the gold ball and the dicing process may be reversed.
【００１２】金ボ−ル８の大きさは用いるワイヤ−の直
径によって異なる。金ボ−ル８が接合されるウエハ２０
の電極部の圧着面積は、一般には金ワイヤ−の場合はワ
イヤ−の直径の３倍の圧着面積が必要である。例えば直
径μｍの金ワイヤ−であればＩＣチップ側の電極パッド
として９０μｍ×９０μｍ程度の大きさが必要となる。
そこで、ＩＣチップの電極パッドを大きくしないで、パ
ッケージングされた後の金ボ−ルの露出面（実装電極
面）を大きくするために、図３に示されるように、初め
に細い金ワイヤ−を用いて下層の金ボ−ル８ａを形成
し、その上に太い金ワイヤ−を用いて上層の金ボ−ル８
ｂを形成してボ−ルを二重にすることにより、実装電極
部の端子面を広くすることができる。支持板としてはガ
ラス板を例示しているが、その他の絶縁性基板であって
もよく、ポリイミドシ−トなどの絶縁性シ−トであって
もよい。The size of the gold ball 8 depends on the diameter of the wire used. Wafer 20 to which gold ball 8 is bonded
In general, in the case of a gold wire, the crimping area of the electrode portion is required to be three times as large as the diameter of the wire. For example, in the case of a gold wire having a diameter of μm, a size of about 90 μm × 90 μm is required as an electrode pad on the IC chip side.
Therefore, in order to increase the exposed surface (mounting electrode surface) of the gold ball after packaging without increasing the electrode pad of the IC chip, as shown in FIG. To form a lower layer gold ball 8a, and a thicker gold wire thereon to form an upper layer gold ball 8a.
By forming b and forming a double ball, it is possible to widen the terminal surface of the mounting electrode portion. Although a glass plate is shown as an example of the support plate, it may be another insulating substrate or an insulating sheet such as a polyimide sheet.
【００１３】[0013]
【発明の効果】本発明のパッケージでは、ＩＣチップの
電極部に金ボ−ルを接合させ、そのＩＣチップ及び金ボ
−ルの周囲を樹脂封止し、金ボ−ルの表面の一部を封止
樹脂表面に露出させているので、パッケージの厚さがチ
ップの厚さとボ−ルの高さにより決まり、ワイヤ−ボン
ディング法のようなワイヤ−ル−プの高さが不要になる
ので、薄型化パッケ−ジが可能になる。また、リ−ドフ
レ−ムを用いないため、電気抵抗も小さくなリ、小型に
もなる。金ボ−ルの側部及びＩＣチップを樹脂封止して
いるので、信頼性が高い。このパッケージを基板に実装
するときは、基板の電極パタ−ンとＩＣチップの電極パ
タ−ンを同じサイズにすることができるため、基板のパ
タ−ンピッチを小さくすることが可能になり、高密度実
装ができるようになる。金ボ−ルは一重のものでもよい
が、チップ側に小さいボ−ルを形成し、その上に重ねて
大きいボ−ルを形成した二重構造とすれば、実装電極部
の端子面を広くすることができて好都合である。In the package of the present invention, the gold ball is bonded to the electrode portion of the IC chip, and the IC chip and the periphery of the gold ball are resin-sealed to form a part of the surface of the gold ball. Since the package is exposed on the surface of the encapsulating resin, the thickness of the package is determined by the chip thickness and the ball height, which eliminates the wire loop height required in the wire bonding method. Therefore, a thinner package is possible. Further, since the lead frame is not used, the electric resistance can be reduced and the size can be reduced. Since the side portion of the gold ball and the IC chip are resin-sealed, the reliability is high. When this package is mounted on a substrate, the electrode pattern of the substrate and the electrode pattern of the IC chip can be made the same size, so that the pattern pitch of the substrate can be made small and high density can be achieved. Can be implemented. The gold ball may be a single layer, but if a small ball is formed on the chip side and a large ball is formed on top of it, the terminal surface of the mounting electrode part will be wide. It is convenient to be able to do it.
【図１】一実施例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment.
【図２】製造方法の一例を示す平面図及び断面図であ
る。FIG. 2 is a plan view and a cross-sectional view showing an example of a manufacturing method.
【図３】他の実施例における金ボ−ルを概略的に示す側
面図である。FIG. 3 is a side view schematically showing a gold ball according to another embodiment.
２ ＩＣチップ ２ａ，２ｂ ＩＣチップの電極部 ４ 銀ペ−スト接着剤 ６ 支持板 ８，８ａ，８ｂ 金ボ−ル １０ 封止用樹脂 2 IC chip 2a, 2b Electrode part of IC chip 4 Silver paste adhesive 6 Support plate 8, 8a, 8b Gold ball 10 Sealing resin
Claims (4)
接合しており、その半導体装置チップ及び金ボ−ルの周
囲が樹脂封止され、金ボ−ルの表面の一部が封止樹脂表
面に露出していることを特徴とする半導体装置実装体。1. A gold ball is joined to an electrode portion of a semiconductor device chip, the semiconductor device chip and the periphery of the gold ball are resin-sealed, and a part of the surface of the gold ball is sealed. A semiconductor device package, which is exposed on the surface of the resin.
形成され、その上に重ねて大きいボ−ルが形成された二
重構造になっている請求項１に記載の半導体装置実装
体。2. The semiconductor device according to claim 1, wherein the gold ball has a double structure in which a small ball is formed on the chip side and a large ball is formed on the small ball. Implementation body.
体装置実装体の製造方法。 （Ａ）半導体素子が形成されたウエハの裏面側を支持板
に接着する工程、 （Ｂ）支持板に接着されたウエハをチップごとに分離
し、かつ支持板の厚みの一部の深さまで切り込みを入れ
るダイシング工程、 （Ｃ）ダイシング工程の前又は後で、ウエハの電極部に
ワイヤ−ボンディング法により金ボ−ルを形成する工
程、 （Ｄ）工程（Ｂ）及び（Ｃ）に後、トランスファモール
ド法により、金ボ−ルの表面の一部が露出するように、
チップ及び金ボ−ルの周囲を封止する樹脂封止工程、 （Ｅ）その後、支持板をチップごとに切り離す工程。3. A method for manufacturing a semiconductor device package, which includes the following steps (A) to (E). (A) A step of adhering the back surface side of a wafer on which a semiconductor element is formed to a support plate, (B) The wafer adhered to the support plate is separated into chips, and cut to a depth of a part of the thickness of the support plate And (C) a step of forming a gold ball on the electrode portion of the wafer by a wire bonding method before or after the dicing step, (D) after steps (B) and (C), and then a transfer step. By the molding method, so that a part of the surface of the gold ball is exposed,
A resin sealing step of sealing the periphery of the chip and the gold ball, (E) Then, a step of separating the support plate for each chip.
ボ−ルが形成されている側の表面を研磨する工程をさら
に含んでいる請求項３に記載の半導体装置実装体の製造
方法。4. The method of manufacturing a semiconductor device package according to claim 3, further comprising the step of polishing the surface on the side where the gold balls are formed after separating the support plate into chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8171750A JPH09330992A (en) | 1996-06-10 | 1996-06-10 | Semiconductor device mounting body and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8171750A JPH09330992A (en) | 1996-06-10 | 1996-06-10 | Semiconductor device mounting body and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09330992A true JPH09330992A (en) | 1997-12-22 |
Family
ID=15929007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8171750A Pending JPH09330992A (en) | 1996-06-10 | 1996-06-10 | Semiconductor device mounting body and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09330992A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000101162A (en) * | 1998-09-25 | 2000-04-07 | Asahi Kasei Denshi Kk | Small-sized magnetoelectric transducer and manufacture thereof |
| JP2004512684A (en) * | 2000-10-17 | 2004-04-22 | スリーエム イノベイティブ プロパティズ カンパニー | Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding |
| CN100378977C (en) * | 2000-11-14 | 2008-04-02 | 联测科技股份有限公司 | Semiconductor device without chip carrier and its preparing process |
| JP2009100005A (en) * | 2003-08-06 | 2009-05-07 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| US7723839B2 (en) | 2005-06-10 | 2010-05-25 | Sharp Kabushiki Kaisha | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device |
-
1996
- 1996-06-10 JP JP8171750A patent/JPH09330992A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000101162A (en) * | 1998-09-25 | 2000-04-07 | Asahi Kasei Denshi Kk | Small-sized magnetoelectric transducer and manufacture thereof |
| JP2004512684A (en) * | 2000-10-17 | 2004-04-22 | スリーエム イノベイティブ プロパティズ カンパニー | Solvent burnishing of pre-underfilled solder bump wafers for flip chip bonding |
| CN100378977C (en) * | 2000-11-14 | 2008-04-02 | 联测科技股份有限公司 | Semiconductor device without chip carrier and its preparing process |
| JP2009100005A (en) * | 2003-08-06 | 2009-05-07 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device |
| US7723839B2 (en) | 2005-06-10 | 2010-05-25 | Sharp Kabushiki Kaisha | Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device |
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