JP2000021906A - Manufacture of semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture the semiconductor chip having the small outer dimensions through a simplified manufacturing process. SOLUTION: A gap 5 is formed between the neighboring semiconductor chips, by performing the first cutting along a scribe line SL for a wafer W stuck to a sheet S. Then, these semiconductor chips are assembled and set in a metal mold for each sheet S. Molding resin is injected, and the forming surface of a bump 4 is covered flatly with molding resin 6. At the same time, the gap 5 is filed. Then, with the mold resin layer 6 filled in the gap 5 as a mark, a second cutting using a dicing wheel DW is performed. The wafer W is again divided into individual semiconductor chips C1. The bump 4 can be used for facedown mounting intactly on the mounting substrate. No assembling whatever using a lead frame and packaging is required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method capable of greatly simplifying a manufacturing process and manufacturing a semiconductor chip having a small external size.

[0002]

2. Description of the Related Art In order to develop smaller, thinner, and lighter portable electronic devices such as digital video cameras, digital mobile phones, and notebook personal computers, the surface mounting density of electronic components inside the devices must be increased. The key point is how to improve Regarding the mounting of a semiconductor chip, one of these electronic components, an SOP (Small Outline Package) whose external dimensions are close to the dimensions of the chip body by devising the internal structure of the package
Have been proposed.

As an example of such an SOP, an example of a manufacturing process of a lead-on-chip (LOC) type semiconductor package will be described with reference to FIGS. FIG.
Pastes a wafer w on which all integrated circuit processes have been completed onto a sheet s made of synthetic resin, and cuts the wafer w into individual semiconductor chips c along a scribe line sl using a dicing wheel dw. It shows the state where it is. FIG. 7A is a schematic perspective view of the entire wafer,
FIG. 7B is a schematic cross-sectional view in which the main part is enlarged.
However, FIG. 7B does not directly reflect the scale of FIG. 7A for convenience of illustration. This is the same for the subsequent drawings.

In each semiconductor chip c, electrode pads 12 are arranged on an upper surface of a substrate 11 on which an IC has been formed in advance.
This upper surface is covered with a protective insulating film 13 for selectively exposing the electrode pad 12, and a pump 14 is attached to an exposed portion of the electrode pad 12. A gap 15 is formed in the wafer w as an allowance for the dicing wheel dw. After all the cutting along the scribe line sl is completed, as shown in FIG. 8, the sheet s is stretched in a two-dimensional plane to separate individual semiconductor chips c, and the semiconductor chips c are separated from the sheet s. I do.

[0005] Thereafter, an assembly process is started. That is, for example, as shown in FIG. 9, the back side of the semiconductor chip c is adhered to the die pad 17 of the lead frame using a paste, and the external leads 16 are connected (bonded) to the bumps 14. Subsequently, the semiconductor chip c is removed using a molding apparatus as shown in FIG.
, And cutting of the lead frame and external leads 16
To complete the semiconductor package. In the example shown in this figure, the external leads 16 are bent in a J-shape inward of the semiconductor package c, and the SOJ (smallout
line J-leaded) Also called a package.

[0006]

However, in the above-described SOJ package manufacturing process, a large number of materials and a large number of steps are used for assembling. That is, as a material, an extra lead frame or molding resin is required. In addition, with the use of the lead frame, various processes such as bonding, cutting of a lead frame unnecessary portion, bending, and the like are additionally generated, and industrial waste accompanying the cutting of the unnecessary portion is also generated. In addition, since external leads are used and the entire semiconductor chip is sealed with a mold resin layer, there is a limit in reducing the external dimensions of a completed package. Therefore, the present invention provides a method of manufacturing a semiconductor chip which reduces the number of steps required for assembly, the type of material required, the amount of material used, industrial waste, and the outer dimensions of a finished product. Aim.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present inventor has repeatedly studied and cut a wafer into individual semiconductor chips and connected external leads as in the prior art. Instead of performing individual resin molding, a continuous molding resin layer is formed in a state where a plurality of semiconductor chips are gathered in one place, and then the idea of cutting and dividing is obtained. In order to maintain the aggregate state of a plurality of semiconductor chips, a support member such as the above-mentioned sheet is used. However, if the wafer is simply covered entirely with mold resin, scribe
Since the position of the line is likely to be unknown, in the present invention, a first cut is made in advance along the scribe line to form a gap between adjacent semiconductor chips before performing the entire coating with the mold resin. Then, the second cutting is performed using the mold resin layer that has entered the gap as a mark.

According to the present invention, it is possible to manufacture a semiconductor chip in which at least the surface on which the external connection terminals are formed is sealed with a mold resin. The external connection terminals of the semiconductor chip can be directly used for connection to a mounting substrate without connecting external leads. Therefore, a lead frame or a mold resin layer surrounding the periphery of the semiconductor chip becomes unnecessary, and the dimensions of the individual semiconductor chips at the time of cutting become the final dimensions of the semiconductor chip.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, after a mold resin layer is collectively formed on the upper surfaces of a plurality of semiconductor chips placed in a collective state, individual semiconductor chips are cut out. A semiconductor chip in which the upper surface to be arranged is resin-molded is obtained. However, depending on the size of the gap between the adjacent semiconductor chips and the cutting margin at the time of cutting, the covering state of the side wall surface can be changed. In other words, when the cutting resin produced by the first cutting is filled with the molding resin as it is and the second cutting is performed with the same cutting margin as that at the time of the first cutting, the molding resin filled in the cutting margin is used. Is removed, and a semiconductor chip having only the upper surface covered with the mold resin is obtained.

On the other hand, when the size of the gap is larger than the cutting allowance at the time of the second cutting, a semiconductor chip is obtained in which not only the upper surface but also the side wall surface is covered with the mold resin.
In this case, the size of the gap is increased in the middle of the process, or the cutting margin at the time of the second cutting is made smaller than the cutting margin at the time of the first cutting, or a combination thereof. Case is conceivable. A practical process is to extend the size of the gap between adjacent semiconductor chips by extending the support member in a two-dimensional plane. According to this method, the mold resin layer can be left on the side wall surface of the semiconductor chip even if the margins for the second cutting and the first cutting are equal.

By the way, the above-mentioned mold resin layer needs to expose at least the upper surface of the external connection terminal formed in advance on the surface of the semiconductor chip. Either the mold resin layer or the external connection terminal may be formed first. When forming the mold resin layer first, it is necessary to open a window at the site where the external connection terminal is to be formed, so that the alignment between the electrode pads on the semiconductor chip and the pattern of the mold resin layer must be accurately performed. There is a need to do. Therefore, it is simpler to form the external connection terminals first as a practical process.

When the external connection terminals are formed first, it is necessary to take measures to prevent the external connection terminals from being finally buried in the mold resin layer. Therefore, in the case where the external connection terminal is once covered to form the mold resin layer, for example, etching is performed so as to reduce the thickness of the mold resin layer under the condition that the selectivity to the external connection terminal can be secured. It is possible to use a photosensitive mold resin to expose the external connection terminals, or to selectively remove only the portions covering the external connection terminals by exposure and development. The present invention proposes a mold using a mold as a simpler method. In this mold, a cavity corresponding to the height of the external connection terminal is formed. An assembly of a plurality of semiconductor chips is set in this cavity as it is, and a resin is injected into the cavity to form the mold. A resin layer is formed. According to this method, the external connection terminals can be exposed in the same plane as the upper surface of the mold resin layer.

The external connection terminal is used as an electrical contact with the mounting substrate as it is in the final product state of the semiconductor chip. A preferred form of such an external connection terminal is a bump. This bump may be obtained by patterning a conductive film formed by a method such as vapor deposition or sputtering, or may be a stud bump formed by using a wire bonder, or further by a transfer bump method. They may be arranged. However, when the mold resin layer is formed using a mold, the upper surface of the external connection terminal is preferably flat, and therefore, the one formed by patterning the conductive film is particularly preferable.

Since the semiconductor chip manufactured according to the present invention is close to a bare chip, the connection path between the chip and the conductor pattern on the mounting board is simplified and the semiconductor chip is not sealed in a package. The distance between the chip and other chips can be shortened as much as the mounting density can be improved. Therefore, it is expected that the speed of signal processing can be increased as well as the size and weight of the electronic device.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described. Example 1 Here, a process in which a mold resin is directly filled into a cutting margin generated by the first cutting and a second cutting is performed with the same cutting margin as in the first cutting, see FIGS. 1 to 4. I will explain while.

FIG. 1 shows a state in which a wafer W having a diameter of 6 inches on which an integrated circuit process has been completed is pasted on a sheet S made of a synthetic resin, and the first time along a scribe line SL using a dicing wheel DW. This shows a state in which the wafer W is divided into individual semiconductor chips C by cutting. FIG. 1A is a schematic perspective view of the entire wafer W, and FIG. 1B is a schematic cross-sectional view in which main parts are enlarged. However, for convenience of illustration, FIG.
It does not directly reflect the scale of (a). This is the same for the subsequent drawings. In each semiconductor chip C, electrode pads 2 are arranged on an upper surface of a substrate 1 in which an IC is formed in advance, and the upper surface is covered with a protective insulating film 3 for selectively exposing the electrode pads 2. A pump 4 having a height of 100 μm is attached to an exposed portion of the pad 2. The size of each semiconductor chip is 10
mm × 10 mm. The wafer W has a width of 60 μm and a depth of 0.4 mm as a cutting allowance of the dicing wheel DW.
Gap 5 was formed.

After all the first cuts along the scribe line SL have been completed, these semiconductor chips C are set together with the sheets S in a mold D as shown in FIG. The mold D has a circular cavity CA that is in flat contact with the upper surface of the bump 4 and has an inner diameter equal to the diameter of the wafer W, and the molding resin is injected into the cavity CA through the gate G. Things. In FIG. 2B, for convenience of illustration, the gate G is horizontally connected to the end of the cavity CA. However, even if the gate G is vertically connected to the center of the circular cavity CA, or a plurality of gates are connected. G may be appropriately arranged so as not to hinder the flow of the resins. As a result, the upper surface of the semiconductor chip C was covered with the mold resin layer 6 having the same height as the upper surface of the bump 4, and the gap 5 was filled with the mold resin layer 6.

Next, the semiconductor chip C was taken out of the mold D together with the sheet S, and as shown in FIG. 3, a second cutting was performed along the scribe line SL. At this time, the mold resin layer 6 filled in the gap 5 serves as a mark of the cutting position. Dicing wheel DW used here
Since the cutting margin is the same as that at the time of the first cutting, the mold resin layer 6 filled in the gap 5 was removed without excess or shortage. By the second cutting, a semiconductor chip C1 in which the bump formation surface was flat and covered with the mold resin layer 6 was obtained. Next, as shown in FIG. 4, the sheet S was stretched in a two-dimensional plane to separate individual semiconductor chips C1, and the semiconductor chips C1 were separated from the sheet S. This semiconductor chip C1
Can be mounted on a mounting substrate with the bumps 4 facing downward.

Example 2 In this example, the cutting allowance generated by the first cutting is temporarily expanded by stretching the sheet, and then filled with a mold resin.
A process of performing the second cutting with the same cutting margin as that at the time of the first cutting will be described with reference to FIGS. The reference numerals used in these figures are partially the same as those in FIGS. 1 to 4 described above.

First, after the first cutting as shown in FIG. 1 described above, the sheet S is stretched in a two-dimensional plane as shown in FIG. 5a was enlarged to 1 mm. Next, a mold resin layer 6a was formed using a mold in the same manner as in Example 1. However, the dimensions of the mold cavity used here were the same as those in Example 1.
Larger than those used in. As a result, the semiconductor chip C
The upper surface of the mold resin layer 6 has the same height as the upper surface of the bump 4.
The gap 5a covered and enlarged by the a is also filled with the mold resin layer 6a.

Next, the semiconductor chip C was taken out of the mold D together with the sheet S, and a second cutting was performed along the center line of the gap 5a as shown in FIG. At this time, the gap 5
The mold resin layer 6a filled in “a” serves as a mark of the cutting position. Since the cutting margin of the dicing wheel DW used here was the same as that at the time of the first cutting, only the central portion of the mold resin layer 6a filled in each gap 5a was removed. By this second cutting, a semiconductor chip C2 was obtained in which the bump formation surface was covered with the mold resin layer 6a flat and the side wall surface was also covered with the mold resin layer 6a. Before the semiconductor chip C2 is separated from the sheet S, the sheet S may be further stretched. The outer dimensions of the semiconductor chip C2 manufactured in the present embodiment are larger than those of the semiconductor chip C1 of the first embodiment because the side wall surface is covered with the mold resin layer 6a, but still larger than those of the conventional SOJ package. Could be downsized.

Although two specific embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, the details such as the shape and external dimensions of each semiconductor chip, the thickness of the material film constituting the semiconductor chip, the structure of the mold, the dimensions of the cavity, the size of the gap between adjacent semiconductor chips, etc. Selection, modification and combination are possible.

[0023]

As is apparent from the above description, according to the method of manufacturing a semiconductor chip of the present invention, the number of steps required for assembly, the type of material required, the amount of material used, the amount of industrial waste is reduced, and The external dimensions of the finished product can also be reduced.
Therefore, it is possible to manufacture a semiconductor chip suitable for high-density mounting with a short manufacturing time, a small manufacturing cost, and excellent productivity, and thereby to reduce the size, weight, and performance of an electronic device equipped with this semiconductor chip. .

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a state in which a first cutting is performed in a process example to which the present invention is applied, wherein FIG. 1A is a schematic perspective view of the whole wafer, and FIG. It is sectional drawing.

FIG. 2 is a schematic cross-sectional view showing a state in which a mold resin layer is formed on the entire surface of the wafer of FIG. 1 using a mold in the first embodiment of the present invention, and FIG. FIG. 1B is a schematic perspective view, and FIG.

3A and 3B are diagrams showing a state in which a second cutting is performed on the wafer of FIG. 2, wherein FIG. 3A is a schematic perspective view of the entire wafer, and FIG. FIG.

4A and 4B are diagrams showing a state in which the semiconductor chip is separated by stretching the sheet of FIG. 3, wherein FIG. 4A is a schematic perspective view of the entire wafer, and FIG. FIG.

FIG. 5 is a view showing a state in which a semiconductor chip is separated by stretching a sheet to which a wafer after the first cutting is adhered in the second embodiment of the present invention; FIG. 1B is a schematic cross-sectional view in which main parts are enlarged.

FIG. 6 is a diagram showing a state in which a mold resin layer is formed on the entire surface of the wafer of FIG. 5 and a second cutting is performed;
(A) is a schematic perspective view of the entire wafer, and (b) is a schematic cross-sectional view in which main parts are enlarged.

FIGS. 7A and 7B are views showing a state in which a wafer is being cut in a conventional process example, wherein FIG. 7A is a schematic perspective view of the entire wafer, and FIG. 7B is a schematic cross-sectional view in which main parts are enlarged. .

8A and 8B are diagrams showing a state in which the semiconductor chip is separated by stretching the sheet of FIG. 7, wherein FIG. 8A is a schematic perspective view of the whole wafer, and FIG. FIG.

9 is a schematic cross-sectional view showing a state where external leads are connected to the separated semiconductor chip of FIG. 8;

FIG. 10 is a schematic sectional view showing a state where a semiconductor package is completed by forming a mold resin layer and bending external leads.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Electrode pad 3 ... Insulating film 4 ... Bump
5: gap 6, 6a: mold resin layer C, C1, C2
... Semiconductor chip S ... Sheet DW ... Dicing wheel SL ... Scribe line W ... Wafer D ...
Mold CA… Cavity G… Gate

Claims (7)

[Claims] A first step of attaching a support member to the back side of a semiconductor substrate on which an integrated circuit is formed, and cutting only the semiconductor substrate from the front side by a first cutting along a scribe line; A second step of covering the upper surfaces of these semiconductor chips with a mold resin layer, including the gaps between adjacent semiconductor chips, while maintaining the aggregate state of the individual semiconductor chips formed by the second cutting; A third step of cutting the mold resin layer by a second cutting along to form individual semiconductor chips again, and a fourth step of peeling the individual semiconductor chips from the support member. Semiconductor chip manufacturing method. 2. The method of manufacturing a semiconductor chip according to claim 1, wherein the size of the gap is made equal to a cutting margin at the time of the first cutting and the second cutting. 3. The method according to claim 1, wherein the size of the gap is larger than a cutting margin at the time of the second cutting.
The manufacturing method of the semiconductor chip described in the above. 4. The size of the gap between adjacent semiconductor chips by extending the support member in a two-dimensional plane after performing the first cutting, so that a margin for the first cutting is provided. 4. The method for manufacturing a semiconductor chip according to claim 3, wherein the value is larger than the value. 5. The method according to claim 1, wherein in the second step, the mold resin layer is formed so as to expose an upper surface of an external connection terminal formed in advance on a surface of each of the semiconductor chips. A method for manufacturing a semiconductor chip. 6. In the second step, the mold resin layer is formed by injecting a resin into a cavity of a mold corresponding to the height of the external connection terminal, so that the mold resin layer has the same upper surface as the mold resin layer. 6. The method according to claim 5, wherein the external connection terminals are exposed in a plane. 7. The method according to claim 6, wherein the external connection terminals are bumps.