JP2002016210A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002016210A JP2002016210A JP2000196426A JP2000196426A JP2002016210A JP 2002016210 A JP2002016210 A JP 2002016210A JP 2000196426 A JP2000196426 A JP 2000196426A JP 2000196426 A JP2000196426 A JP 2000196426A JP 2002016210 A JP2002016210 A JP 2002016210A
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor chip
- lead
- fixed
- bridge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数の半導体チッ
プがアイランドに平面的におよび一部は立体的に配列さ
れた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor chips are arranged on an island two-dimensionally and partially three-dimensionally.
【０００２】[0002]
【従来の技術】近年、モールド型半導体チップが高機能
に成っており、複数の半導体チップを１パッケージ化す
るものが開発されている。2. Description of the Related Art In recent years, a mold type semiconductor chip has become highly functional, and a type in which a plurality of semiconductor chips are integrated into one package has been developed.
【０００３】この技術として例えば、特開平５−１２１
６４５号公報の従来例がある。これは、図５に示すよう
に、第１の半導体チップ１および第２の半導体チップ２
が１つのリードフレームの１つのアイランド３に固着さ
れている。第１および第２の半導体チップ１、２のボン
ディングパット４、５とリード６の先端が金属細線７に
より実現され、全体が樹脂で封止されている。そして、
第１の半導体チップ１と第２の半導体チップ２との間の
接続は、ボンディングパット８、９の間を金属細線１０
により接続されている。As this technique, for example, Japanese Patent Laid-Open No. 5-121 is disclosed.
There is a conventional example of JP-A-645-645. This is, as shown in FIG. 5, the first semiconductor chip 1 and the second semiconductor chip 2
Are fixed to one island 3 of one lead frame. The bonding pads 4 and 5 of the first and second semiconductor chips 1 and 2 and the tips of the leads 6 are realized by thin metal wires 7, and the whole is sealed with resin. And
The connection between the first semiconductor chip 1 and the second semiconductor chip 2 is performed by connecting a thin metal wire 10 between the bonding pads 8 and 9.
Connected by
【０００４】[0004]
【発明が解決しようとする課題】金属細線による電気的
接続は、一般にワイヤボンディングにより実現され、一
端はボールボンディング、他端はステッチボンディング
により実現されている。また、ステッチボンディング
は、金属細線をキャピラリーチップ（ボンディングツー
ル）で強く押さえ力で引きちぎるため、ステッチボンデ
ィング下の部分には直接キャピラリーチップがぶつかり
ストレスが加わる。リード６とボンディングパット５と
の間は、リード側をステッチボンディング、ボンディン
グパット側をボールボンディングにすれば、半導体チッ
プにはストレスは加わりにくいが、ボンディングパット
８とボンディングパット９との間は、どちらか一方は、
必ずステッチボンディングとなり、どちらか一方の半導
体チップのボンディングパットにストレスが加わる。最
近は、ボンディングパットの下に保護ダイオード等の半
導体装置が組み込まれるため、このストレスにより半導
体装置自身が不良になったり、ボンディングパット下の
半導体素子が破壊してしまう問題があった。The electrical connection by a thin metal wire is generally realized by wire bonding, one end is realized by ball bonding, and the other end is realized by stitch bonding. Further, in the stitch bonding, since a thin metal wire is strongly torn off by a capillary chip (bonding tool) with a pressing force, the capillary chip directly hits a portion under the stitch bonding and a stress is applied. If the lead side is stitch-bonded and the bonding pad side is ball-bonded between the lead 6 and the bonding pad 5, stress is less likely to be applied to the semiconductor chip. On the other hand,
Stitch bonding is always performed, and stress is applied to the bonding pad of one of the semiconductor chips. Recently, since a semiconductor device such as a protection diode is incorporated under the bonding pad, there has been a problem that the semiconductor device itself becomes defective or a semiconductor element under the bonding pad is destroyed by the stress.
【０００５】[0005]
【課題を解決するための手段】本発明は、前述の課題に
鑑みてなされ、第１に、第１のアイランドと第２のアイ
ランド間を橋渡しする２本の橋絡リードと、前記第１の
アイランド、前記第２のアイランドおよび橋絡リードと
で囲まれた領域に設けられ、電気的に分離されたボンデ
ィング可能なブリッヂを設けることで、半導体チップ側
の接続はボールボンディングで、前記ブリッヂ側の接続
はステッチボンディングで実現することができる。ま
た、前記２本の橋絡リードはそれぞれプレス・カット等
で第１のアイランドと第２のアイランドを電気的に分離
し、第１の半導体チップのノイズが第２の半導体チップ
へ侵入しないような構造をとっている。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and firstly, two bridging leads for bridging between a first island and a second island; By providing an electrically separated bondable bridge provided in a region surrounded by the island, the second island, and the bridging lead, the connection on the semiconductor chip side is performed by ball bonding, and the connection on the bridge side is performed. The connection can be realized by stitch bonding. The two bridging leads electrically separate the first and second islands by press cutting or the like, respectively, so that noise of the first semiconductor chip does not enter the second semiconductor chip. It has a structure.
【０００６】また、前記ブリッヂを接着テープにより固
定し、この接着テープが設けられた領域に対応する橋絡
リードに前記切断分離を設けることで、この切断分離部
とブリッヂの安定化を図っている。In addition, the bridge is fixed by an adhesive tape, and the bridge lead corresponding to the area where the adhesive tape is provided is provided with the cut / separation, thereby stabilizing the cut / separated portion and the bridge. .
【０００７】また、前記第１の半導体チップおよび前記
第２の半導体チップを、絶縁性接着剤により固着するこ
とで解決するものである。この接着剤（例えば体積抵抗
率１０の５乗程度）の使用で、チップとアイランド間の
インピーダンスが高くなり、ノイズの伝搬を抑制するこ
とができる。Another object is to solve the problem by fixing the first semiconductor chip and the second semiconductor chip with an insulating adhesive. The use of this adhesive (for example, about 5 times the volume resistivity of 10) increases the impedance between the chip and the island, thereby suppressing the propagation of noise.
【０００８】[0008]
【発明の実施の形態】以下に本発明の第１の実施の形態
を図１を参照しながら詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below in detail with reference to FIG.
【０００９】図に示したように、第１のアイランド２０
上には第１の親子半導体チップ２２が形成され、第２の
アイランド２１上には第２の半導体チップ２４が形成さ
れている。第１および第２の半導体チップ２２、２４の
シリコン表面には、前工程において各種の能動、受動回
路素子が形成され、更にチップの周辺部に外部接続用の
ボンディングパット２５、２６、２７が形成されてい
る。そのボンディングパット２５、２６、２７を被覆す
るようにシリコン窒化膜、シリコン酸化膜、ポリイミド
系絶縁膜などのパッシベーション被膜が形成され、ボン
ディングパット２５、２６、２７の上部は、ボンディン
グ接続のために開口されている。As shown, the first island 20
A first parent-child semiconductor chip 22 is formed thereon, and a second semiconductor chip 24 is formed on the second island 21. Various active and passive circuit elements are formed on the silicon surface of the first and second semiconductor chips 22 and 24 in the previous process, and bonding pads 25, 26 and 27 for external connection are formed on the periphery of the chips. Have been. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide-based insulating film is formed so as to cover the bonding pads 25, 26, and 27. The upper portions of the bonding pads 25, 26, and 27 are opened for bonding connection. Have been.
【００１０】第１および第２の半導体チップ２２、２４
はリードフレームの第１および第２のアイランド２０、
２１に接着材（ここでは、半田や銀ベースト等）により
ダイボンドされ、第１および第２の半導体チップ２２、
２４表面のボンディングパット２５、２６、２７には、
金線等のボンディングワイヤ２８の一端がボールボンデ
ィングでワイヤボンドされており、ボンディングワイヤ
２８の他端は外部導出用のリード２９の先端部にステッ
チボンディングでワイヤボンドされている。First and second semiconductor chips 22, 24
Are the first and second islands 20 of the leadframe,
The first and second semiconductor chips 22 and 21 are die-bonded to each other by an adhesive (here, solder, silver base, or the like).
The bonding pads 25, 26, 27 on the surface 24
One end of a bonding wire 28 such as a gold wire is wire-bonded by ball bonding, and the other end of the bonding wire 28 is wire-bonded to the tip of an external lead 29 by stitch bonding.
【００１１】一方、第１の半導体チップ２２と第２の半
導体チップ２４との接続は、以下の構成になっている。
まず、第１および第２の半導体チップ２２、２４との間
に対応する第１および第２のアイランド２０、２１に
は、開口部３０が設けられ、この中には、必要な本数だ
けアイランド状のブリッヂ３１が設けられている。On the other hand, the connection between the first semiconductor chip 22 and the second semiconductor chip 24 has the following configuration.
First, openings 30 are provided in the first and second islands 20 and 21 corresponding to the first and second semiconductor chips 22 and 24, respectively. Bridge 31 is provided.
【００１２】前文では、第１および第２のアイランド２
０、２１に開口部３０を設けたと述べたが、第１のアイ
ランド２０と第２のアイランド２１とが２本の橋絡リー
ド３２、３３で囲まれた領域が、前記開口部３０を構成
しているとも言える。また、後述するがそれぞれの橋絡
リード３２、３３には離間部３４が設けられている。In the preamble, the first and second islands 2
Although it has been described that the openings 30 are provided at 0 and 21, the region where the first island 20 and the second island 21 are surrounded by the two bridging leads 32 and 33 constitutes the opening 30. It can be said that. Further, as will be described later, a separation portion 34 is provided in each of the bridging leads 32 and 33.
【００１３】本実施例では、リードフレーム形成時（プ
レスカットやエッチング）、第１および第２のアイラン
ド２０、２１と一体のブリッヂ３１、第１および第２の
アイランド２０、２１と一体の橋絡リード３２、３３
（ただし橋絡部に離間部３４が形成される）を形成して
おき、図１のように接着テープ３５を貼った後に、ブリ
ッヂ３１を第１および第２のアイランド２０、２１から
切り離せばよい。接着テープ３５は、ブリッヂ３１と離
間部３４を構成する橋絡リード３２、３３を貼りつける
ことになる。In this embodiment, when forming a lead frame (press cutting or etching), a bridge 31 integrated with the first and second islands 20 and 21 and a bridge integrated with the first and second islands 20 and 21 are formed. Leads 32, 33
(However, the separation portion 34 is formed in the bridge portion), and the bridge 31 may be separated from the first and second islands 20 and 21 after the adhesive tape 35 is applied as shown in FIG. . The adhesive tape 35 attaches the bridging leads 32 and 33 that constitute the bridge 31 and the separation portion 34.
【００１４】本発明は、このブリッヂ３１とボンディン
グパット２５、２６、２７との接続について、第１およ
び第２の半導体チップ２２、２４側のボンディングパッ
ト２５、２６、２７をボールボンディングで行い、ブリ
ッヂ３１側をステッチボンディングで行うことに特徴を
有する。According to the present invention, the bridge 31 is connected to the bonding pads 25, 26, 27 by bonding the bonding pads 25, 26, 27 on the first and second semiconductor chips 22, 24 by ball bonding. It is characterized by performing stitch bonding on the 31st side.
【００１５】また必要により、第１の半導体チップ２２
と第２の半導体チップ２４に組み込まれる回路により、
相互干渉を生じる場合がある。例えば、第１の半導体チ
ップ２２から発生するノイズが第１のアイランド２０、
橋絡リード３２、３３、第２のアイランド２１を介して
第２の半導体チップ２４に侵入する場合は、ここにプレ
スカット等で離間部３４を設けることで、このノイズの
侵入を防止できる。If necessary, the first semiconductor chip 22
And a circuit incorporated in the second semiconductor chip 24,
Mutual interference may occur. For example, the noise generated from the first semiconductor chip 22 may be the first island 20,
In the case of invading the second semiconductor chip 24 via the bridging leads 32, 33 and the second island 21, by providing a separation portion 34 by press cutting or the like, the intrusion of this noise can be prevented.
【００１６】金属細線によるワイヤボンディングは、一
端はボールボンディング、他端はステッチボンディンに
より実現されている。特に、ステッチボンディングは、
金属細線をキャピラリーチップで強く押さえ、力で引き
ちぎるため、ステッチボンディング下の部分にはストレ
スが加わるが、ブリッヂ３１側をステッチボンディング
とし第１および第２の半導体チップ２２、２４側をボー
ルボンディングとしたため、この第１および第２の半導
体チップ２２、２４のボンディングパット２５、２６、
２７下に加わるストレスを抑制することができる。従っ
て、ボンディングパット２５、２６、２７下の半導体素
子の劣化を抑制することができる。The wire bonding by the thin metal wire is realized by ball bonding at one end and by stitch bonding at the other end. In particular, stitch bonding
Since the thin metal wire is strongly pressed by the capillary chip and torn off by force, stress is applied to the portion under the stitch bonding, but the bridge 31 side is stitch bonding and the first and second semiconductor chips 22 and 24 are ball bonding. , Bonding pads 25, 26 of the first and second semiconductor chips 22, 24,
27 can be suppressed. Therefore, deterioration of the semiconductor element under the bonding pads 25, 26, 27 can be suppressed.
【００１７】第１および第２の半導体チップ２２、２
４、第１および第２のアイランド２０、２１の近傍まで
延在される複数のリード２３、２９の先端部、およびボ
ンディングワイヤ２８を含む主要部は、一点鎖線の如く
エポキシ系の熱硬化樹脂３６でモールドされ、パッケー
ジ化される。First and second semiconductor chips 22, 2
4. The tip of the plurality of leads 23 and 29 extending to the vicinity of the first and second islands 20 and 21 and the main part including the bonding wire 28 are made of an epoxy-based thermosetting resin 36 as indicated by a dashed line. And packaged.
【００１８】このような半導体装置の構造はフラッシュ
メモリ等に用いられ、半導体チップを２段に搭載するこ
とで高集積化ができ、また、メモリー容量を倍にするこ
とができる。Such a structure of a semiconductor device is used for a flash memory or the like. By mounting semiconductor chips in two stages, high integration can be achieved and the memory capacity can be doubled.
【００１９】次に、第２の実施の形態について図２から
図４を参照して説明する。図２は図１に示した半導体装
置と同様に親子チップを搭載する半導体チップの平面図
である。また、図２の半導体装置のＡ−Ａ線断面図であ
る図３に示したように、この半導体装置は、アイランド
上にマザーチップ４３を、そして、マザーチップ４３上
にドウターチップ４２をそれぞれ接着テープ４８または
半田や銀ペースト等を用いて接着されている。そして、
マザーチップ４３およびドウターチップ４２にボールボ
ンディングされたボンディングワイヤ４４、４９は、互
いに接触しショートしないように、ボンディングワイヤ
４９は、Ｍ型に加工されて第２のリード４５にステッチ
ボンディングされている。尚、ボンディングワイヤ４９
は必ずしもＭ型の形状でステッチボンディングされなく
ても良く、ボンディングワイヤ４４、４９が互いに接触
しない構造であれば良い。Next, a second embodiment will be described with reference to FIGS. FIG. 2 is a plan view of a semiconductor chip on which a parent-child chip is mounted, similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 3 which is a cross-sectional view of the semiconductor device of FIG. 2 along the line AA, this semiconductor device has a mother chip 43 bonded on an island, and a daughter chip 42 bonded on the mother chip 43. It is bonded using a tape 48 or solder or silver paste. And
The bonding wires 49 are machined into an M shape and stitch-bonded to the second leads 45 so that the bonding wires 44 and 49 ball-bonded to the mother chip 43 and the daughter chip 42 are in contact with each other and do not short-circuit. The bonding wire 49
Need not necessarily be stitch-bonded in an M-shape, as long as the bonding wires 44 and 49 do not contact each other.
【００２０】そして、この半導体装置の第２のリード４
５は、第１の実施の形態でのブリッジ３１と同様の役割
を果たす。第２のリード４５は、隣接する第１のリード
４１や電気的に使用されないリード５２に接続された状
態で加工される。そして、第２のリード４５が接着テー
プ４７で固定された後に、プレスカットにて第１のリー
ド４１やリード５２から切り離されることで、浮きピン
状に形成される。The second lead 4 of the semiconductor device
5 plays a role similar to that of the bridge 31 in the first embodiment. The second lead 45 is processed while being connected to the adjacent first lead 41 and the lead 52 that is not electrically used. Then, after the second lead 45 is fixed with the adhesive tape 47, the second lead 45 is cut off from the first lead 41 or the lead 52 by press cutting to form a floating pin.
【００２１】そのため、この第２のリード４５は、接着
テープ４７で接着されることでフレーム上に固定され
る。このとき、第１および第２のリード４１、４５はリ
ード幅が狭く形成されている。そのため、接着テープ４
７の接着面積を確保するため第２のリード４５に隣接す
る第１のリード４１に幅の広い部分４６を設けている。
そのことにより、接着テープ４７は第１および第２のリ
ード４１、４５上に確実に接着し、第２のリード４５は
固定される。Therefore, the second lead 45 is fixed on the frame by being adhered with an adhesive tape 47. At this time, the first and second leads 41 and 45 are formed to have a narrow lead width. Therefore, the adhesive tape 4
The first lead 41 adjacent to the second lead 45 is provided with a wide portion 46 in order to secure the bonding area 7.
As a result, the adhesive tape 47 is securely adhered onto the first and second leads 41 and 45, and the second lead 45 is fixed.
【００２２】その結果、第２のリード４５は、マザーチ
ップ４３とドウターチップ４２とを電気的に接続すると
き、第２のリード４５は接着テープ４７で固定されてい
るため浮き上がりや移動等を防止することができ、良好
なワイヤーボンディングが可能となる。ここで、接着テ
ープ４７は、半導体チップを囲むように第１および第２
のリード４１、４５上を全周に渡り形成される場合や、
また、第２のリード４５および隣接して設けられる第１
のリード４１の幅の広い部分４６を主に利用してその部
分で形成される場合もある。As a result, when the second lead 45 is electrically connected to the mother chip 43 and the daughter chip 42, the second lead 45 is fixed by the adhesive tape 47, so that the second lead 45 is prevented from floating or moving. And good wire bonding becomes possible. Here, the first and second adhesive tapes 47 surround the semiconductor chip.
Formed over the entire circumference on the leads 41 and 45 of
Further, the second lead 45 and the first lead 45
The lead 41 may be formed mainly by using the wide portion 46 of the lead 41.
【００２３】本発明は、第１の実施の形態において、こ
のブリッヂ３１とボンディングパット２５、２６、２７
との接続について、第１および第２の半導体チップ２
２、２４側のボンディングパット２５，２６、２７をボ
ールボンディングで行い、ブリッヂ３１側をステッチボ
ンディングで行うことに特徴を有する。According to the present invention, in the first embodiment, the bridge 31 and the bonding pads 25, 26, 27
Connection with the first and second semiconductor chips 2
It is characterized in that the bonding pads 25, 26, 27 on the 2, 24 side are performed by ball bonding, and the bridge 31 side is performed by stitch bonding.
【００２４】また、接着テープ３５は前実施の形態と同
様に、ブリッヂ３１や離間部３４を有する橋絡リード３
２、３３を支持している。従って、離間部３４により、
一方の半導体チップから発生するノイズが、橋絡リード
３２、３３を介して他方のチップへ入るのを防止するこ
とができる。The adhesive tape 35 is made of a bridging lead 3 having a bridge 31 and a separation portion 34 as in the previous embodiment.
2, 33 are supported. Therefore, by the separating portion 34,
Noise generated from one semiconductor chip can be prevented from entering the other chip via the bridging leads 32, 33.
【００２５】特に、ノイズの伝搬の原因が、半導体チッ
プを固着する接着材にあることが判った。つまり、銀入
りの接着剤（銀ペースト）を採用すると、ノイズがペー
スト、第１および第２のアイランド２０、２１を介して
他方のチップに伝搬することが判った。In particular, it has been found that the cause of noise propagation is the adhesive material for fixing the semiconductor chip. That is, it was found that when an adhesive containing silver (silver paste) was employed, noise propagated to the other chip via the paste and the first and second islands 20 and 21.
【００２６】例えば、一方の半導体チップがＩＬＬによ
るデジタルオートバランス回路内蔵で、１〜８（Ｈｚ）
の動作クロックを持ち、他方の半導体チップは、Ｃ−Ｍ
ＯＳロジックによるデジタルディレイライン内蔵で、数
１００〜数ＭＨｚの動作クロックを有した場合、ディレ
イラインで発生する動作クロックノイズがオートバラン
ス回路の動作クロックに混入し、動作速度が速くなる等
の異常動作が発生した。For example, one of the semiconductor chips has a built-in digital auto-balance circuit by ILL and has a frequency of 1 to 8 (Hz).
And the other semiconductor chip has a CM
If the digital delay line built by OS logic has an operation clock of several hundreds to several MHz, the operation clock noise generated in the delay line will be mixed into the operation clock of the auto balance circuit, and the operation speed will be increased. There has occurred.
【００２７】しかし、前記離間部３４の設置またはイン
ピーダンスの高い絶縁性接着剤によるチップの固着で、
これらの問題が解決された。この絶縁性接着剤は、片方
の半導体チップに採用しても良いが、プロセス上両者に
採用しても良い。However, by installing the separating portion 34 or fixing the chip with an insulating adhesive having high impedance,
These problems have been solved. This insulating adhesive may be used for one of the semiconductor chips, or may be used for both in the process.
【００２８】そして、第２の実施の形態において、第２
のリード４５のようにリードが浮きピン状に形成される
場合、第２のリード４５に隣接する第１のリード４１に
幅の広い部分４６を設ける。そのことにより、第２のリ
ード４５を接着テープ４７で固定するとき、接着テープ
４７の接着面積が確保され、第２のリード４５がより安
定して固定され、半導体チップとの良好なワイヤーボン
ディングを可能にすることができる。In the second embodiment, the second
When the lead is formed in the shape of a floating pin like the lead 45 of the first embodiment, a wide portion 46 is provided on the first lead 41 adjacent to the second lead 45. Thereby, when the second lead 45 is fixed with the adhesive tape 47, the bonding area of the adhesive tape 47 is ensured, the second lead 45 is more stably fixed, and good wire bonding with the semiconductor chip can be performed. Can be made possible.
【００２９】[0029]
【発明の効果】以上に説明した通り、本発明によれば、
第１に、２つの半導体チップの間に位置するアイランド
に開口部を設け、この開口部にブリッヂを設け、半導体
チップ側の接続はボールボンディングで、前記ブリッヂ
側の接続はステッチボンディングで金属細線をワイヤー
ボンディングすることで、ボンディングパット下の半導
体素子の劣化を防止することができる。As described above, according to the present invention,
First, an opening is provided in an island located between two semiconductor chips, and a bridge is provided in the opening. The connection on the semiconductor chip side is made by ball bonding, and the connection on the bridge side is made by stitch bonding to form a thin metal wire. By performing wire bonding, deterioration of the semiconductor element under the bonding pad can be prevented.
【００３０】しかもチップとチップの接続は、１本の金
属細線から２本の金属細線に分割したため、ボンディン
グの際にこの金属細線の高さを低くすることができる。
従って、封止樹脂の厚みを薄くすることができる。Furthermore, since the connection between the chips is divided from one thin metal wire into two thin metal wires, the height of the thin metal wire can be reduced during bonding.
Therefore, the thickness of the sealing resin can be reduced.
【００３１】第２に、半導体チップを２段に搭載し半導
体装置を形成したことで、高集積化が可能となり、ま
た、メモリー容量が増大された半導体装置を得ることが
できる。Second, by forming a semiconductor device by mounting semiconductor chips in two stages, high integration is possible and a semiconductor device with an increased memory capacity can be obtained.
【００３２】第３に、橋絡リードの設置または絶縁性接
着剤の使用で、一方のチップから他方へのノイズの侵入
を制御することができる。Third, the placement of bridging leads or the use of an insulating adhesive can control the penetration of noise from one chip to the other.
【００３３】また、ブリッヂをリードフレームの形成時
に同時に形成するため、ブリッヂをプレスで簡単にに分
離でき、また、接着テープによりブリッヂを固定できる
ため、良好なワイヤーボンディングが可能となる。Further, since the bridge is formed simultaneously with the formation of the lead frame, the bridge can be easily separated by a press, and the bridge can be fixed by an adhesive tape, so that good wire bonding can be performed.
【００３４】第４に、浮きピンに形成されたリードおよ
びそのリードに隣接するリードに幅の広いリードを形成
し一体に接着テープで固定することで、浮きピン状のリ
ードが確実に固定され半導体チップとの良好なワイヤー
ボンディングが可能となる。Fourthly, by forming a wide lead on a lead formed on a floating pin and a lead adjacent to the lead and integrally fixing the lead with an adhesive tape, the floating pin-shaped lead is securely fixed. Good wire bonding with the chip becomes possible.
【図１】本発明の第１の実施の形態を説明する半導体装
置の平面図である。FIG. 1 is a plan view of a semiconductor device illustrating a first embodiment of the present invention.
【図２】本発明の第１および第２の実施の形態を説明す
る半導体装置の平面図である。FIG. 2 is a plan view of a semiconductor device illustrating first and second embodiments of the present invention.
【図３】図２に示した本発明の半導体装置のＡ−Ａ線断
面図である。FIG. 3 is a cross-sectional view taken along line AA of the semiconductor device of the present invention shown in FIG. 2;
【図４】本発明の第２の実施の形態を説明する半導体装
置の平面図である。FIG. 4 is a plan view of a semiconductor device illustrating a second embodiment of the present invention.
【図５】従来の半導体装置の平面図である。FIG. 5 is a plan view of a conventional semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 竹澤 良典 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 Ｆターム(参考） 5F044 AA01 AA10 AA12 CC05 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshinori Takezawa 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. (reference) 5F044 AA01 AA10 AA12 CC05
Claims (8)
第１のアイランドおよび第２の半導体チップの固着領域
を有する第２のアイランドと、 前記第１のアイランドと前記第２のアイランド間を橋渡
しする２本の連絡リードと、 前記第１のアイランド、前記第２のアイランドの周辺に
延在された複数のリードと、 前記第１のアイランドに固着された第１の親子半導体チ
ップおよび前記第２のアイランドに固着された第２の半
導体チップと、 前記第１の親子半導体チップおよび前記第２の半導体チ
ップと前記リードを電気的に接続する第１の金属細線
と、 前記第１のアイランド、前記第２のアイランドおよび前
記橋絡リードとで囲まれた領域に設けられ、電気的に分
離されたボンディング可能なブリッヂと、 前記半導体チップと前記ブリッヂとの間に設けられ、半
導体チップ側の接続はボールボンディングで、前記ブリ
ッヂ側の接続はステッチボンディングで実現される第２
の金属細線とを有し、 前記第１のアイランドと前記第２のアイランドとを電気
的に分離するため、前記２本の橋絡リードはそれぞれ分
離されていることを特徴とした半導体装置。1. A first island having a fixed region of a first semiconductor chip and a second island having a fixed region of a second semiconductor chip, and bridging between the first island and the second island. A plurality of leads extending around the first island and the second island; a first parent-child semiconductor chip fixed to the first island; and the second A second semiconductor chip fixed to the island, a first thin metal wire for electrically connecting the first parent-child semiconductor chip and the second semiconductor chip to the lead, the first island, An electrically isolated bondable bridge provided in a region surrounded by a second island and the bridging lead; and the semiconductor chip and the bridge. The connection on the semiconductor chip side is realized by ball bonding, and the connection on the bridge side is realized by stitch bonding.
Wherein the two bridging leads are separated from each other so as to electrically separate the first island and the second island from each other.
間されて成る請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the separation of the bridging leads is separated by cutting.
され、この接着テープが設けられた領域に対応する橋絡
リードに前記切断分離が設けられる請求項２記載の半導
体装置。3. The semiconductor device according to claim 2, wherein said bridge is fixed by an adhesive tape, and said cut-off is provided in a bridging lead corresponding to a region where said adhesive tape is provided.
第１のアイランドおよびだい２の半導体チップの固着領
域を有する第２のアイランドと、 前記第１のアイランドと前記第２のアイランド間を橋渡
しする２本の連絡リードと、 前記第１のアイランド、前記第２のアイランドの周辺に
延在された複数のリードと、 前記第１のアイランドに固着された第１の親子半導体チ
ップおよび前記第２のアイランドに固着された前記第２
の半導体チップと、 前記第１の親子半導体チップおよび前記第２の半導体チ
ップと前記リードを電気的に接続する第１の金属細線
と、 前記第１のアイランド、前記第２のアイランドおよび前
記橋絡リードとで囲まれた領域に設けられ、電気的に分
離されたボンディング可能なブリッヂと、 前記半導体チップと前記ブリッヂとの間に設けられ、半
導体チップ側の接続はボールボンディングで、前記ブリ
ッヂ側の接続はステッチボンディングで実現される第２
の金属細線とを有し、 前記第１の親子半導体チップおよび前記第２の半導体チ
ップは、絶縁性接着剤により固着されることを特徴とし
た半導体装置。4. A first island having a fixed region of the first semiconductor chip and a second island having a fixed region of about two semiconductor chips, and bridging between the first island and the second island. A plurality of leads extending around the first island and the second island; a first parent-child semiconductor chip fixed to the first island; and the second The second fixed to the island of
A first metal wire that electrically connects the first parent-child semiconductor chip and the second semiconductor chip to the lead; a first island, the second island, and the bridge A bridge that is provided in a region surrounded by the leads and is electrically separated and can be bonded; and is provided between the semiconductor chip and the bridge. The connection on the semiconductor chip side is ball bonding, and the connection on the bridge side is Connection is realized by stitch bonding
Wherein the first parent-child semiconductor chip and the second semiconductor chip are fixed with an insulating adhesive.
ンドと、 前記アイランドを囲むように周辺に延在された外部に導
出される第１のリードおよび外部に導出されない第２の
リードと、 前記アイランドに固着された親子半導体チップと、 前記親子半導体チップと前記第１および第２のリードを
電気的に接続する金属細線とを有し、 前記第２のリードは接着テープにより固定され、前記親
子半導体チップは前記第２のリードを介して電気的に接
続されることを特徴とした半導体装置。5. An island having a fixed region of a semiconductor chip, a first lead extending to the periphery surrounding the island and a second lead not extending to the outside, A parent-child semiconductor chip fixed thereto; and a fine metal wire for electrically connecting the parent-child semiconductor chip to the first and second leads, wherein the second lead is fixed by an adhesive tape, and the parent-child semiconductor chip is provided. Is a semiconductor device electrically connected via the second lead.
よびその近傍に位置する第１のリードと接着されること
を特徴とした請求項５記載の半導体装置。6. The semiconductor device according to claim 5, wherein the adhesive tape is bonded to the second lead and a first lead located near the second lead.
プを囲むように全周に渡り形成されることを特徴とした
請求項５記載の半導体装置。7. The semiconductor device according to claim 5, wherein the adhesive tape is formed over the entire circumference so as to surround the parent and child semiconductor chips.
リードは、リード幅が広く形成されることを特徴とした
請求項５記載の半導体装置。8. The semiconductor device according to claim 5, wherein said first lead adjacent to said second lead has a wide lead width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000196426A JP3702152B2 (en) | 2000-06-29 | 2000-06-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000196426A JP3702152B2 (en) | 2000-06-29 | 2000-06-29 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005172460A Division JP4275109B2 (en) | 2005-06-13 | 2005-06-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002016210A true JP2002016210A (en) | 2002-01-18 |
| JP3702152B2 JP3702152B2 (en) | 2005-10-05 |
Family
ID=18694924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000196426A Expired - Fee Related JP3702152B2 (en) | 2000-06-29 | 2000-06-29 | Semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3702152B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064076A (en) * | 2003-08-20 | 2005-03-10 | Sanyo Electric Co Ltd | Circuit device |
| JP2007027579A (en) * | 2005-07-20 | 2007-02-01 | Fujitsu Ltd | Relay substrate and semiconductor device comprising it |
| JP2007281509A (en) * | 2007-06-15 | 2007-10-25 | Sanyo Electric Co Ltd | Semiconductor device |
-
2000
- 2000-06-29 JP JP2000196426A patent/JP3702152B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005064076A (en) * | 2003-08-20 | 2005-03-10 | Sanyo Electric Co Ltd | Circuit device |
| JP2007027579A (en) * | 2005-07-20 | 2007-02-01 | Fujitsu Ltd | Relay substrate and semiconductor device comprising it |
| JP4703300B2 (en) * | 2005-07-20 | 2011-06-15 | 富士通セミコンダクター株式会社 | Relay board and semiconductor device including the relay board |
| JP2007281509A (en) * | 2007-06-15 | 2007-10-25 | Sanyo Electric Co Ltd | Semiconductor device |
| JP4642047B2 (en) * | 2007-06-15 | 2011-03-02 | 三洋電機株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3702152B2 (en) | 2005-10-05 |
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