JP3702152B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3702152B2
JP3702152B2 JP2000196426A JP2000196426A JP3702152B2 JP 3702152 B2 JP3702152 B2 JP 3702152B2 JP 2000196426 A JP2000196426 A JP 2000196426A JP 2000196426 A JP2000196426 A JP 2000196426A JP 3702152 B2 JP3702152 B2 JP 3702152B2
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Prior art keywords
lead
bonding
semiconductor chip
chip
bridge
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JP2000196426A
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JP2002016210A (en
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公 落合
誠 坪野谷
良典 竹澤
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体チップがアイランドに平面的におよび一部は立体的に配列された半導体装置に関する。
【０００２】
【従来の技術】
近年、モールド型半導体チップが高機能に成っており、複数の半導体チップを１パッケージ化するものが開発されている。
【０００３】
この技術として例えば、特開平５−１２１６４５号公報の従来例がある。これは、図５に示すように、第１の半導体チップ１および第２の半導体チップ２が１つのリードフレームの１つのアイランド３に固着されている。第１および第２の半導体チップ１、２のボンディングパット４、５とリード６の先端が金属細線７により実現され、全体が樹脂で封止されている。そして、第１の半導体チップ１と第２の半導体チップ２との間の接続は、ボンディングパット８、９の間を金属細線１０により接続されている。
【０００４】
【発明が解決しようとする課題】
金属細線による電気的接続は、一般にワイヤボンディングにより実現され、一端はボールボンディング、他端はステッチボンディングにより実現されている。また、ステッチボンディングは、金属細線をキャピラリーチップ（ボンディングツール）で強く押さえ力で引きちぎるため、ステッチボンディング下の部分には直接キャピラリーチップがぶつかりストレスが加わる。リード６とボンディングパット５との間は、リード側をステッチボンディング、ボンディングパット側をボールボンディングにすれば、半導体チップにはストレスは加わりにくいが、ボンディングパット８とボンディングパット９との間は、どちらか一方は、必ずステッチボンディングとなり、どちらか一方の半導体チップのボンディングパットにストレスが加わる。最近は、ボンディングパットの下に保護ダイオード等の半導体装置が組み込まれるため、このストレスにより半導体装置自身が不良になったり、ボンディングパット下の半導体素子が破壊してしまう問題があった。
【０００５】
【課題を解決するための手段】
本発明は、前述の課題に鑑みてなされ、第１に、第１のアイランドと第２のアイランド間を橋渡しする２本の橋絡リードと、前記第１のアイランド、前記第２のアイランドおよび橋絡リードとで囲まれた領域に設けられ、電気的に分離されたボンディング可能なブリッヂを設けることで、半導体チップ側の接続はボールボンディングで、前記ブリッヂ側の接続はステッチボンディングで実現することができる。また、前記２本の橋絡リードはそれぞれプレス・カット等で第１のアイランドと第２のアイランドを電気的に分離し、第１の半導体チップのノイズが第２の半導体チップへ侵入しないような構造をとっている。
【０００６】
また、前記ブリッヂを接着テープにより固定し、この接着テープが設けられた領域に対応する橋絡リードに前記切断分離を設けることで、この切断分離部とブリッヂの安定化を図っている。
【０００７】
また、前記第１の半導体チップおよび前記第２の半導体チップを、絶縁性接着剤により固着することで解決するものである。この接着剤（例えば体積抵抗率１０の５乗程度）の使用で、チップとアイランド間のインピーダンスが高くなり、ノイズの伝搬を抑制することができる。
【０００８】
【発明の実施の形態】
以下に本発明の第１の実施の形態を図１を参照しながら詳細に説明する。
【０００９】
図に示したように、第１のアイランド２０上には第１の親子半導体チップ２２が形成され、第２のアイランド２１上には第２の半導体チップ２４が形成されている。第１および第２の半導体チップ２２、２４のシリコン表面には、前工程において各種の能動、受動回路素子が形成され、更にチップの周辺部に外部接続用のボンディングパット２５、２６、２７が形成されている。そのボンディングパット２５、２６、２７を被覆するようにシリコン窒化膜、シリコン酸化膜、ポリイミド系絶縁膜などのパッシベーション被膜が形成され、ボンディングパット２５、２６、２７の上部は、ボンディング接続のために開口されている。
【００１０】
第１および第２の半導体チップ２２、２４はリードフレームの第１および第２のアイランド２０、２１に接着材（ここでは、半田や銀ベースト等）によりダイボンドされ、第１および第２の半導体チップ２２、２４表面のボンディングパット２５、２６、２７には、金線等のボンディングワイヤ２８の一端がボールボンディングでワイヤボンドされており、ボンディングワイヤ２８の他端は外部導出用のリード２９の先端部にステッチボンディングでワイヤボンドされている。
【００１１】
一方、第１の半導体チップ２２と第２の半導体チップ２４との接続は、以下の構成になっている。まず、第１および第２の半導体チップ２２、２４との間に対応する第１および第２のアイランド２０、２１には、開口部３０が設けられ、この中には、必要な本数だけアイランド状のブリッヂ３１が設けられている。
【００１２】
前文では、第１および第２のアイランド２０、２１に開口部３０を設けたと述べたが、第１のアイランド２０と第２のアイランド２１とが２本の橋絡リード３２、３３で囲まれた領域が、前記開口部３０を構成しているとも言える。また、後述するがそれぞれの橋絡リード３２、３３には離間部３４が設けられている。
【００１３】
本実施例では、リードフレーム形成時（プレスカットやエッチング）、第１および第２のアイランド２０、２１と一体のブリッヂ３１、第１および第２のアイランド２０、２１と一体の橋絡リード３２、３３（ただし橋絡部に離間部３４が形成される）を形成しておき、図１のように接着テープ３５を貼った後に、ブリッヂ３１を第１および第２のアイランド２０、２１から切り離せばよい。接着テープ３５は、ブリッヂ３１と離間部３４を構成する橋絡リード３２、３３を貼りつけることになる。
【００１４】
本発明は、このブリッヂ３１とボンディングパット２５、２６、２７との接続について、第１および第２の半導体チップ２２、２４側のボンディングパット２５、２６、２７をボールボンディングで行い、ブリッヂ３１側をステッチボンディングで行うことに特徴を有する。
【００１５】
また必要により、第１の半導体チップ２２と第２の半導体チップ２４に組み込まれる回路により、相互干渉を生じる場合がある。例えば、第１の半導体チップ２２から発生するノイズが第１のアイランド２０、橋絡リード３２、３３、第２のアイランド２１を介して第２の半導体チップ２４に侵入する場合は、ここにプレスカット等で離間部３４を設けることで、このノイズの侵入を防止できる。
【００１６】
金属細線によるワイヤボンディングは、一端はボールボンディング、他端はステッチボンディンにより実現されている。特に、ステッチボンディングは、金属細線をキャピラリーチップで強く押さえ、力で引きちぎるため、ステッチボンディング下の部分にはストレスが加わるが、ブリッヂ３１側をステッチボンディングとし第１および第２の半導体チップ２２、２４側をボールボンディングとしたため、この第１および第２の半導体チップ２２、２４のボンディングパット２５、２６、２７下に加わるストレスを抑制することができる。従って、ボンディングパット２５、２６、２７下の半導体素子の劣化を抑制することができる。
【００１７】
第１および第２の半導体チップ２２、２４、第１および第２のアイランド２０、２１の近傍まで延在される複数のリード２３、２９の先端部、およびボンディングワイヤ２８を含む主要部は、一点鎖線の如くエポキシ系の熱硬化樹脂３６でモールドされ、パッケージ化される。
【００１８】
このような半導体装置の構造はフラッシュメモリ等に用いられ、半導体チップを２段に搭載することで高集積化ができ、また、メモリー容量を倍にすることができる。
【００１９】
次に、第２の実施の形態について図２から図４を参照して説明する。図２は図１に示した半導体装置と同様に親子チップを搭載する半導体チップの平面図である。また、図２の半導体装置のＡ−Ａ線断面図である図３に示したように、この半導体装置は、アイランド上にマザーチップ４３を、そして、マザーチップ４３上にドウターチップ４２をそれぞれ接着テープ４８または半田や銀ペースト等を用いて接着されている。そして、マザーチップ４３およびドウターチップ４２にボールボンディングされたボンディングワイヤ４４、４９は、互いに接触しショートしないように、ボンディングワイヤ４９は、Ｍ型に加工されて第２のリード４５にステッチボンディングされている。尚、ボンディングワイヤ４９は必ずしもＭ型の形状でステッチボンディングされなくても良く、ボンディングワイヤ４４、４９が互いに接触しない構造であれば良い。
【００２０】
そして、この半導体装置の第２のリード４５は、第１の実施の形態でのブリッジ３１と同様の役割を果たす。第２のリード４５は、隣接する第１のリード４１や電気的に使用されないリード５２に接続された状態で加工される。そして、第２のリード４５が接着テープ４７で固定された後に、プレスカットにて第１のリード４１やリード５２から切り離されることで、浮きピン状に形成される。
【００２１】
そのため、この第２のリード４５は、接着テープ４７で接着されることでフレーム上に固定される。このとき、第１および第２のリード４１、４５はリード幅が狭く形成されている。そのため、接着テープ４７の接着面積を確保するため第２のリード４５に隣接する第１のリード４１に幅の広い部分４６を設けている。そのことにより、接着テープ４７は第１および第２のリード４１、４５上に確実に接着し、第２のリード４５は固定される。
【００２２】
その結果、第２のリード４５は、マザーチップ４３とドウターチップ４２とを電気的に接続するとき、第２のリード４５は接着テープ４７で固定されているため浮き上がりや移動等を防止することができ、良好なワイヤーボンディングが可能となる。ここで、接着テープ４７は、半導体チップを囲むように第１および第２のリード４１、４５上を全周に渡り形成される場合や、また、第２のリード４５および隣接して設けられる第１のリード４１の幅の広い部分４６を主に利用してその部分で形成される場合もある。
【００２３】
本発明は、第１の実施の形態において、このブリッヂ３１とボンディングパット２５、２６、２７との接続について、第１および第２の半導体チップ２２、２４側のボンディングパット２５，２６、２７をボールボンディングで行い、ブリッヂ３１側をステッチボンディングで行うことに特徴を有する。
【００２４】
また、接着テープ３５は前実施の形態と同様に、ブリッヂ３１や離間部３４を有する橋絡リード３２、３３を支持している。従って、離間部３４により、一方の半導体チップから発生するノイズが、橋絡リード３２、３３を介して他方のチップへ入るのを防止することができる。
【００２５】
特に、ノイズの伝搬の原因が、半導体チップを固着する接着材にあることが判った。つまり、銀入りの接着剤（銀ペースト）を採用すると、ノイズがペースト、第１および第２のアイランド２０、２１を介して他方のチップに伝搬することが判った。
【００２６】
例えば、一方の半導体チップがＩＬＬによるデジタルオートバランス回路内蔵で、１〜８（Ｈｚ）の動作クロックを持ち、他方の半導体チップは、Ｃ−ＭＯＳロジックによるデジタルディレイライン内蔵で、数１００〜数ＭＨｚの動作クロックを有した場合、ディレイラインで発生する動作クロックノイズがオートバランス回路の動作クロックに混入し、動作速度が速くなる等の異常動作が発生した。
【００２７】
しかし、前記離間部３４の設置またはインピーダンスの高い絶縁性接着剤によるチップの固着で、これらの問題が解決された。この絶縁性接着剤は、片方の半導体チップに採用しても良いが、プロセス上両者に採用しても良い。
【００２８】
そして、第２の実施の形態において、第２のリード４５のようにリードが浮きピン状に形成される場合、第２のリード４５に隣接する第１のリード４１に幅の広い部分４６を設ける。そのことにより、第２のリード４５を接着テープ４７で固定するとき、接着テープ４７の接着面積が確保され、第２のリード４５がより安定して固定され、半導体チップとの良好なワイヤーボンディングを可能にすることができる。
【００２９】
【発明の効果】
以上に説明した通り、本発明によれば、第１に、２つの半導体チップの間に位置するアイランドに開口部を設け、この開口部にブリッヂを設け、半導体チップ側の接続はボールボンディングで、前記ブリッヂ側の接続はステッチボンディングで金属細線をワイヤーボンディングすることで、ボンディングパット下の半導体素子の劣化を防止することができる。
【００３０】
しかもチップとチップの接続は、１本の金属細線から２本の金属細線に分割したため、ボンディングの際にこの金属細線の高さを低くすることができる。従って、封止樹脂の厚みを薄くすることができる。
【００３１】
第２に、半導体チップを２段に搭載し半導体装置を形成したことで、高集積化が可能となり、また、メモリー容量が増大された半導体装置を得ることができる。
【００３２】
第３に、橋絡リードの設置または絶縁性接着剤の使用で、一方のチップから他方へのノイズの侵入を制御することができる。
【００３３】
また、ブリッヂをリードフレームの形成時に同時に形成するため、ブリッヂをプレスで簡単にに分離でき、また、接着テープによりブリッヂを固定できるため、良好なワイヤーボンディングが可能となる。
【００３４】
第４に、浮きピンに形成されたリードおよびそのリードに隣接するリードに幅の広いリードを形成し一体に接着テープで固定することで、浮きピン状のリードが確実に固定され半導体チップとの良好なワイヤーボンディングが可能となる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態を説明する半導体装置の平面図である。
【図２】本発明の第１および第２の実施の形態を説明する半導体装置の平面図である。
【図３】図２に示した本発明の半導体装置のＡ−Ａ線断面図である。
【図４】本発明の第２の実施の形態を説明する半導体装置の平面図である。
【図５】従来の半導体装置の平面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a plurality of semiconductor chips are arranged on an island in a planar manner and partly in a three-dimensional manner.
[0002]
[Prior art]
In recent years, a mold type semiconductor chip has a high function, and a semiconductor chip in which a plurality of semiconductor chips are packaged has been developed.
[0003]
As this technique, for example, there is a conventional example of JP-A-5-121645. As shown in FIG. 5, the first semiconductor chip 1 and the second semiconductor chip 2 are fixed to one island 3 of one lead frame. The tips of the bonding pads 4 and 5 and the leads 6 of the first and second semiconductor chips 1 and 2 are realized by a thin metal wire 7, and the whole is sealed with resin. And the connection between the 1st semiconductor chip 1 and the 2nd semiconductor chip 2 is connected between the bonding pads 8 and 9 by the metal fine wire 10. FIG.
[0004]
[Problems to be solved by the invention]
The electrical connection by the fine metal wire is generally realized by wire bonding, one end is realized by ball bonding and the other end is realized by stitch bonding. In stitch bonding, a fine metal wire is strongly pressed by a capillary tip (bonding tool) and is torn off with a force, so that the capillary tip directly hits the portion under the stitch bonding and stress is applied. Between the lead 6 and the bonding pad 5, if the lead side is stitch-bonded and the bonding pad side is ball-bonded, the semiconductor chip is hardly stressed, but between the bonding pad 8 and the bonding pad 9, One of them is always stitch bonding, and stress is applied to the bonding pad of one of the semiconductor chips. Recently, since a semiconductor device such as a protection diode is incorporated under the bonding pad, there is a problem that the semiconductor device itself becomes defective due to this stress, or the semiconductor element under the bonding pad is destroyed.
[0005]
[Means for Solving the Problems]
The present invention has been made in view of the above-mentioned problems. First, two bridge leads that bridge between the first island and the second island, the first island, the second island, and the bridge By providing a bondable bridge that is electrically isolated and provided in a region surrounded by the wire leads, the connection on the semiconductor chip side can be realized by ball bonding, and the connection on the bridge side can be realized by stitch bonding. it can. The two bridging leads electrically separate the first island and the second island by press cutting or the like so that the noise of the first semiconductor chip does not enter the second semiconductor chip. It has a structure.
[0006]
In addition, the bridge is fixed by an adhesive tape, and the cutting and separating is provided in the bridging lead corresponding to the region where the adhesive tape is provided, thereby stabilizing the cutting and separating portion and the bridge.
[0007]
Further, the problem is solved by fixing the first semiconductor chip and the second semiconductor chip with an insulating adhesive. Use of this adhesive (for example, about the fifth power of volume resistivity 10) increases the impedance between the chip and the island, and can suppress the propagation of noise.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIG.
[0009]
As shown in the figure, a first parent-child semiconductor chip 22 is formed on the first island 20, and a second semiconductor chip 24 is formed on the second island 21. Various active and passive circuit elements are formed in the previous process on the silicon surfaces of the first and second semiconductor chips 22 and 24, and bonding pads 25, 26, and 27 for external connection are formed in the periphery of the chip. Has been. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide insulating film is formed so as to cover the bonding pads 25, 26, and 27, and upper portions of the bonding pads 25, 26, and 27 are opened for bonding connection. Has been.
[0010]
The first and second semiconductor chips 22 and 24 are die-bonded to the first and second islands 20 and 21 of the lead frame with an adhesive (here, solder, silver base etc.), and the first and second semiconductor chips One end of a bonding wire 28 such as a gold wire is wire-bonded to the bonding pads 25, 26 and 27 on the surfaces 22 and 24 by ball bonding, and the other end of the bonding wire 28 is the tip of a lead 29 for external lead-out. It is wire bonded by stitch bonding.
[0011]
On the other hand, the connection between the first semiconductor chip 22 and the second semiconductor chip 24 has the following configuration. First, an opening 30 is provided in the first and second islands 20 and 21 corresponding to the first and second semiconductor chips 22 and 24, and a necessary number of islands are formed therein. The bridge 31 is provided.
[0012]
In the preceding sentence, it was described that the opening 30 was provided in the first and second islands 20 and 21, but the first island 20 and the second island 21 were surrounded by two bridging leads 32 and 33. It can be said that the region constitutes the opening 30. Further, as will be described later, the bridging leads 32 and 33 each have a separation portion 34.
[0013]
In this embodiment, when the lead frame is formed (press cut or etching), the bridge 31 integral with the first and second islands 20, 21 and the bridging lead 32 integral with the first and second islands 20, 21; 33 (the separation portion 34 is formed at the bridging portion), and after the adhesive tape 35 is applied as shown in FIG. 1, the bridge 31 is separated from the first and second islands 20 and 21. Good. The adhesive tape 35 affixes the bridging leads 32 and 33 constituting the bridge 31 and the separating portion 34.
[0014]
In the present invention, for the connection between the bridge 31 and the bonding pads 25, 26, 27, the bonding pads 25, 26, 27 on the first and second semiconductor chips 22, 24 are performed by ball bonding, and the bridge 31 side is It is characterized in that it is performed by stitch bonding.
[0015]
If necessary, mutual interference may occur due to circuits incorporated in the first semiconductor chip 22 and the second semiconductor chip 24. For example, when noise generated from the first semiconductor chip 22 enters the second semiconductor chip 24 via the first island 20, the bridging leads 32 and 33, and the second island 21, press cut is performed here. Providing the separation portion 34 by means of, for example, can prevent this noise from entering.
[0016]
Wire bonding using fine metal wires is realized by ball bonding at one end and stitch bonding at the other end. In particular, in stitch bonding, a metal thin wire is strongly pressed by a capillary chip and is torn off by force. Therefore, stress is applied to a portion under the stitch bonding, but the first and second semiconductor chips 22 and 24 are formed by stitch bonding on the bridge 31 side. Since the side is made of ball bonding, it is possible to suppress stress applied below the bonding pads 25, 26, 27 of the first and second semiconductor chips 22, 24. Therefore, the deterioration of the semiconductor elements under the bonding pads 25, 26, 27 can be suppressed.
[0017]
The main parts including the first and second semiconductor chips 22 and 24, the tips of the leads 23 and 29 extending to the vicinity of the first and second islands 20 and 21, and the main part including the bonding wire 28 are provided at one point. Molded with an epoxy-based thermosetting resin 36 like a chain line, and packaged.
[0018]
Such a structure of a semiconductor device is used for a flash memory or the like. By mounting semiconductor chips in two stages, high integration can be achieved and the memory capacity can be doubled.
[0019]
Next, a second embodiment will be described with reference to FIGS. FIG. 2 is a plan view of a semiconductor chip on which a parent-child chip is mounted in the same manner as the semiconductor device shown in FIG. Further, as shown in FIG. 3 which is a cross-sectional view taken along line AA of the semiconductor device of FIG. 2, this semiconductor device has a mother chip 43 bonded onto the island and a daughter chip 42 bonded onto the mother chip 43. Bonding is performed using tape 48 or solder or silver paste. The bonding wires 49 are processed into an M shape and stitch bonded to the second lead 45 so that the bonding wires 44 and 49 ball-bonded to the mother chip 43 and the daughter chip 42 are not in contact with each other and short-circuited. Yes. Note that the bonding wire 49 is not necessarily M-shaped and stitch-bonded, and may have any structure as long as the bonding wires 44 and 49 do not contact each other.
[0020]
The second lead 45 of this semiconductor device plays the same role as the bridge 31 in the first embodiment. The second lead 45 is processed in a state where it is connected to the adjacent first lead 41 or the lead 52 that is not electrically used. Then, after the second lead 45 is fixed with the adhesive tape 47, the second lead 45 is separated from the first lead 41 and the lead 52 by press cutting, thereby forming a floating pin shape.
[0021]
Therefore, the second lead 45 is fixed on the frame by being bonded with the adhesive tape 47. At this time, the first and second leads 41 and 45 are formed to have a narrow lead width. Therefore, a wide portion 46 is provided in the first lead 41 adjacent to the second lead 45 in order to secure the bonding area of the adhesive tape 47. As a result, the adhesive tape 47 is securely bonded onto the first and second leads 41 and 45, and the second lead 45 is fixed.
[0022]
As a result, when the second lead 45 electrically connects the mother chip 43 and the daughter chip 42, the second lead 45 is fixed by the adhesive tape 47, so that it can be prevented from being lifted or moved. And good wire bonding is possible. Here, the adhesive tape 47 is formed over the entire circumference on the first and second leads 41 and 45 so as to surround the semiconductor chip, or is provided adjacent to the second lead 45. In some cases, the wide portion 46 of one lead 41 is mainly used to form that portion.
[0023]
According to the present invention, in the first embodiment, the bonding pads 25, 26, 27 on the first and second semiconductor chips 22, 24 side are connected to the bridge 31 and the bonding pads 25, 26, 27. It is characterized by bonding, and the bridge 31 side is formed by stitch bonding.
[0024]
Further, the adhesive tape 35 supports the bridging leads 32 and 33 having the bridge 31 and the separating portion 34 as in the previous embodiment. Therefore, the separation portion 34 can prevent noise generated from one semiconductor chip from entering the other chip via the bridging leads 32 and 33.
[0025]
In particular, it has been found that the cause of noise propagation is the adhesive that fixes the semiconductor chip. That is, it has been found that when a silver-containing adhesive (silver paste) is employed, noise propagates to the other chip via the paste and the first and second islands 20 and 21.
[0026]
For example, one semiconductor chip has a built-in digital autobalance circuit by ILL and has an operation clock of 1 to 8 (Hz), and the other semiconductor chip has a built-in digital delay line by C-MOS logic and has several hundred to several MHz. When the operation clock is included, the operation clock noise generated in the delay line is mixed into the operation clock of the auto balance circuit, and an abnormal operation such as an increase in the operation speed occurs.
[0027]
However, these problems have been solved by installing the spacing portion 34 or fixing the chip with an insulating adhesive having a high impedance. This insulating adhesive may be employed for one semiconductor chip, but may be employed for both in the process.
[0028]
In the second embodiment, when the lead is formed like a floating pin like the second lead 45, the wide portion 46 is provided in the first lead 41 adjacent to the second lead 45. . As a result, when the second lead 45 is fixed with the adhesive tape 47, the bonding area of the adhesive tape 47 is secured, the second lead 45 is more stably fixed, and good wire bonding with the semiconductor chip is achieved. Can be possible.
[0029]
【The invention's effect】
As described above, according to the present invention, first, an opening is provided in an island located between two semiconductor chips, a bridge is provided in the opening, and the connection on the semiconductor chip side is performed by ball bonding. For the connection on the bridge side, deterioration of the semiconductor element under the bonding pad can be prevented by wire bonding the fine metal wire by stitch bonding.
[0030]
In addition, since the chip-to-chip connection is divided into two fine metal wires from one fine metal wire, the height of the fine metal wire can be lowered during bonding. Therefore, the thickness of the sealing resin can be reduced.
[0031]
Second, since the semiconductor device is formed by mounting the semiconductor chips in two stages, a high integration can be achieved and a semiconductor device with an increased memory capacity can be obtained.
[0032]
Third, the installation of bridge leads or the use of an insulating adhesive can control the intrusion of noise from one chip to the other.
[0033]
Further, since the bridge is formed at the same time as the lead frame is formed, the bridge can be easily separated with a press, and the bridge can be fixed with an adhesive tape, so that excellent wire bonding can be achieved.
[0034]
Fourthly, by forming a wide lead on the lead formed on the floating pin and the lead adjacent to the lead and fixing the lead integrally with an adhesive tape, the floating pin-shaped lead is securely fixed to the semiconductor chip. Good wire bonding is possible.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor device for explaining a first embodiment of the present invention;
FIG. 2 is a plan view of a semiconductor device for explaining first and second embodiments of the present invention;
3 is a cross-sectional view taken along line AA of the semiconductor device of the present invention shown in FIG. 2. FIG.
FIG. 4 is a plan view of a semiconductor device for explaining a second embodiment of the present invention;
FIG. 5 is a plan view of a conventional semiconductor device.

Claims (2)

一つのアイランドに固着された第１の半導体チップと、
前記第１の半導体チップ上に設けられた第２の半導体チップと、
前記アイランドの周辺に設けられた複数の第１のリードと、
前記アイランドの周辺に設けられると共に、前記第１のリードと隣接して設けられ、ブリッヂとして機能する複数の第２のリードと、
前記第１の半導体チップと前記第２のリードを接続する第１の金属細線と、
前記第１の金属細線が接続された前記第２のリードと前記第２の半導体チップを接続する第２の金属細線とを有し、
前記第２のリードと隣接する前記第１のリードには、幅広部が設けられ、前記複数の第２のリードおよび前記幅広部には、同一の接着テープが貼着されることを特徴とする半導体装置。 A first semiconductor chip fixed to one island;
A second semiconductor chip provided on the first semiconductor chip;
A plurality of first leads provided around the island;
A plurality of second leads provided around the island and adjacent to the first lead and functioning as a bridge;
A first thin metal wire connecting the first semiconductor chip and the second lead;
The second lead to which the first thin metal wire is connected and the second thin metal wire to connect the second semiconductor chip;
The first lead adjacent to the second lead is provided with a wide portion, and the same adhesive tape is attached to the plurality of second leads and the wide portion. Semiconductor device. 前記接着テープは、前記半導体チップを囲むように全周に渡り形成されることを特徴とする請求項１記載の半導体装置。    The semiconductor device according to claim 1, wherein the adhesive tape is formed over the entire circumference so as to surround the semiconductor chip.
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