JPS62154769A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62154769A JPS62154769A JP60292664A JP29266485A JPS62154769A JP S62154769 A JPS62154769 A JP S62154769A JP 60292664 A JP60292664 A JP 60292664A JP 29266485 A JP29266485 A JP 29266485A JP S62154769 A JPS62154769 A JP S62154769A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor pellet
- semiconductor
- pellet
- wiring
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 本発明は、半導体装置に適用して有効な技術に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a technique that is effective when applied to semiconductor devices.
半導体装置のパッケージサイズやそのリード間隔は規格
によって適当に制限される。一方、半導体ペレットはそ
の集積度の向上環の要請により、長大化する傾向にある
。そのため、半導体ペレットの端部とパッケージ端部と
の間のパッケージ部の巾が減少される。The package size and lead spacing of semiconductor devices are appropriately limited by standards. On the other hand, semiconductor pellets tend to become longer due to demands for increased integration. Therefore, the width of the package portion between the end of the semiconductor pellet and the end of the package is reduced.
ところで、パッケージのリード線は、一般的に言うと前
記半導体ペレット端部とパッケージ端部との間のパンケ
ージ部に配置される。この場合、パ・７ケージにおける
リード配線形成領域がますます制限されることになる。Incidentally, the lead wires of the package are generally arranged in the pan cage section between the end of the semiconductor pellet and the end of the package. In this case, the area for forming lead wiring in the P7 cage becomes increasingly limited.
そこで、本発明者等は、通常は配線形成が行われない半
導体ペレットの下部にも配線を形成し、配線形成領域を
広げることにより半導体ペレットの実装密度を向上させ
ることを検討した。Therefore, the present inventors have considered improving the packaging density of the semiconductor pellet by forming wiring also in the lower part of the semiconductor pellet, where wiring is not normally formed, and expanding the wiring formation area.
しかしながら、一般的な半導体ペレットにおいて、その
非回路形成面である裏面には、絶縁物が形成されていな
い。この場合、半導体ペレットを配線上に直接的に取付
けると、該配線と半導体ペレットとの間でショートを生
じる問題が生ずる。However, in a typical semiconductor pellet, no insulator is formed on the back surface, which is the non-circuit-forming surface. In this case, if the semiconductor pellet is attached directly onto the wiring, a problem arises in that a short circuit occurs between the wiring and the semiconductor pellet.
なお、半導体ペレットの実装については、１９８０年１
月１５日、株式会社工業調査会発行、日本マイクロエレ
クトロニクス協会編ｒ Ｉ Ｃ化実装技術ＪＰ１３６以
下に説明されている。Regarding the mounting of semiconductor pellets, the 1980 January
It is explained below in IC Mounting Technology JP 136, edited by Japan Microelectronics Association, published by Kogyo Kenkyukai Co., Ltd. on May 15th.
本発明の目的は、半導体ペレットの実装密度を向上する
ことができる技術を提供することにある。An object of the present invention is to provide a technique that can improve the packaging density of semiconductor pellets.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りであるゆすなわち、半導
体ペレットの裏面に絶縁膜を設けることにより、該半導
体ペレットの裏面を配線に直接接触させることが可能と
なるため、半導体ペレットの下にも配線を形成すること
が可能となる。したがって、配線形成領域を拡張できる
ことになり、それだけ大形の半導体ペレットを搭載する
ことが可能となり、前記目的が達成される。A brief overview of the typical inventions disclosed in this application is as follows.In other words, by providing an insulating film on the back surface of a semiconductor pellet, the back surface of the semiconductor pellet is brought into direct contact with wiring. Therefore, it becomes possible to form wiring also under the semiconductor pellet. Therefore, the wiring formation area can be expanded, and a larger semiconductor pellet can be mounted accordingly, thus achieving the above object.
〔実施例１〕
第１図は本発明による実施例１である半導体装置の概略
を示す第２図におけるＩ−１断面図で、第２図は上記半
導体装置の半導体ペレットとり−ドとの関係を示す概略
説明図である。[Example 1] Fig. 1 is a sectional view taken along line I-1 in Fig. 2 showing the outline of a semiconductor device according to an embodiment 1 of the present invention, and Fig. 2 shows the relationship between the semiconductor device and the semiconductor pellet lead. FIG.
本実施例１の半導体装置は、パッケージｌがエポキシ樹
脂等の樹脂でモールド形成された、いわゆる樹脂封止型
半導体装置である。上記パ・ノケージｌの内部には、そ
の裏面に二酸化ケイ素（ＳｉＯ□）からなる絶縁膜２が
形成された半導体ペレット３が封止されており、該半導
体ペレット３の雪掻パッド２ａとリード４とは金等のワ
イヤ５を介して電気的に接続されている。The semiconductor device of Example 1 is a so-called resin-sealed semiconductor device in which the package l is molded with a resin such as epoxy resin. A semiconductor pellet 3 having an insulating film 2 made of silicon dioxide (SiO□) formed on its back surface is sealed inside the package l, and the semiconductor pellet 3 has a snow scraping pad 2a and a lead 4. and are electrically connected via a wire 5 made of gold or the like.
また、本実施例１においては、該半導体ペレット３は、
その下に配設されているリード４にエポキシ樹脂からな
るような絶縁性接着剤６を介して接合されている。この
リード４は、パッケージｌの外に延在されている外部リ
ード４ａと連続しているものである。Moreover, in the present Example 1, the semiconductor pellet 3 is
It is bonded to a lead 4 disposed below it via an insulating adhesive 6 made of epoxy resin. This lead 4 is continuous with an external lead 4a extending outside the package l.
このような半導体装置は、次のようにして製造される。Such a semiconductor device is manufactured as follows.
すなわち、まずフレーム部、リード部およびリード部間
に配置されたタイバ一部を持つ平板状のリードフレーム
、および半導体ペレット３が用意される。次に半導体ペ
レット３がリード部に接着剤６を介して取付けられる。That is, first, a flat lead frame having a frame portion, a lead portion, and a portion of a tie bar disposed between the lead portions, and a semiconductor pellet 3 are prepared. Next, the semiconductor pellet 3 is attached to the lead portion via the adhesive 6.
その後、ワイヤボンディング技術によって、半導体ペレ
ット３のポンディングパッド雪掻とリードとの間にワイ
ヤ５が取付けられる。かかるワイヤボンディングの後、
リードフレームが樹脂モールド用装置のモールド型には
さまれ、樹脂モールドされる。その後、リードフレーム
のフレーム部およびタイバ一部がプレス金型からなるよ
うな切断装置によって切断除去され、かかる切断除去の
後にリード４が図示のように折り曲げられる。Thereafter, a wire 5 is attached between the semiconductor pellet 3's padding pad and the lead by wire bonding technology. After such wire bonding,
The lead frame is sandwiched between molds of a resin molding device and resin molded. Thereafter, the frame portion and part of the tie bars of the lead frame are cut and removed by a cutting device such as a press die, and after such cutting and removal, the leads 4 are bent as shown.
前記半導体ペレット３とリード４との関係を第２図に示
すように、リード４は半導体ペレット３の裏面に沿って
パッケージ１の内部を引き回され、その先端を半導体ペ
レット３の先端部を越えたパッケージ部まで延長され、
該先端部でワイヤボンディングが行われている。As the relationship between the semiconductor pellet 3 and the leads 4 is shown in FIG. extended to the package part,
Wire bonding is performed at the tip.
本実施例１に示すように、半導体ペレット３をその裏面
部をリード４に接合して搭載させることができるのは、
該半導体ペレット３の裏面に絶縁膜２が被着されている
ためである。したがって、本実施例１に示す半導体ペレ
ット３を用いれば、リード４の形成領域を拡張すること
ができ、かつ該リード４の合理的配設が可能となる。そ
の結果、搭載する半導体ペレット３を大きくすることが
でき、そのパッケージｌに占める半導体ペレットの割合
である実装密度を増大させることができるものである。As shown in the first embodiment, the semiconductor pellet 3 can be mounted with its back side joined to the leads 4 because
This is because the insulating film 2 is adhered to the back surface of the semiconductor pellet 3. Therefore, by using the semiconductor pellet 3 shown in Example 1, the area in which the leads 4 are formed can be expanded, and the leads 4 can be arranged rationally. As a result, the size of the semiconductor pellet 3 to be mounted can be increased, and the packaging density, which is the ratio of the semiconductor pellet to the package l, can be increased.
なお、半導体ペレット３の絶縁膜２は、半導体ペレット
の製造工程において、常法に基づいて容易に形成できる
。特に、半導体基板がシリコン（Ｓｉ）である場合には
、該基板を直接酸化することによっても形成できる。Note that the insulating film 2 of the semiconductor pellet 3 can be easily formed based on a conventional method in the semiconductor pellet manufacturing process. In particular, when the semiconductor substrate is silicon (Si), it can also be formed by directly oxidizing the substrate.
〔実施例２〕
第３図は本発明による実施例２である半導体装置を示す
概略断面図である。[Embodiment 2] FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to Embodiment 2 of the present invention.
本実施例２の半導体”Ａ’ｌｌは、セラミックパッケー
ジからなる、いわゆるピングリッドアレイ型半導体装置
である。すなわち、そのパンケージはアルミナ（Ａｌ□
０３）からなる基板７と該基板７０周縁部に低融点ガラ
ス８を介して接合された、断面がコ字状のアルミナから
なるキャップ９で構成されている。The semiconductor "A'll" in Example 2 is a so-called pin grid array type semiconductor device made of a ceramic package. That is, the pan cage is made of alumina (Al□
03) and a cap 9 made of alumina and having a U-shaped cross section and bonded to the peripheral edge of the substrate 70 via a low melting point glass 8.
上記基板７の裏面には外部端子であるビン１０が限ろう
（図示せず）で取付けられており、その上面には該基板
７を貫通するスルーホール配線１１を介して上記ビン１
０と電気的に接続されている表層配線１２が形成されて
いる。また、上記基板７の上には、複数の半導体ペレッ
ト３がそのバンプ電極１３を介してフェイスダウンボン
ディングされた大形の半導体ペレットであるマザーチッ
プ１４がシリコーン系の接着剤６を介して接合されてい
る。そして、マザーチップ１４と表層配線１２とはワイ
ヤ５を介して電気的に接続されている。A vial 10, which is an external terminal, is attached to the back surface of the substrate 7 with a fitting (not shown), and the vial 10 is connected to the upper surface of the substrate 7 via a through-hole wiring 11 penetrating the substrate 7.
A surface layer wiring 12 electrically connected to 0 is formed. Further, on the substrate 7, a mother chip 14, which is a large semiconductor pellet in which a plurality of semiconductor pellets 3 are face-down bonded via their bump electrodes 13, is bonded via a silicone adhesive 6. ing. The mother chip 14 and the surface wiring 12 are electrically connected via wires 5.
本実施例２においては、マザーチップ１４の裏面に二酸
化ケイ素からなる絶縁膜２が形成されており、それ故に
前記実施例１の場合と同様に表層配線１２の上に接合で
きるものである。In the second embodiment, the insulating film 2 made of silicon dioxide is formed on the back surface of the mother chip 14, so that it can be bonded onto the surface wiring 12 as in the first embodiment.
もし、マザーチップ１４の裏面に絶縁膜２がない場合に
は、表層配ｖＡ１２の上には接合できない。If there is no insulating film 2 on the back surface of the mother chip 14, it cannot be bonded onto the surface layer wiring A12.
したがって、マザーチップ１４の下方に位置するビン１
０については基板７の内部を配線を引き回し、該マザー
チップ１４の周囲に引き出す必要があり、それだけ複雑
になる。Therefore, the bin 1 located below the mother chip 14
For 0, it is necessary to route wiring inside the substrate 7 and around the mother chip 14, which increases the complexity accordingly.
ところが、本実施例２では、前記のように、マザーチッ
プ１４の下の基板部にも表層配線１２を形成できること
により、表層配線１２を合理的に配設することが可能と
なるものである。However, in the second embodiment, as described above, the surface layer wiring 12 can also be formed on the substrate portion below the mother chip 14, so that the surface layer wiring 12 can be arranged rationally.
したがって、マザーチップ１４の周囲に形成する表層配
線を減らすことができ、搭載するマザーチップ１４を、
さらに大形化することも可能となる。Therefore, the surface wiring formed around the mother chip 14 can be reduced, and the mother chip 14 to be mounted can be
It is also possible to make it even larger.
（１）、半導体ペレットの裏面に絶縁膜を設けることに
より、該半導体ペレットの裏面を配線に直接接触させる
。ことが可能となるため、半導体ペレットの下のパッケ
ージ部にも配線を形成することが可能となる。(1) By providing an insulating film on the back surface of the semiconductor pellet, the back surface of the semiconductor pellet is brought into direct contact with the wiring. Therefore, it becomes possible to form wiring also in the package section under the semiconductor pellet.
（２）、前記（１１により、配線形成領域を拡張するこ
とができるので、配線形成の自由度が増し、合理的配線
形成が可能となる。(2) According to (11) above, the wiring formation area can be expanded, so the degree of freedom in wiring formation increases, and rational wiring formation becomes possible.
（３）−前記＋２１により、パッケージにおける半導体
ペレット実装密度を向上することができる。(3) - The above +21 allows the semiconductor pellet packaging density in the package to be improved.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、半導体ペレットの裏面に形成する絶縁膜とし
ては二酸化ケイ素からなるものについて説明したが、窒
化ケイ素（ＳｉｚＮ−）等の他の無機系材料からなるも
のであっても、またポリイミド樹脂等の有機系材料から
なるものであってもよい。For example, although the insulating film formed on the back surface of the semiconductor pellet is made of silicon dioxide, it may be made of other inorganic materials such as silicon nitride (SizN-), or it may be made of organic material such as polyimide resin. It may also be made of other materials.
また、実施例１に示したパンケージ内部のリードの形状
は、図示したものに限るものでなく、電気的接続が可能
でかつ半導体ペレットの接合が可能な形状であれば、如
何なるものであってもよい。Furthermore, the shape of the leads inside the pan cage shown in Example 1 is not limited to the one shown in the drawings, but may be of any shape as long as it allows electrical connection and bonding of semiconductor pellets. good.
なお、半導体ペレットの接合に使用する接着剤としてエ
ポキシ系およびシリコーン系接着剤の２例を示したが、
導電性、非導電性を問わず、種々の接着剤を使用するこ
とができるものである。In addition, although two examples of adhesives used for bonding semiconductor pellets, epoxy-based and silicone-based adhesives, are shown,
Various adhesives can be used, regardless of whether they are conductive or non-conductive.
さらに、実施例２においては、本発明による技術をマザ
ーチップに適用したものを示したが、回路が形成された
通常の半導体ペレットに適用してもよい。Further, in Example 2, the technique according to the present invention was applied to a mother chip, but it may also be applied to a normal semiconductor pellet on which a circuit is formed.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である、いわゆるＤＩＰ型
の樹脂封止型半導体装置およびセラミックパッケージか
らなるピングリッドアレイ型半導体装置に適用した場合
について説明したが、それに限定されるものではなく、
たとえば、パッケージ形成材料はもとより、パッケージ
の形式に関係なくあらゆる半導体装置に適用することが
できる技術である。The above explanation mainly describes the case where the invention made by the present inventor is applied to the field of application which is the background of the invention, which is a so-called DIP type resin-sealed semiconductor device and a pin grid array type semiconductor device made of a ceramic package. However, it is not limited to
For example, it is a technique that can be applied not only to package forming materials but also to all semiconductor devices regardless of package format.
第１図は本発明による実施例１である半導体装置の概略
を示す第２図におけるｉｌ断面図、第２図は上記半導体
装置の半導体ペレットとす−ドとの関係を示す概略説明
図、
第３図は本発明による実施例２である半導体装置を示す
概略断面図である。
ｌ・・・パッケージ、２・・・絶縁膜、２ａ・・・電極
パッド、３・・・半導体ペレット、４・・ ・リード、
４ａ・・・外部リード、５・・・ワイヤ、６・・・接着
剤、７・・・基板、８・・・低融点ガラス、９・・・キ
ャンプ、１０・・・ピン、ｌｌ・・・スルーホール配線
、１２・・・表層配線、１３・・・バンプ電極、１４・
・・マザーチップ。
第 １ 図
第 ２ 図1 is a cross-sectional view of FIG. 2 schematically showing a semiconductor device according to a first embodiment of the present invention; FIG. FIG. 3 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. l... Package, 2... Insulating film, 2a... Electrode pad, 3... Semiconductor pellet, 4... Lead,
4a... External lead, 5... Wire, 6... Adhesive, 7... Substrate, 8... Low melting point glass, 9... Camp, 10... Pin, ll... Through-hole wiring, 12... Surface wiring, 13... Bump electrode, 14.
...Mother chip. Figure 1 Figure 2
Claims (1)
されてなる半導体装置。 ２、半導体ペレットが、その裏面を外部端子に接合して
搭載されていることを特徴とする特許請求の範囲第１項
記載の半導体装置。 ３、半導体ペレットがマザーチップであることを特徴と
する特許請求の範囲第１項記載の半導体装置。[Claims] 1. A semiconductor device including a semiconductor pellet having an insulating film formed on its back surface. 2. The semiconductor device according to claim 1, wherein the semiconductor pellet is mounted with its back surface joined to an external terminal. 3. The semiconductor device according to claim 1, wherein the semiconductor pellet is a mother chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60292664A JPS62154769A (en) | 1985-12-27 | 1985-12-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60292664A JPS62154769A (en) | 1985-12-27 | 1985-12-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62154769A true JPS62154769A (en) | 1987-07-09 |
Family
ID=17784703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60292664A Pending JPS62154769A (en) | 1985-12-27 | 1985-12-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62154769A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4989068A (en) * | 1988-02-12 | 1991-01-29 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| US5122860A (en) * | 1987-08-26 | 1992-06-16 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit device and manufacturing method thereof |
| EP0510905A1 (en) * | 1991-04-22 | 1992-10-28 | Motorola, Inc. | Semiconductor package which does not delaminate or crack |
| USRE36097E (en) * | 1991-11-14 | 1999-02-16 | Lg Semicon, Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| GB2508633A (en) * | 2012-11-29 | 2014-06-11 | Cambridge Silicon Radio Ltd | Die package |
-
1985
- 1985-12-27 JP JP60292664A patent/JPS62154769A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5122860A (en) * | 1987-08-26 | 1992-06-16 | Matsushita Electric Industrial Co., Ltd. | Integrated circuit device and manufacturing method thereof |
| US4989068A (en) * | 1988-02-12 | 1991-01-29 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| EP0510905A1 (en) * | 1991-04-22 | 1992-10-28 | Motorola, Inc. | Semiconductor package which does not delaminate or crack |
| USRE36097E (en) * | 1991-11-14 | 1999-02-16 | Lg Semicon, Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| USRE37413E1 (en) | 1991-11-14 | 2001-10-16 | Hyundai Electronics Industries Co., Ltd. | Semiconductor package for a semiconductor chip having centrally located bottom bond pads |
| GB2508633A (en) * | 2012-11-29 | 2014-06-11 | Cambridge Silicon Radio Ltd | Die package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3420057B2 (en) | Resin-sealed semiconductor device | |
| US6911353B2 (en) | Semiconductor device and method of manufacturing same | |
| US6703696B2 (en) | Semiconductor package | |
| US5468993A (en) | Semiconductor device with polygonal shaped die pad | |
| JP2001313363A (en) | Resin-encapsulated semiconductor device | |
| JPH0350758A (en) | Resin seal type semiconductor device | |
| JP4408475B2 (en) | Semiconductor devices that do not use bonding wires | |
| JP2000294715A (en) | Semiconductor device and manufacture thereof | |
| JPS60167454A (en) | Semiconductor device | |
| WO2007018473A1 (en) | Leadframe and semiconductor package | |
| JPS62154769A (en) | Semiconductor device | |
| EP0415106B1 (en) | Lead frames for semiconductor device | |
| JP2539763B2 (en) | Semiconductor device mounting method | |
| JP2756436B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4162303B2 (en) | Manufacturing method of semiconductor device | |
| KR0152902B1 (en) | Structure of bottom lead package and method for manufacturing the same | |
| JPS61241954A (en) | Semiconductor device | |
| JP3938525B2 (en) | Manufacturing method of semiconductor device | |
| KR100290783B1 (en) | Semiconductor package | |
| JP4569048B2 (en) | Surface mount semiconductor package and manufacturing method thereof | |
| KR200169976Y1 (en) | Semiconductor package | |
| JPH02202042A (en) | Resin-sealed semiconductor device | |
| KR100252862B1 (en) | Semiconductor package and method for fabricating the same | |
| KR100370480B1 (en) | Lead frame for semiconductor package | |
| JP2577880B2 (en) | Semiconductor device |