JP2007281509A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007281509A
JP2007281509A JP2007158205A JP2007158205A JP2007281509A JP 2007281509 A JP2007281509 A JP 2007281509A JP 2007158205 A JP2007158205 A JP 2007158205A JP 2007158205 A JP2007158205 A JP 2007158205A JP 2007281509 A JP2007281509 A JP 2007281509A
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JP
Japan
Prior art keywords
electrode
electrode pad
wire
semiconductor chip
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007158205A
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Japanese (ja)
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JP4642047B2 (en
Inventor
Makoto Tsubonoya
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Publication date
Application filed by Kanto Sanyo Semiconductors Co Ltd, Sanyo Electric Co Ltd filed Critical Kanto Sanyo Semiconductors Co Ltd
Priority to JP2007158205A priority Critical patent/JP4642047B2/en
Publication of JP2007281509A publication Critical patent/JP2007281509A/en
Application granted granted Critical
Publication of JP4642047B2 publication Critical patent/JP4642047B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for preventing an increase of a chip area without enlarging a formation area of a desired electrode pad or without increasing the number of electrode pads, even if electrode pads of different current capacities to be transferred with an outside are formed. <P>SOLUTION: Fining of a metallic fine line is realized with reference to an electrode pad of a small current capacity to be transferred with an outside. Connection is performed for an electrode pad 1 of an IC chip 2 by a metallic fine line 5 of the same diameter. Meanwhile, in the electrode pad 1 for transferring a large current capacity with an outside, a bump electrode 13 is formed and a plurality of metallic fine lines 5 are connected. Consequently, a large current capacity can be transferred, and both a manufacturing cost and a chip area can be reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明の半導体装置は、種々の電流を授受する電極パッドが複数形成された半導体素子において、同一径のボンディングワイヤーにより、全ての電極パッドに対し電気的に接続する技術に関する。   The semiconductor device of the present invention relates to a technique for electrically connecting all electrode pads with bonding wires having the same diameter in a semiconductor element in which a plurality of electrode pads for transmitting and receiving various currents are formed.

例えば、ＬＳＩへの電源電圧の供給は、半導体チップ上に設けた電極パッドとリード端子とをボンディングワイヤにより接続することで行っている。また、同様に、半導体チップ上に形成されたその他の電極パッドもその他のリード端子とボンディングワイヤにより接続している。   For example, power supply voltage is supplied to an LSI by connecting an electrode pad provided on a semiconductor chip and a lead terminal by a bonding wire. Similarly, other electrode pads formed on the semiconductor chip are also connected to other lead terminals by bonding wires.

従来の電力用半導体装置では、中でもチップの表面電極と外部電極との接続方法としてはワイヤボンディング法がある。そして、例えば、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ−Ｇａｔｅ−Ｂｉｐｏｌａｒ−Ｔｒａｎｓｉｓｔｏｒ）チップ上には、エミッタ電極とゲート電極が形成されている。そして、それぞれの電極パッドとリードとが金属細線により接続されている。このとき、大電流を授受するエミッタ電極は多数形成されたり、個々のエミッタ電極の形成領域を大きくし、金属細線をワイヤボンディングし、対応していた（例えば、特許文献１。）。
特開平５−２０６４４９号公報（第１３−１４頁、第１−３図） In a conventional power semiconductor device, there is a wire bonding method as a connection method between the surface electrode of the chip and the external electrode. For example, an emitter electrode and a gate electrode are formed on an IGBT (Insulated-Gate-Bipolar-Transistor) chip. And each electrode pad and lead | read | reed are connected with the metal fine wire. At this time, a large number of emitter electrodes that transmit and receive a large current are formed, or the formation area of each emitter electrode is enlarged, and a thin metal wire is wire-bonded (for example, Patent Document 1).
JP-A-5-206449 (pages 13-14, Fig. 1-3)

上述したように、従来の半導体装置では、例えば、エミッタ電極等の電極に流れる電流容量に応じて、接続する金属細線の太さを可変したり、または、半導体チップ表面に複数の電極パッドを形成したり、することで対応している。   As described above, in a conventional semiconductor device, for example, the thickness of a thin metal wire to be connected is changed according to the current capacity flowing through an electrode such as an emitter electrode, or a plurality of electrode pads are formed on the surface of a semiconductor chip. It corresponds by doing.

そして、電極パッドの電流容量に応じて金属細線の太さを可変とする場合には、一回のワイヤーボンディング工程で全て電極パッドと接続することが出来ず、ボンディング時間を多大に要し、作業効率は悪く量産性が向上しないという問題があった。また、全ての電極パッドに対し、金属細線の太さを統一する場合には、最大の電流容量を有する電極パッドに対する金属細線の太さに統一する必要がある。そのため、この場合には、金属細線による配線抵抗が大きくなり、電力消費が増加してしまい、半導体特性が悪化するという問題があった。   And, if the thickness of the fine metal wire is made variable according to the current capacity of the electrode pad, it cannot be connected to the electrode pad in a single wire bonding process, requiring a lot of bonding time, There was a problem that efficiency was bad and mass productivity was not improved. Moreover, when unifying the thickness of a metal fine wire with respect to all the electrode pads, it is necessary to unify to the thickness of the metal thin wire with respect to the electrode pad which has the largest current capacity. Therefore, in this case, there is a problem that the wiring resistance due to the fine metal wire is increased, the power consumption is increased, and the semiconductor characteristics are deteriorated.

一方、半導体チップ表面に複数の電極パッドを形成し、対応する場合では、金属細線の太さは、他の電極パッド上に接続する金属細線と同様に細い太さのもので対応できる。しかしながら、半導体チップ表面では、電極パッドを形成するための領域が必要となり、チップ面積を縮小することが困難であるという問題があった。また、電極パッドの形成される任意の半導体チップ表面上でワイヤーボンディングが行われる為、ワイヤーボンディング時の振動等による機械的ストレスにより、シリコン酸化膜等から成る層間絶縁膜にクラックが入るという問題があった。   On the other hand, in the case where a plurality of electrode pads are formed on the surface of the semiconductor chip and corresponding, the thickness of the metal fine wire can be dealt with as thin as the metal thin wire connected on the other electrode pad. However, on the surface of the semiconductor chip, a region for forming an electrode pad is required, and there is a problem that it is difficult to reduce the chip area. In addition, since wire bonding is performed on the surface of any semiconductor chip on which electrode pads are formed, there is a problem in that an interlayer insulating film made of a silicon oxide film or the like cracks due to mechanical stress due to vibration during wire bonding. there were.

上述した従来の課題に鑑みてなされたもので、本発明の半導体装置では、第１に、第１のアイランド上に固着された第１の半導体チップと、前記第１のアイランドと離間して配置された第２のアイランド上に固着された第２の半導体チップと、前記第１のアイランドと前記第２のアイランドを囲むように設けられた複数のリードとを有する半導体装置に於いて、前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第１の半導体チップ側に設けられた複数の第１の電極パッドと、前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第２の半導体チップ側に設けられた第２の電極パッドと、前記第２の電極パッドに設けられたバンプ電極と、前記複数の第１の電極パッドの一つ目と前記バンプ電極とを接続する第１のボンディングワイヤと、前記複数の第１の電極パッドの二つ目と前記バンプ電極とを接続する第２のボンディングワイヤとを有する事で解決するものである。
第２に、前記第２の電極パッドは、Ｖｃｃ用またはＧＮＤ用のパッドであることで解決するものである。
第３に、第１のアイランド上に固着された第１の半導体チップと、前記第１のアイランドと離間して配置された第２のアイランド上に固着された第２の半導体チップと、前記第１のアイランドと前記第２のアイランドを囲むように設けられた複数のリードとを有する半導体装置に於いて、前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第１の半導体チップ側に設けられた複数の第１の電極パッドと、前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第２の半導体チップ側に設けられた第２の電極パッドと、前記第２の電極パッドに設けられたバンプ電極と、前記複数の第１の電極パッドの一つ目と前記バンプ電極とを接続する第１のボンディングワイヤと、前記複数の第１の電極パッドの二つ目と前記バンプ電極とを接続する第２のボンディングワイヤとを有し、前記バンプ電極側の前記第１のボンディングワイヤおよび前記第２のボンディングワイヤの付け根は、前記バンプ電極を形成する際に設けられる凸部の上を避けて設けられる事で解決するもので有る。
第４に、前記ボンディングワイヤの前記バンプ電極側は、スティッチボンドで形成されることで解決するものである。 In view of the above-described conventional problems, in the semiconductor device of the present invention, first, the first semiconductor chip fixed on the first island and the first island are arranged apart from the first island. A semiconductor device having a second semiconductor chip fixed on the second island and a plurality of leads provided to surround the first island and the second island; A plurality of first electrode pads located on opposite sides of the first semiconductor chip and the second semiconductor chip, provided on the first semiconductor chip side, the first semiconductor chip and the first semiconductor chip; A second electrode pad provided on the side opposite to the second semiconductor chip, provided on the second semiconductor chip side, a bump electrode provided on the second electrode pad, and the plurality of second electrodes 1st electrode pad of 1 A first bonding wire for connecting the bump electrode, solves by having a second bonding wire for connecting the second and the bump electrodes of the plurality of first electrode pads.
Second, the second electrode pad can be solved by being a pad for Vcc or GND.
Third, a first semiconductor chip fixed on the first island, a second semiconductor chip fixed on a second island spaced apart from the first island, and the first In a semiconductor device having one island and a plurality of leads provided so as to surround the second island, the semiconductor device is located on opposite sides of the first semiconductor chip and the second semiconductor chip. A plurality of first electrode pads provided on the first semiconductor chip side, and a side of the first semiconductor chip and the second semiconductor chip facing each other, the second semiconductor chip A second electrode pad provided on the side, a bump electrode provided on the second electrode pad, and a first bonding for connecting the first of the plurality of first electrode pads and the bump electrode Wire and said plurality A second bonding wire connecting the second electrode pad and the bump electrode, and the base of the first bonding wire and the second bonding wire on the bump electrode side is the bump The problem can be solved by avoiding the projections provided when the electrodes are formed.
Fourth, the bump wire side of the bonding wire is solved by being formed by stitch bonding.

第１に、本発明の半導体装置では、ＩＣチップの電極パッド上に形成されたバンプ電極に対し、少なくとも２本以上の金属細線を接続することができる。そのことで、外部と授受する電流容量が大きい電極パッドでは、複数本の金属細線を接続し、外部と授受する電流容量が小さい電極パッドでは、１本の金属細線を接続する。その結果、外部と授受する電流容量が小さい電極パッドを基準とし、金属細線の径を選択することができるので、金属細線の配線抵抗の低減を実現することができる。   First, in the semiconductor device of the present invention, at least two or more fine metal wires can be connected to the bump electrodes formed on the electrode pads of the IC chip. Therefore, a plurality of fine metal wires are connected to an electrode pad having a large current capacity to be exchanged with the outside, and a single fine metal wire is connected to an electrode pad having a small current capacity to be exchanged with the outside. As a result, the diameter of the fine metal wire can be selected on the basis of the electrode pad having a small current capacity to be exchanged with the outside, so that the wiring resistance of the fine metal wire can be reduced.

第２に、本発明の半導体装置では、外部と授受する電流容量が小さい電極パッドを基準とし、金属細線の径を選択することができる。そのことで、ＩＣチップ上の全ての電極パッドに対し、細い径の金属細線でワイヤーボンディングを行うことができる。その結果、金属細線のコストを低減でき、且つ、細い径の金属細線であるが、大きい電流容量を外部と授受することができる。   Secondly, in the semiconductor device of the present invention, the diameter of the thin metal wire can be selected with reference to an electrode pad having a small current capacity to and from the outside. As a result, it is possible to perform wire bonding to all electrode pads on the IC chip with thin metal wires having a small diameter. As a result, the cost of the fine metal wires can be reduced, and the thin metal wires can be exchanged with a large current capacity.

第３に、本発明の半導体装置の製造方法では、外部と授受する電流容量が小さい電極パッドを基準とし、金属細線の径を選択し、その径の金属細線でＩＣ上の所望の電極パッドに対し、ワイヤーボンディングを行う。そのことで、同一径の金属細線を用いることで、１回のワイヤーボンディング工程で、種々の電流容量を外部と授受する電極パッドに金属細線を接続することができる。その結果、製造コストを低減し、製造時間の短縮を実現することができる。   Thirdly, in the method of manufacturing a semiconductor device according to the present invention, the diameter of a fine metal wire is selected based on an electrode pad having a small current capacity to be exchanged with the outside, and the desired fine electrode pad on the IC is formed with the fine metal wire of that diameter. On the other hand, wire bonding is performed. Thus, by using the fine metal wires having the same diameter, the fine metal wires can be connected to the electrode pads that exchange various current capacities with the outside in one wire bonding step. As a result, the manufacturing cost can be reduced and the manufacturing time can be shortened.

以下に、本発明における半導体装置およびその製造方法において、図１〜図５を参照として説明する。特に、ＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔｓ）チップの電極パッド上における金属細線の接続構造及びその製造方法について説明する。図１（Ａ）はＩＣチップの電極パッドとリードとを金属細線を介して接続する状況を説明する平面図であり、図１（Ｂ）はＩＣチップの電極パッド間を金属細線を介して接続する状況を説明する平面図であり、図２（Ａ）及び（Ｂ）はＩＣチップの電極パッド上の金属細線の接続状況を説明する平面図であり、図３（Ａ）及び（Ｂ）はＩＣチップの電極パッド間の接続状況を説明する図である。   Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS. In particular, a connection structure of metal thin wires on an electrode pad of an IC (Integrated Circuits) chip and a manufacturing method thereof will be described. FIG. 1A is a plan view for explaining a situation in which the electrode pads and leads of the IC chip are connected through the fine metal wires, and FIG. 1B is a connection between the electrode pads of the IC chips through the fine metal wires 2 (A) and 2 (B) are plan views for explaining the connection state of the fine metal wires on the electrode pads of the IC chip, and FIGS. 3 (A) and 3 (B) are diagrams. It is a figure explaining the connection condition between the electrode pads of an IC chip.

図１（Ａ）に示す本実施の形態では、表面に複数の電極パッド１が形成されているＩＣチップ２が、例えば、リードフレームに形成されたアイランド３上に、例えば、Ａｇペースト等の導電ペーストを介して固着されている。また、リードフレームには、アイランド３の周囲を囲むように複数のリード４が形成されている。そして、ＩＣチップ２の電極パッド部１とリード４とは、それぞれ金属細線５を介して電気的に接続している。尚、本実施の形態では、リードフレームは、例えば、銅を主材料とするフレームから成る。しかし、リードフレームの材料としては、Ｆｅ−Ｎｉを主材料としても良いし、他の金属材料でも良い。また、リードフレームを用いる場合に、特に、限定する必要はなく、プリント基板、導電箔を所望のパターンに加工した場合でも良い。   In this embodiment shown in FIG. 1A, an IC chip 2 having a plurality of electrode pads 1 formed on a surface thereof is electrically conductive, for example, Ag paste on an island 3 formed on a lead frame. It is fixed via paste. The lead frame is formed with a plurality of leads 4 so as to surround the island 3. The electrode pad portion 1 and the lead 4 of the IC chip 2 are electrically connected to each other through a fine metal wire 5. In the present embodiment, the lead frame is made of a frame mainly made of copper, for example. However, the lead frame material may be Fe-Ni as the main material or other metal material. In the case of using a lead frame, there is no particular limitation, and the printed board and conductive foil may be processed into a desired pattern.

また、図１（Ｂ）に示す本実施の形態では、例えば、リードフレームに第１のアイランド６と第２のアイランド７とが多少離間して連続して形成されている。そして、第１及び第２のアイランド６、７上には、それぞれＩＣチップ８、９が例えば、Ａｇペースト等の導電ペーストを介して固着されている。また、リードフレームには、第１及び第２のアイランド６、７の周囲を囲むように複数のリード１１が形成されている。そして、ＩＣチップ８、９の電極パッド部１０、１５とリード１１とは、それぞれ金属細線１２を介して電気的に接続している。また、本実施の形態では、ＩＣチップ８、９の相対峙する側辺の近傍領域に形成された電極パッド１０、１５間は、直接、金属細線１２を介して電気的に接続している。尚、本実施の形態においても、同様に、リードフレームの材料としては、銅を主材料とするフレームに限定する必要はなく、Ｆｅ−Ｎｉを主材料としても良いし、他の金属材料でも良い。また、リードフレームを用いる場合に、特に、限定する必要はなく、プリント基板、導電箔を所望のパターンに加工した場合でも良い。   Further, in the present embodiment shown in FIG. 1B, for example, the first island 6 and the second island 7 are continuously formed on the lead frame with some separation. Then, IC chips 8 and 9 are fixed on the first and second islands 6 and 7 via conductive paste such as Ag paste, for example. The lead frame is formed with a plurality of leads 11 so as to surround the first and second islands 6 and 7. The electrode pad portions 10 and 15 of the IC chips 8 and 9 and the leads 11 are electrically connected to each other through thin metal wires 12. Further, in the present embodiment, the electrode pads 10 and 15 formed in the vicinity of the opposite sides of the IC chips 8 and 9 are electrically connected directly via the fine metal wires 12. Also in the present embodiment, similarly, the material of the lead frame is not necessarily limited to the frame mainly made of copper, Fe-Ni may be used as the main material, and other metal materials may be used. . In the case of using a lead frame, there is no particular limitation, and the printed board and conductive foil may be processed into a desired pattern.

また、図示の如く、金属細線の一端に示す丸印はボールボンディングが行われる側を示している。そして、金属細線の他端がＩＣチップの電極パッドと接続する場合には、図示していないが、電極パッド上にはバンプ電極１３（図２参照）が形成されている。   Further, as shown in the figure, a circle at one end of the fine metal wire indicates the side on which ball bonding is performed. When the other end of the fine metal wire is connected to the electrode pad of the IC chip, the bump electrode 13 (see FIG. 2) is formed on the electrode pad, although not shown.

図２（Ａ）及び（Ｂ）に示すように、本実施の形態では、ＩＣチップ２の電極パッド１上にバンプ電極１３形成した後、そのバンプ電極１３に対し複数の金属細線５がステッチボンディングにより接続されている。つまり、本実施の形態では、図１（Ａ）に示すように、電極パッド１とリード４とを金属細線５を介して接続する際には、リード４側はボールボンディングにより接続し、電極パッド１側はステッチボンディングにより接続している。一方、図１（Ｂ）に示すように、電極パッド１０、１５間を金属細線１２を介して接続する際には、一方の電極パッド１０上にはバンプ電極１３を形成する。そして、バンプ電極１３を形成しない他方の電極パッド１０側はボールボンディングにより接続し、バンプ電極１３を形成した電極パッド１０側はステッチボンディングにより接続している。   As shown in FIGS. 2A and 2B, in the present embodiment, after the bump electrode 13 is formed on the electrode pad 1 of the IC chip 2, a plurality of fine metal wires 5 are stitch bonded to the bump electrode 13. Connected by. That is, in the present embodiment, as shown in FIG. 1A, when the electrode pad 1 and the lead 4 are connected through the fine metal wire 5, the lead 4 side is connected by ball bonding, and the electrode pad is connected. One side is connected by stitch bonding. On the other hand, as shown in FIG. 1B, when the electrode pads 10 and 15 are connected via the fine metal wire 12, the bump electrode 13 is formed on the one electrode pad 10. The other electrode pad 10 side where the bump electrode 13 is not formed is connected by ball bonding, and the electrode pad 10 side where the bump electrode 13 is formed is connected by stitch bonding.

通常、金属細線を接続するワイヤボンディングは、一端はボールボンディングにより接続し、他端はステッチボンディングにより接続する。そして、ステッチボンディングが行われる側では、金属細線をキャピラリーで強く押さえ、力で引きちぎるため、ステッチボンディングされた領域にはストレスが加わる。特に、ＩＣチップの電極パッド上で、直接、ステッチボンディングが行われると、その衝撃により、電極パッドの下部に位置するシリコン酸化膜等から成る層間絶縁膜にクラックが入るという問題があった。しかしながら、本実施の形態における構造では、衝撃が大きいステッチボンディングは、バンプ電極１３上で行うことができる。そのことで、本実施の形態では、上述したＩＣチップの層間絶縁膜の破壊を抑制することができ、リードのステッチボンディングによる損傷も抑制することができる。   Usually, in wire bonding for connecting fine metal wires, one end is connected by ball bonding and the other end is connected by stitch bonding. On the side where the stitch bonding is performed, the metal thin wire is strongly pressed by the capillary and is torn off by force, so that stress is applied to the stitch bonded region. In particular, when stitch bonding is performed directly on an electrode pad of an IC chip, there is a problem that an interlayer insulating film made of a silicon oxide film or the like located under the electrode pad cracks due to the impact. However, in the structure in the present embodiment, stitch bonding with a large impact can be performed on the bump electrode 13. As a result, in this embodiment, the above-described breakdown of the interlayer insulating film of the IC chip can be suppressed, and damage due to lead stitch bonding can also be suppressed.

そして、本実施の形態では、バンプ電極１３が形成された１つの電極パッドに対し、少なくとも２本以上の金属細線５を接続することで、金属細線５として細い径のものを使用することができる。図１（Ａ）及び（Ｂ）に示すように、ＩＣチップ２、８、９上には、それぞれ複数の電極パッド１、１０、１５が形成されている。そして、電極パッド１、１０、１５は、ＩＣチップ２、８、９内に形成された抵抗体、コンデンサー、トランジスタ等の多数の素子に対し電流の授受を行っている。そのため、それぞれの電極パッド１、１０、１５では、目的に応じて外部と授受する電流容量が異なる。例えば、Ｖｃｃ（電源電極）用の電極パッド、ＧＮＤ（接地電極）用の電極パッドでは、外部と授受する電流容量は大きいため、接続される金属細線の径は、他の電極パッドと接続されるものよりも太くする必要がある。   And in this Embodiment, the thing of a thin diameter can be used as the metal fine wire 5 by connecting at least 2 or more metal fine wire 5 with respect to one electrode pad in which the bump electrode 13 was formed. . As shown in FIGS. 1A and 1B, a plurality of electrode pads 1, 10, and 15 are formed on the IC chips 2, 8, and 9, respectively. The electrode pads 1, 10 and 15 send and receive current to a number of elements such as resistors, capacitors and transistors formed in the IC chips 2, 8 and 9. Therefore, each electrode pad 1, 10, 15 has a different current capacity to be exchanged with the outside depending on the purpose. For example, an electrode pad for Vcc (power supply electrode) and an electrode pad for GND (ground electrode) have a large current capacity to be exchanged with the outside. Therefore, the diameter of the thin metal wire to be connected is connected to other electrode pads. It needs to be thicker than things.

ここで、通常、ＩＣチップ２の電極パッド１とリード４とを金属細線５を介して接続する場合、製造工程上１回のワイヤーボンディング工程で行われる。そのため、１回のワイヤーボンディング工程において、ＩＣチップ２の電極パッド１とリード４とを接続するためには、最も大きい電流を授受する電極パッドにあわせて、金属細線の径を決める必要がある。この場合では、その他大部分である小さい電流を授受する電極パッドにおいても、同様に必要以上の太い径である金属細線により接続される。例えば、接続される金属細線の径がφ２５μｍで十分である電極パッドに対しても、φ３８μｍの径の金属細線を接続しなければならない。この構造では、径の太い金属細線を用いることで、金属細線の配線抵抗が大きく、消費電力が大きくなり、電力コストの低減を図ることができない。また、金属細線のコストの低減も図ることができない。   Here, normally, when the electrode pad 1 of the IC chip 2 and the lead 4 are connected via the fine metal wire 5, it is performed in one wire bonding step in the manufacturing process. Therefore, in order to connect the electrode pad 1 of the IC chip 2 and the lead 4 in one wire bonding step, it is necessary to determine the diameter of the fine metal wire in accordance with the electrode pad that receives and receives the largest current. In this case, the electrode pads that exchange a small amount of current, which is the majority, are similarly connected by a thin metal wire having a larger diameter than necessary. For example, a metal thin wire having a diameter of φ38 μm must be connected to an electrode pad in which the diameter of the metal thin wire to be connected is sufficient to be φ25 μm. In this structure, by using a metal fine wire having a large diameter, the wiring resistance of the metal fine wire is large, the power consumption is large, and the power cost cannot be reduced. In addition, the cost of the fine metal wires cannot be reduced.

一方、それぞれの電極パッドの授受する電流容量にあわせて、最適の径の金属細線を接続する場合には、１枚のＩＣチップ２に対し、複数回のワイヤーボンディング工程が必要となる。そのため、この構造の場合には、製造コストの低減を図ることが出来ず、また、製造時間の低減も図ることが出来ない。   On the other hand, when a thin metal wire having an optimum diameter is connected in accordance with the current capacity transferred by each electrode pad, a plurality of wire bonding steps are required for one IC chip 2. Therefore, in the case of this structure, the manufacturing cost cannot be reduced, and the manufacturing time cannot be reduced.

しかしながら、本実施の形態の半導体装置では、外部と授受する電流容量が大きい等の所望の電極パッドでは、その電極パッドに形成されたバンプ電極１３に対し、複数本の金属細線５を接続することができる。そして、ＩＣチップ２の表面に形成される複数の電極パッド１の大部分は、Ｖｃｃ用の電極パッド、ＧＮＤ用の電極パッドより細い径の金属細線で所望の目的を達成することができる。そのため、本実施の形態では、外部と授受する電流容量の小さい電極パッドを基準とし、金属細線の径を選択することが出来る。そして、選択したその径の金属細線により、ＩＣチップ２上の電極パッド１に対し、１回のワイヤーボンディング工程で金属細線５を接続することができる。   However, in the semiconductor device of the present embodiment, a plurality of fine metal wires 5 are connected to the bump electrode 13 formed on the electrode pad in a desired electrode pad having a large current capacity to be exchanged with the outside. Can do. Most of the plurality of electrode pads 1 formed on the surface of the IC chip 2 can achieve a desired purpose with a fine metal wire having a diameter smaller than that of the Vcc electrode pad and the GND electrode pad. Therefore, in the present embodiment, the diameter of the fine metal wire can be selected with reference to an electrode pad having a small current capacity exchanged with the outside. And the metal fine wire 5 can be connected to the electrode pad 1 on the IC chip 2 by a single wire bonding step by the selected metal fine wire of the diameter.

つまり、本実施の形態では、Ｖｃｃ用の電極パッド、ＧＮＤ用の電極パッドでは、電極パッド上のバンプ電極に対し、複数本の金属細線を接続することで、所望の電流容量を外部と授受することができる。そして、その他の電極パッドでは、授受する電流容量に適した径の金属細線により外部と接続させることができる。そのことで、本実施の形態では、外部と授受する電流容量の小さい電極パッドにあわせ金属細線の径を選択できるので、金属細線の配線抵抗を低減した構造を実現することができる。一方、外部と授受する電流容量の大きい電極パッドにおいても、複数本の金属細線により所望の電流容量を確実に授受することができる。   That is, in the present embodiment, in the Vcc electrode pad and the GND electrode pad, a plurality of fine metal wires are connected to the bump electrode on the electrode pad, and a desired current capacity is exchanged with the outside. be able to. The other electrode pads can be connected to the outside by a thin metal wire having a diameter suitable for the current capacity to be exchanged. As a result, in this embodiment, the diameter of the fine metal wire can be selected according to the electrode pad having a small current capacity to be exchanged with the outside, so that a structure with reduced wiring resistance of the fine metal wire can be realized. On the other hand, even in an electrode pad having a large current capacity to be exchanged with the outside, a desired current capacity can be reliably exchanged with a plurality of thin metal wires.

また、本実施の形態では、外部と授受する電流容量の大きい電極パッドでは、
１つの電極パッドで複数本の金属細線を接続することができるので、電極パッドの形成面積を統一して形成することができる。つまり、外部と授受する電流容量の大小によらず、電極パッドの形成面積を統一することができる。また、外部と授受する電流容量の大きい場合にも、形成する電極パッドの数を必要最低限の数とすることができる。そのことで、ＩＣチップサイズの低減も実現することができる。 In the present embodiment, in the electrode pad having a large current capacity to be exchanged with the outside,
Since a plurality of fine metal wires can be connected by one electrode pad, the formation area of the electrode pad can be unified. That is, the formation area of the electrode pad can be unified regardless of the size of the current capacity exchanged with the outside. Further, even when the current capacity to be exchanged with the outside is large, the number of electrode pads to be formed can be reduced to the minimum necessary number. As a result, a reduction in IC chip size can also be realized.

更に、本実施の形態では、図２（Ａ）及び（Ｂ）に示すように、例えば、電極パッド１上のバンプ電極１３に対し、２本の金属細線５をステッチボンディングにより接続する。このとき、図２（Ａ）に示すように、１本目の金属細線と２本目の金属細線の端部が一部重なっても良いが、離間して接続する。具体的には、金属細線５がバンプ電極１３と接続する付け根部分５１において、少なくとも１本目と２本目の金属細線５が重ならないように接続する。一方、図２（Ｂ）では、１本目と２本目の金属細線５が、１本目の金属細線５がバンプ電極１３と接続する付け根部分５１で重なるように接続する場合を示す。この場合には、２本目の金属細線５を接続する際に、金属細線５をキャピラリーで強く押さえ、力で引きちぎる。この際に、既に、接続されている１本目の金属細線５に対し、歪みを生じさせ金属細線５のループの安定性を害する場合がある。   Furthermore, in this embodiment, as shown in FIGS. 2A and 2B, for example, two fine metal wires 5 are connected to the bump electrode 13 on the electrode pad 1 by stitch bonding. At this time, as shown in FIG. 2 (A), the ends of the first fine metal wire and the second fine metal wire may partially overlap, but they are connected apart from each other. Specifically, in the base portion 51 where the fine metal wire 5 is connected to the bump electrode 13, the connection is made so that at least the first and second fine metal wires 5 do not overlap. On the other hand, FIG. 2B shows a case where the first and second fine metal wires 5 are connected so that the first fine metal wires 5 overlap each other at the base portion 51 that connects to the bump electrode 13. In this case, when connecting the second metal thin wire 5, the metal thin wire 5 is strongly pressed with a capillary and is torn off by force. At this time, the first fine metal wire 5 already connected may be distorted to impair the stability of the loop of the fine metal wire 5.

そのため、本実施の形態では、電極パッド１上のバンプ電極１３に対し、２本の金属細線５をステッチボンディングにより接続する際には、図２（Ａ）に示すように、それぞれの金属細線５の付け根部分５１が離間するように接続する。また、バンプ電極１３を形成する際の凸部１４上を避けて、金属細線５をステッチボンディングにより、接続することが望ましい。本実施の形態では、後述する製造方法によりバンプ電極１３を形成し、その製造方法では、バンプ電極１３の凸部１４は安定して形成される。しかし、もし、バンプ電極１３の凸部１４が所望の形状に形成されなかった場合でも、その凸部１４を避けて金属細線５を接続することで、金属細線５を確実に接続でき、且つ金属細線５のループの安定性を実現することができる。尚、金属細線５のループの安定性を実現することができる場合には、図２（Ｂ）に示すように、１本目の金属細線と２本目の金属細線とを重ねて接続しても問題はない。また、バンプ電極上に複数本の金属細線を接続する場合も同様である。   For this reason, in the present embodiment, when the two fine metal wires 5 are connected to the bump electrode 13 on the electrode pad 1 by stitch bonding, as shown in FIG. The base portions 51 are connected so as to be separated from each other. Further, it is desirable to connect the fine metal wires 5 by stitch bonding while avoiding the projections 14 when the bump electrodes 13 are formed. In the present embodiment, the bump electrode 13 is formed by a manufacturing method described later, and in the manufacturing method, the convex portion 14 of the bump electrode 13 is stably formed. However, even if the convex portion 14 of the bump electrode 13 is not formed in a desired shape, by connecting the fine metal wire 5 while avoiding the convex portion 14, the fine metal wire 5 can be reliably connected, and the metal The stability of the loop of the thin wire 5 can be realized. In addition, when the stability of the loop of the fine metal wire 5 can be realized, there is a problem even if the first metal fine wire and the second metal fine wire are overlapped and connected as shown in FIG. There is no. The same applies to the case where a plurality of fine metal wires are connected on the bump electrode.

そして、図３（Ａ）及び（Ｂ）では、図１（Ｂ）においても示すように、ＩＣチップ８、９の電極パッド１０、１５間を、直接、金属細線１２で接続する図を示している。図３（Ａ）では、ＩＣチップ９の電極パッド１５上にバンプ電極１３を形成し、ＩＣチップ８の電極パッド１０上ではボールボンディングを行い、ＩＣチップ９のバンプ電極１３上ではステッチボンディングを行う。そして、ＩＣチップ８とＩＣチップ９との授受する電流容量の等しい電極パッド１０同士を接続している。この際、図３（Ｂ）に示すように、図２（Ａ）及び（Ｂ）を用いて上述した製造方法により金属細線１２を接続することで、金属細線５を確実に接続でき、且つ金属細線５のループの安定性を実現している。尚、ＩＣチップ８、９上では、電極パッド１０、１５に対し、直接、ステッチボンディングを行うことなく、金属細線の接続を行っている。   3A and 3B show a diagram in which the electrode pads 10 and 15 of the IC chips 8 and 9 are directly connected by the fine metal wires 12 as shown in FIG. 1B. Yes. In FIG. 3A, bump electrodes 13 are formed on the electrode pads 15 of the IC chip 9, ball bonding is performed on the electrode pads 10 of the IC chip 8, and stitch bonding is performed on the bump electrodes 13 of the IC chip 9. . The electrode pads 10 having the same current capacity between the IC chip 8 and the IC chip 9 are connected to each other. At this time, as shown in FIG. 3B, by connecting the fine metal wires 12 by the manufacturing method described above with reference to FIGS. 2A and 2B, the fine metal wires 5 can be reliably connected, and the metal The stability of the loop of the thin wire 5 is realized. On the IC chips 8 and 9, the fine metal wires are connected to the electrode pads 10 and 15 without directly performing stitch bonding.

次に、図４及び図５を用いて、電極パッド上にバンプ電極を形成する製造方法について説明する。   Next, a manufacturing method for forming bump electrodes on the electrode pads will be described with reference to FIGS.

先ず、図４（Ａ）に示すように、集積回路網を形成したＩＣチップ２０のアルミ電極パッド２１上方にキャピラリ２２を移動する。キャピラリ２２の中心孔２３には直径が２０〜３０μｍ程度の金ワイヤ２４が挿通されており、キャピラリ２２上方にはワイヤ２４を狭持するためのクランパ２５が配置されている。キャピラリ２２先端部は直径１００μｍ程度の大きさを有する。そして、金ワイヤ２４の先端部にスパーク２６を飛ばしてこれを融解させ、表面張力により金ボール２７（図４（Ｂ）参照）を形成する。この段階でクランパ２５は閉じている。   First, as shown in FIG. 4A, the capillary 22 is moved above the aluminum electrode pad 21 of the IC chip 20 on which the integrated circuit network is formed. A gold wire 24 having a diameter of about 20 to 30 μm is inserted into the center hole 23 of the capillary 22, and a clamper 25 for holding the wire 24 is disposed above the capillary 22. The tip of the capillary 22 has a diameter of about 100 μm. Then, the spark 26 is blown to the tip of the gold wire 24 and melted to form a gold ball 27 (see FIG. 4B) by surface tension. At this stage, the clamper 25 is closed.

次に、図４（Ｂ）に示すように、キャピラリ２２から飛び出たワイヤ２４の先端に金ボール２７が形成される。尚、金ボール２７の直径はスパーク２６の電流値と時間で制御され、本実施の形態では、例えば、金ボール２７の直径は６０〜８０μｍ程度である。しかし、金ボール２７の直径は、所望の目的に応じて任意に設計変更することができる。そして、次の作業に備え、クランパ２５を開け、ワイヤ２４を解放する。   Next, as shown in FIG. 4B, a gold ball 27 is formed at the tip of the wire 24 jumping out from the capillary 22. The diameter of the gold ball 27 is controlled by the current value and time of the spark 26. In the present embodiment, for example, the diameter of the gold ball 27 is about 60 to 80 μm. However, the diameter of the gold ball 27 can be arbitrarily changed according to a desired purpose. Then, in preparation for the next operation, the clamper 25 is opened and the wire 24 is released.

次に、図４（Ｃ）に示すように、キャピラリ２２を下降させることにより、金ボール２７を電極パッド２１表面に当接し、一定の圧力を加える。そして、同時に、キャピラリ２２を通して超音波振動を与え且つ加熱し、金ボール２７と電極パッド２１とを固着する。   Next, as shown in FIG. 4C, the capillary 22 is lowered to bring the gold ball 27 into contact with the surface of the electrode pad 21 and apply a certain pressure. At the same time, ultrasonic vibration is applied through the capillary 22 and heated to fix the gold ball 27 and the electrode pad 21 together.

次に、図４（Ｄ）に示すように、金ボール２７が固着した後、金ボール２７と金ワイヤ２４を残して、キャピラリ２２を垂直に上昇させる。   Next, as shown in FIG. 4D, after the gold ball 27 is fixed, the capillary 22 is raised vertically, leaving the gold ball 27 and the gold wire 24.

次に、図５（Ａ）に示すように、キャピラリ２２を再度垂直に下降させた後、
キャピラリ２２の水平方向の位置はそのままで、その先端と金ボール２７の上端（平坦部）との距離２８が１０〜３０μｍ程度となるような位置でキャピラリ２２を停止する。金ワイヤ２４の付け根付近はキャピラリ２２内部に収納されず、露出した状態となる。 Next, as shown in FIG. 5A, after the capillary 22 is again lowered vertically,
The capillary 22 is stopped at a position where the distance 28 between the tip of the capillary 22 and the upper end (flat portion) of the gold ball 27 is about 10 to 30 μm while keeping the horizontal position of the capillary 22 as it is. The vicinity of the root of the gold wire 24 is not housed inside the capillary 22 and is exposed.

次に、図５（Ｂ）に示すように、キャピラリ２２を水平移動させるが、このとき、上述した距離２８を維持した状態で、金ワイヤ２４の直径の３分の２を超える距離２９だけ移動させる。例えば、キャピラリ２２の先端部の穴の直径が４０μｍであるときは、２５〜３５μｍ程度だけキャピラリ２２を移動する。金ワイヤ２４はキャピラリ２２の先端部で途中まで剪断され、糸を引くように細い部分３０のみで連続している状態となる。   Next, as shown in FIG. 5B, the capillary 22 is moved horizontally. At this time, the capillary is moved by a distance 29 exceeding two-thirds of the diameter of the gold wire 24 while maintaining the distance 28 described above. Let For example, when the diameter of the hole at the tip of the capillary 22 is 40 μm, the capillary 22 is moved by about 25 to 35 μm. The gold wire 24 is sheared halfway at the tip of the capillary 22 and is continuous only at the thin portion 30 so as to pull the yarn.

次に、図５（Ｃ）に示すように、金ワイヤ２４と金ボール２７とを細い部分３０のみで連続させた状態で、再び、キャピラリ２２を上昇させる。   Next, as shown in FIG. 5C, the capillary 22 is raised again in a state in which the gold wire 24 and the gold ball 27 are continuous only by the thin portion 30.

最後に、図５（Ｄ）に示すように、金ワイヤ２４が所望の長さ（テイル長さ３１）だけ突出するようにキャピラリ２２を上昇させる。その後、今まで解放していたクランパ２５を閉じて金ワイヤ２４を狭持し、上方に引き上げることで細い部分３０を完全に切断する。そして、電極パッド２１上部にはバンプ電極３２が形成され、キャピラリ２２先端にはテイル長さ３１の分だけの金ワイヤ２４が残る。   Finally, as shown in FIG. 5D, the capillary 22 is raised so that the gold wire 24 protrudes by a desired length (tail length 31). Thereafter, the clamper 25 that has been released so far is closed, the gold wire 24 is pinched, and the thin portion 30 is completely cut by pulling it upward. A bump electrode 32 is formed on the electrode pad 21, and a gold wire 24 corresponding to the tail length 31 remains at the tip of the capillary 22.

尚、本実施の形態では、上述した製造方法により電極パッド上にバンプ電極を形成したが、この製造方法に限定する必要はない。本実施の形態以外の方法で電極パッド上にバンプ電極を形成した場合においても、上述した金属細線の接続構造及び接続方法を実現することができる。そして、その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。   In this embodiment, the bump electrode is formed on the electrode pad by the manufacturing method described above, but it is not necessary to limit to this manufacturing method. Even when the bump electrode is formed on the electrode pad by a method other than the present embodiment, the above-described metal thin wire connection structure and connection method can be realized. Various other modifications can be made without departing from the scope of the present invention.

上述したように、第１に、本発明の半導体装置では、ＩＣチップの電極パッド上に形成されたバンプ電極に対し、少なくとも２本以上の金属細線を接続することができる。そのことで、外部と授受する電流容量が大きい電極パッドでは、複数本の金属細線を接続し、外部と授受する電流容量が小さい電極パッドでは、１本の金属細線を接続する。その結果、外部と授受する電流容量が小さい電極パッドを基準とし、金属細線の径を選択することができるので、金属細線の配線抵抗の低減を実現することができる。   As described above, first, in the semiconductor device of the present invention, at least two or more fine metal wires can be connected to the bump electrodes formed on the electrode pads of the IC chip. Therefore, a plurality of fine metal wires are connected to an electrode pad having a large current capacity to be exchanged with the outside, and a single fine metal wire is connected to an electrode pad having a small current capacity to be exchanged with the outside. As a result, the diameter of the fine metal wire can be selected on the basis of the electrode pad having a small current capacity to be exchanged with the outside, so that the wiring resistance of the fine metal wire can be reduced.

第２に、本発明の半導体装置では、外部と授受する電流容量が小さい電極パッドを基準とし、金属細線の径を選択することができる。そのことで、ＩＣチップ上の全ての電極パッドに対し、細い径の金属細線でワイヤーボンディングを行うことができる。その結果、金属細線のコストを低減でき、且つ、細い径の金属細線であるが、大きい電流容量を外部と授受することができる。   Secondly, in the semiconductor device of the present invention, the diameter of the thin metal wire can be selected with reference to an electrode pad having a small current capacity to and from the outside. As a result, it is possible to perform wire bonding to all electrode pads on the IC chip with thin metal wires having a small diameter. As a result, the cost of the fine metal wires can be reduced, and the thin metal wires can be exchanged with a large current capacity.

第３に、本発明の半導体装置の製造方法では、外部と授受する電流容量が小さい電極パッドを基準とし、金属細線の径を選択し、その径の金属細線でＩＣ上の所望の電極パッドに対し、ワイヤーボンディングを行う。そのことで、同一径の金属細線を用いることで、１回のワイヤーボンディング工程で、種々の電流容量を外部と授受する電極パッドに金属細線を接続することができる。その結果、製造コストを低減し、製造時間の短縮を実現することができる。   Thirdly, in the method of manufacturing a semiconductor device according to the present invention, the diameter of a fine metal wire is selected based on an electrode pad having a small current capacity to be exchanged with the outside, and the desired fine electrode pad on the IC is formed with the fine metal wire of that diameter. On the other hand, wire bonding is performed. Thus, by using the fine metal wires having the same diameter, the fine metal wires can be connected to the electrode pads that exchange various current capacities with the outside in one wire bonding step. As a result, the manufacturing cost can be reduced and the manufacturing time can be shortened.

本発明の半導体装置を説明するための（Ａ）平面図（Ｂ）平面図である。BRIEF DESCRIPTION OF THE DRAWINGS (A) Top view (B) Plan view for demonstrating the semiconductor device of this invention. 本発明の半導体装置及びその製造方法を説明するための（Ａ）平面図（Ｂ）平面図である。It is (A) top view (B) top view for demonstrating the semiconductor device of this invention, and its manufacturing method. 本発明の半導体装置及び製造方法を説明するための（Ａ）平面図（Ｂ）斜視図である。It is (A) top view (B) perspective view for demonstrating the semiconductor device and manufacturing method of this invention. 本発明の半導体装置の製造方法を説明するための（Ａ）断面図（Ｂ）断面図（Ｃ）断面図（Ｄ）断面図である。It is (A) sectional drawing (B) sectional drawing (C) sectional drawing (D) sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明するための（Ａ）断面図（Ｂ）断面図（Ｃ）断面図（Ｄ）断面図である。It is (A) sectional drawing (B) sectional drawing (C) sectional drawing (D) sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention.

符号の説明Explanation of symbols

１:電極パッド
２:ＩＣチップ
３:アイランド
６:第１のアイランド
７:第２のアイランド
１５:電極パッド 1: electrode pad 2: IC chip 3: island 6: first island 7: second island 15: electrode pad

Claims (4)

第１のアイランド上に固着された第１の半導体チップと、
前記第１のアイランドと離間して配置された第２のアイランド上に固着された第２の半導体チップと、
前記第１のアイランドと前記第２のアイランドを囲むように設けられた複数のリードとを有する半導体装置に於いて、
前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第１の半導体チップ側に設けられた複数の第１の電極パッドと、
前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第２の半導体チップ側に設けられた第２の電極パッドと、
前記第２の電極パッドに設けられたバンプ電極と、
前記複数の第１の電極パッドの一つ目と前記バンプ電極とを接続する第１のボンディングワイヤと、
前記複数の第１の電極パッドの二つ目と前記バンプ電極とを接続する第２のボンディングワイヤとを有する事を特徴とした半導体装置。 A first semiconductor chip fixed on the first island;
A second semiconductor chip fixed on a second island spaced apart from the first island;
In a semiconductor device having a plurality of leads provided so as to surround the first island and the second island,
A plurality of first electrode pads located on opposite sides of the first semiconductor chip and the second semiconductor chip and provided on the first semiconductor chip side;
A second electrode pad located on the opposite side of the first semiconductor chip and the second semiconductor chip and provided on the second semiconductor chip side;
A bump electrode provided on the second electrode pad;
A first bonding wire connecting the first of the plurality of first electrode pads and the bump electrode;
A semiconductor device comprising: a second bonding wire for connecting a second of the plurality of first electrode pads and the bump electrode. 前記第２の電極パッドは、Ｖｃｃ用またはＧＮＤ用のパッドである請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second electrode pad is a pad for Vcc or GND. 第１のアイランド上に固着された第１の半導体チップと、
前記第１のアイランドと離間して配置された第２のアイランド上に固着された第２の半導体チップと、
前記第１のアイランドと前記第２のアイランドを囲むように設けられた複数のリードとを有する半導体装置に於いて、
前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第１の半導体チップ側に設けられた複数の第１の電極パッドと、
前記第１の半導体チップと前記第２の半導体チップとの対向する側辺に位置し、前記第２の半導体チップ側に設けられた第２の電極パッドと、
前記第２の電極パッドに設けられたバンプ電極と、
前記複数の第１の電極パッドの一つ目と前記バンプ電極とを接続する第１のボンディングワイヤと、
前記複数の第１の電極パッドの二つ目と前記バンプ電極とを接続する第２のボンディングワイヤとを有し、
前記バンプ電極側の前記第１のボンディングワイヤおよび前記第２のボンディングワイヤの付け根は、前記バンプ電極を形成する際に設けられる凸部の上を避けて設けられる事を特徴とした半導体装置。 A first semiconductor chip fixed on the first island;
A second semiconductor chip fixed on a second island spaced apart from the first island;
In a semiconductor device having a plurality of leads provided so as to surround the first island and the second island,
A plurality of first electrode pads located on opposite sides of the first semiconductor chip and the second semiconductor chip and provided on the first semiconductor chip side;
A second electrode pad located on the opposite side of the first semiconductor chip and the second semiconductor chip and provided on the second semiconductor chip side;
A bump electrode provided on the second electrode pad;
A first bonding wire connecting the first of the plurality of first electrode pads and the bump electrode;
A second bonding wire connecting the second of the plurality of first electrode pads and the bump electrode;
The semiconductor device according to claim 1, wherein the bases of the first bonding wire and the second bonding wire on the bump electrode side are provided so as not to be on a convex portion provided when the bump electrode is formed. 前記ボンディングワイヤの前記バンプ電極側は、スティッチボンドで形成される請求項３の半導体装置。   The semiconductor device according to claim 3, wherein the bump electrode side of the bonding wire is formed by stitch bonding.
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