JP4476247B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP4476247B2
JP4476247B2 JP2006172961A JP2006172961A JP4476247B2 JP 4476247 B2 JP4476247 B2 JP 4476247B2 JP 2006172961 A JP2006172961 A JP 2006172961A JP 2006172961 A JP2006172961 A JP 2006172961A JP 4476247 B2 JP4476247 B2 JP 4476247B2
Authority
JP
Japan
Prior art keywords
ball
bonding wire
bonding
capillary
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2006172961A
Other languages
Japanese (ja)
Other versions
JP2006253727A (en
Inventor
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2006172961A priority Critical patent/JP4476247B2/en
Publication of JP2006253727A publication Critical patent/JP2006253727A/en
Application granted granted Critical
Publication of JP4476247B2 publication Critical patent/JP4476247B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20756—Diameter ranges larger or equal to 60 microns less than 70 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H01L2924/20757—Diameter ranges larger or equal to 70 microns less than 80 microns

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which overlaps a plurality of semiconductor chips for molding, while decreasing a thickness of a package external shape, wherein the high reliability of a ball bump is materialized. <P>SOLUTION: A ball bump 33 makes use of ball bonding of a bonding wire 32, and a capillary 30 arranged with a ball 33 is used at a distal end thereof. The ball 33 is secured to a bonding pad 12a, and the capillary 30 is lifted up and moved horizontally so that the bonding wire near a root of the ball 33 is not received in the capillary, whereby a fine bonding wire is formed between the ball and the bonding wire. In such a state that the fine bonding wire is contiguous to the ball 33, the bonding wire is clamped and the capillary is lifted up, whereby the fine bonding wire is cut. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は、複数の半導体チップを重ね合わせてモールドしつつ、パッケージ外形の薄型化が可能な、半導体装置に関する。   The present invention relates to a semiconductor device capable of reducing the package outer shape while stacking and molding a plurality of semiconductor chips.

半導体装置の封止技術として最も普及しているのが、図４（Ａ）に示したような、半導体チップ１の周囲を熱硬化性のエポキシ樹脂２で封止するトランスファーモールド技術である。半導体チップ１の支持素材としてリードフレームを用いており、リードフレームのアイランド３に半導体チップ１をダイボンドし、半導体チップ１のボンディングパッドとリード４をワイヤ５でワイヤボンドし、所望の外形形状を具備する金型内にリードフレームをセットし、金型内にエポキシ樹脂を注入、これを硬化させることにより製造される。   As the semiconductor device sealing technique, the transfer mold technique for sealing the periphery of the semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. A lead frame is used as a support material for the semiconductor chip 1, the semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pad of the semiconductor chip 1 and the lead 4 are wire-bonded with the wire 5 to have a desired outer shape. The lead frame is set in a mold to be manufactured, and an epoxy resin is injected into the mold and is cured.

一方、各種電子機器に対する小型、軽量化の波はとどまるところを知らず、これらに組み込まれる半導体装置にも、一層の大容量、高機能、高集積化が望まれることになる。   On the other hand, the wave of miniaturization and weight reduction for various electronic devices is not limited, and further higher capacity, higher functionality, and higher integration are desired for semiconductor devices incorporated therein.

そこで、以前から発想としては存在していた（例えば、特開昭５５ー１１１１５１７号）、１つのパッケージ内に複数の半導体チップを封止する技術が注目され、実現化する動きが出てきた。つまり図４（Ｂ）に示すように、アイランド３上に第１の半導体チップ１ａを固着し、第１の半導体チップ１ａの上に第２の半導体チップ１ｂを固着し、対応するボンディングパッドとリード４とを第１と第２のボンディングワイヤ５ａ、５ｂで接続し、樹脂２で封止したものである。   Therefore, a technique that has existed as an idea for a long time (for example, Japanese Patent Application Laid-Open No. 55-1111517) has been attracting attention and a movement to realize it has attracted attention. That is, as shown in FIG. 4B, the first semiconductor chip 1a is fixed on the island 3, the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and leads are fixed. 4 is connected by first and second bonding wires 5 a and 5 b and sealed with resin 2.

コストアップになるにも関わらず複数のチップを一体化させることは、即ち軽薄短小化の要求が極めて強いからに他ならない。故に外形寸法に余裕のあるＤＩＰ型パッケージよりは、表面実装型の、しかも薄型のパッケージに収納したい意向が強く、その方が全体としてのメリットが大きい。   In spite of the increase in cost, the integration of a plurality of chips is none other than the strong demand for miniaturization. Therefore, there is a strong desire to be housed in a surface mount type and thin package rather than a DIP type package with a sufficient external dimension, and this has a larger merit as a whole.

しかしながら、半導体チップ１には、機械的強度を持たせる必要性から、ある程度の厚み以上には薄くすることができないので、チップを積層した分だけパッケージ外形を大型化する欠点がある。   However, since the semiconductor chip 1 cannot be made thinner than a certain thickness because of the need to have mechanical strength, there is a drawback that the package outer shape is increased by the amount of stacked chips.

また、第２のボンディングワイヤ５ｂは、第１の半導体チップ１ａとの接触を避けることと、第１のボンディングワイヤ５ａと交差したときの接触を避けるという意味で、ワイヤループを相当大きく取る必要性が生じる。そのため、ワイヤループの高さ６が大きくなりがちであり、これがパッケージ全体の厚みを厚くして、薄形化を阻害するという欠点があった。   Further, the second bonding wire 5b needs to have a considerably large wire loop in the sense of avoiding contact with the first semiconductor chip 1a and avoiding contact when intersecting with the first bonding wire 5a. Occurs. For this reason, the height 6 of the wire loop tends to be large, which increases the overall thickness of the package and has a drawback of hindering thinning.

本発明は上述した従来の課題に鑑み成されたもので、
第１に、ボンディングパッドを有する半導体チップにボールバンプを形成する半導体装置の製造方法であり、
前記ボールバンプは、ボンディングワイヤのボールボンディングが活用され、
先端にボールが配置されたキャピラリを使い、前記ボンディングパッドに前記ボールを固着し、
前記ボールの付け根付近の前記ボンディングワイヤが前記キャピラリの内部に収納されないように、前記キャピラリを上昇させ、
前記キャピラリを水平移動させることによって、前記ボールと前記ボンディングワイヤの間に細いボンディングワイヤを形成し、
前記細いボンディングワイヤが前記ボールと連続している状態で、前記ボンディングワイヤをクランプしてキャピラリを上昇させることにより、前記細いボンディングワイヤを切断させて前記ボールバンプを形成することで解決するものである。
第２に、前記キャピラリの水平移動の距離を、前記ボンディングワイヤの直径のほぼ３分の２を越える距離とすることで解決するものである。
第３に、前記ボンディングワイヤをクランプし水平方向に移動させることにより、剪断しながら前記細いボンディングワイヤを形成することで解決するものである。 The present invention has been made in view of the above-described conventional problems.
1st is the manufacturing method of the semiconductor device which forms a ball bump in the semiconductor chip which has a bonding pad,
The ball bump is a ball bonding of a bonding wire,
Using a capillary in which a ball is arranged at the tip, the ball is fixed to the bonding pad,
Raise the capillary so that the bonding wire near the base of the ball is not housed inside the capillary,
By horizontally moving the capillary, a thin bonding wire is formed between the ball and the bonding wire,
In the state where the thin bonding wire is continuous with the ball, the bonding wire is clamped and the capillary is raised to cut the thin bonding wire to form the ball bump. .
Second, the distance of the horizontal movement of the capillary is set to a distance exceeding approximately two thirds of the diameter of the bonding wire.
Third, the thin bonding wire is formed while being sheared by clamping and moving the bonding wire in the horizontal direction.

以上に説明した通り、本発明によれば、１つのパッケージ内に複数の半導体チップ１０、１１を積層する事により、電子機器の軽薄短小化の要求に沿った高密度実装の製品を提供できる利点を有する。   As described above, according to the present invention, by stacking a plurality of semiconductor chips 10 and 11 in a single package, it is possible to provide a product with high-density mounting that meets the demand for light and thin electronic devices. Have

また、ボンディングワイヤ１８と内部電極１４とを、第１のボンディングパッド１２ａを介して接続するので、パッド１２ｂからパッド１２ａまでのボンディングワイヤ１８の長さを短くできる利点を有する。これにより、ループ高さ２２を低く抑えることができるので、パッケージの厚みを薄形化できる利点を有する。   Further, since the bonding wire 18 and the internal electrode 14 are connected via the first bonding pad 12a, there is an advantage that the length of the bonding wire 18 from the pad 12b to the pad 12a can be shortened. Thereby, since the loop height 22 can be kept low, there is an advantage that the thickness of the package can be reduced.

そして、第２のボンディングパッド１２ｂから内部電極１４に直接ワイヤボンドしないので、ボンディングワイヤ１８の交差が無くなり、電気的短絡という事故を防ぐ他、ボンディングワイヤ１８と第１の半導体チップ１０との接触をも防止することができる。   Since the second bonding pad 12b is not directly wire-bonded to the internal electrode 14, the bonding wire 18 is not crossed to prevent an electrical short circuit, and the contact between the bonding wire 18 and the first semiconductor chip 10 is prevented. Can also be prevented.

更に内部電極１４へのステッチボンドが１本で済むので、ボンディングエリアを小さくすることができ、半導体装置の小型化を図ることができる。   Furthermore, since only one stitch bond to the internal electrode 14 is required, the bonding area can be reduced, and the semiconductor device can be miniaturized.

以下に本発明の一実施の形態を図面を参照しながら詳細に説明する。   Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

先ず、図１（Ａ）は本発明の半導体装置を示す断面図、図１（Ｂ）は要部拡大断面図である。   First, FIG. 1A is a cross-sectional view showing a semiconductor device of the present invention, and FIG.

図中、１０、１１は各々第１と第２の半導体チップを示している。第１と第２の半導体チップ１０、１１のシリコン表面には、前工程において各種の能動、受動回路素子が形成されている。第１の半導体チップ１０の表面には外部接続用の第１のボンディングパッド１２ａが形成されている。同様に第２の半導体チップ１１の表面には第２のボンディングパッド１２ｂが形成されている。各チップ表面には各ボンディングパッド１２ａ、１２ｂを被覆するようにシリコン窒化膜、シリコン酸化膜、ポリイミド系絶縁膜などのパッシベーション皮膜が形成され、ボンディングパッド１２ａ、１２ｂの上部は電気接続のために開口されている。   In the figure, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. Various active and passive circuit elements are formed on the silicon surfaces of the first and second semiconductor chips 10 and 11 in the previous step. A first bonding pad 12 a for external connection is formed on the surface of the first semiconductor chip 10. Similarly, a second bonding pad 12 b is formed on the surface of the second semiconductor chip 11. A passivation film such as a silicon nitride film, a silicon oxide film, or a polyimide insulating film is formed on the surface of each chip so as to cover the bonding pads 12a and 12b, and upper portions of the bonding pads 12a and 12b are opened for electrical connection. Has been.

絶縁性のフィルム基板１３は、これら第１と第２の半導体チップ１０、１１を支持する基板となる。フィルム基板１３の表面には金メッキ層によって導電パターンが描画されている。導電パターンは各ボンディングパッド１２ａ、１２ｂとバンプ電極２０とを各々接続するための内部電極１４とを形成する。   The insulating film substrate 13 serves as a substrate that supports the first and second semiconductor chips 10 and 11. A conductive pattern is drawn on the surface of the film substrate 13 by a gold plating layer. The conductive pattern forms an internal electrode 14 for connecting each bonding pad 12a, 12b and the bump electrode 20 respectively.

第１の半導体チップ１０は、前記アイランド部の上にエポキシ系絶縁接着剤１５により固着されている。第２の半導体チップ１１は第１の半導体チップ１０の前記パッシベーション皮膜上に絶縁性のエポキシ系接着剤１５により固着されている。但し第２の半導体チップ１１は第１のボンディングパッド１２ａを被覆しないチップサイズである。   The first semiconductor chip 10 is fixed on the island part with an epoxy insulating adhesive 15. The second semiconductor chip 11 is fixed on the passivation film of the first semiconductor chip 10 with an insulating epoxy adhesive 15. However, the second semiconductor chip 11 has a chip size that does not cover the first bonding pad 12a.

第１のボンディングパッド１２ａの上部には、ボールバンプ１７が形成されている。ボールバンプ１７は、金ワイヤのボールボンディング手法を利用して、金ボール部分だけを残す形で形成したバンプ電極である。そして、第２のボンディングパッド１２ｂと内部電極１４とが、ボールバンプ１７を経由して、連続したボンディングワイヤ１８によって接続されている。ボンディングワイヤ１８は第２の電極パッド１２ｂ表面にボードボンドされ（ファーストボンド）、ボールバンプ１７の上部で一端ステッチボンドされ、そして内部電極１４表面で再度ステッチボンドされて接続されている。このボールバンプ１７は、ボンディングワイヤ１８を第１の電極パッド１２ａ上にセカンドボンド（ステッチボンド）する際に、ボンディングツールの先端が第１の半導体チップ１０の表面に直接当接する事を防止する緩衝剤となる。   Ball bumps 17 are formed on the first bonding pads 12a. The ball bumps 17 are bump electrodes formed using a gold wire ball bonding technique so as to leave only the gold ball portion. The second bonding pad 12 b and the internal electrode 14 are connected by a continuous bonding wire 18 via a ball bump 17. The bonding wire 18 is board-bonded to the surface of the second electrode pad 12b (first bond), is stitch-bonded once on the top of the ball bump 17, and is stitch-bonded again on the surface of the internal electrode 14 to be connected. The ball bump 17 is a buffer that prevents the tip of the bonding tool from directly contacting the surface of the first semiconductor chip 10 when the bonding wire 18 is second bonded (stitch bonded) onto the first electrode pad 12a. Become an agent.

複数のバンプ電極２０が、フィルム基板１３の裏面側に形成されている。フィルム基板１３には図示せぬ貫通孔が設けられており、この貫通孔を介して内部電極１４とバンプ電極２０とが接続している。   A plurality of bump electrodes 20 are formed on the back side of the film substrate 13. The film substrate 13 is provided with a through hole (not shown), and the internal electrode 14 and the bump electrode 20 are connected through the through hole.

エポキシ系の熱硬化樹脂２１が、第１と第２の半導体チップ１０、１１の周囲を被覆する。熱硬化性樹脂２１はフィルム基板１３の上側を被覆して、パッケージ外形を形成する。   An epoxy thermosetting resin 21 covers the periphery of the first and second semiconductor chips 10 and 11. The thermosetting resin 21 covers the upper side of the film substrate 13 to form a package outer shape.

図２は、ボンディングワイヤ１８を形成するときのステップを示している。あらかじめ図２（Ａ）に示したように、第１の電極パッド１２ａ上にボールバンプ１７を形成しておき、キャピラリ３０を利用して第２の電極パッド１２ｂ上に金ボール３３をファーストボンドし、続いてキャピラリ３０を移動してボールバンプ１７上に金ワイヤ３２をステッチボンドし、この時に金ワイヤ３２を切断せずに連続させて延在させ、そして内部電極１４表面にセカンドボンドを行う。   FIG. 2 shows the steps in forming the bonding wire 18. As shown in FIG. 2A, ball bumps 17 are formed on the first electrode pads 12a in advance, and gold balls 33 are first bonded on the second electrode pads 12b using the capillaries 30. Subsequently, the capillary 30 is moved to stitch bond the gold wire 32 onto the ball bump 17, and at this time, the gold wire 32 is continuously extended without being cut, and a second bond is performed on the surface of the internal electrode 14.

第１と第２の半導体チップ１０、１１は、メモリ装置で組み合わせることが簡便である。例えば、第１と第２の半導体チップ１０、１１としてＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を用いた場合（第１の組み合わせ例）は、１つのパッケージで記憶容量を２倍、３倍・・・にすることができる。また、第１の半導体チップ１０にＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を、第２の半導体チップ１１にはＳＲＡＭ等の半導体記憶装置を形成するような場合（第２の組み合わせ例）も考えられる。   The first and second semiconductor chips 10 and 11 can be easily combined in a memory device. For example, when a semiconductor storage device such as an EEPROM (flash memory) is used as the first and second semiconductor chips 10 and 11 (first combination example), the storage capacity is doubled, tripled,・ ・Further, a case where a semiconductor memory device such as an EEPROM (flash memory) is formed on the first semiconductor chip 10 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 (second combination example) is also considered. It is done.

どちらの組み合わせの場合でも、各チップにはデータの入出力を行うＩ／Ｏ端子と、データのアドレスを指定するアドレス端子、及びデータの入出力を許可するチップイネーブル端子とを具備しており、両チップのピン配列が酷似している。そのため、第１と第２の半導体チップ１０、１１のＩ／Ｏ端子やアドレス端子用の内部電極１４を共用することが可能であり、各チップに排他的なチップイネーブル信号を印加することにより、どちらか一方の半導体チップのメモリセルを排他的に選択することが可能である。また、斯かる構成によって、第１と第２のボンディングパッド１２ａ、１２ｂを電気的に接続することが可能となる。   In either combination, each chip has an I / O terminal for inputting / outputting data, an address terminal for designating an address of data, and a chip enable terminal for permitting input / output of data, The pin arrangement of both chips is very similar. Therefore, the internal electrodes 14 for the I / O terminals and address terminals of the first and second semiconductor chips 10 and 11 can be shared, and by applying an exclusive chip enable signal to each chip, It is possible to exclusively select the memory cells of either one of the semiconductor chips. In addition, with this configuration, the first and second bonding pads 12a and 12b can be electrically connected.

尚、第１と第２のボンディングパッド１２ａ、１２ｂを電気的に接続できない回路構成である場合は、第１のボンディングパッド１２ａを電気的に独立させて回路的な機能を持たないダミーのパッドとし、該ダミーパッド上にボールバンプ１７を形成して、図１のようにボンディングワイヤ１８で接続する。   When the circuit configuration is such that the first and second bonding pads 12a and 12b cannot be electrically connected, the first bonding pad 12a is electrically independent to form a dummy pad having no circuit function. Then, ball bumps 17 are formed on the dummy pads and connected by bonding wires 18 as shown in FIG.

図３は、ボールバンプ１７の製造方法を簡単に説明するための断面図である。   FIG. 3 is a cross-sectional view for briefly explaining the method of manufacturing the ball bump 17.

図３（Ａ）参照：キャピラリ３０の中心孔３１に直径が２０〜３０μ程度の金ワイヤ３２を挿通し、そのワイヤ３２の先端にあらかじめスパークなどの手段によって直径が６０〜８０μの金ボール３３を形成しておく。これを第１のボンディングパッド１２ａ上方に移動し、キャピラリ３０を下降させることにより、金ボール３３を電極パッド１２ａ表面に当接し、一定の圧力を加える。同時にキャピラリ１２を通して超音波振動を与え且つ加熱して、金ボール３３と第１のボンディングパッド１２ａとを固着する。   3A: A gold wire 32 having a diameter of about 20 to 30 μ is inserted into the center hole 31 of the capillary 30, and a gold ball 33 having a diameter of 60 to 80 μ is previously inserted into the tip of the wire 32 by means such as spark. Form it. This is moved above the first bonding pad 12a and the capillary 30 is lowered, whereby the gold ball 33 is brought into contact with the surface of the electrode pad 12a and a certain pressure is applied. Simultaneously, ultrasonic vibration is applied through the capillary 12 and heated to fix the gold ball 33 and the first bonding pad 12a.

図３（Ｂ）参照：キャピラリ３０を垂直に上昇させ、再度垂直に下降させる。キャピラリ３０の先端と金ボール３３の上端（平坦部）との距離３４が１０〜３０μｍとなるような位置でキャピラリ３０を停止する。金ボール３３の付け根付近はキャピラリ３０内部に収納されず、露出した状態となる。   See FIG. 3B: The capillary 30 is raised vertically and lowered again vertically. The capillary 30 is stopped at a position where the distance 34 between the tip of the capillary 30 and the upper end (flat portion) of the gold ball 33 is 10 to 30 μm. The vicinity of the base of the gold ball 33 is not stored in the capillary 30 and is exposed.

図３（Ｃ）参照：上記の距離３４を維持した上で、金ワイヤ３２の直径の３分の２を超える距離だけキャピラリ３０を水平移動する。例えば、キャピラリ１２先端部の穴の直径が４０μであるときは２５μ〜３５μだけ移動する。金ワイヤ３２はキャピラリ３０の先端部で途中まで剪断され、糸を引くように細い部分３５でかろうじて連続している状態となる。   See FIG. 3C: The above-described distance 34 is maintained, and the capillary 30 is horizontally moved by a distance exceeding two-thirds of the diameter of the gold wire 32. For example, when the diameter of the hole at the tip of the capillary 12 is 40 μm, the capillary 12 moves by 25 μm to 35 μm. The gold wire 32 is sheared halfway at the tip of the capillary 30 and is barely continuous at the narrow portion 35 so as to pull the yarn.

本工程で剪断を与えるために、距離３４は重要な意味を持つ。この距離３４が大きすぎると金ワイヤ３２が塑性変形するだけで細い部分３５を作れなくなるし、距離３４が小さすぎると、接合した金ボール１７を剥がすことになる。キャピラリ３０の先端が、図３（Ｄ）に示したように、金ボール３３の付け根近傍で、塑性変形の影響を受けずに金ワイヤ３２が本来の直径Φ１を維持した部分の直ぐ上部に位置するようにコントロールする。   The distance 34 has an important meaning in order to provide shear in this process. If the distance 34 is too large, the thin portion 35 cannot be formed simply by plastic deformation of the gold wire 32. If the distance 34 is too small, the bonded gold ball 17 is peeled off. As shown in FIG. 3D, the tip of the capillary 30 is located near the base of the gold ball 33, just above the portion where the gold wire 32 maintains the original diameter Φ1 without being affected by plastic deformation. To control.

図３（Ｅ）参照：再びキャピラリ１２を垂直上昇させた状態を示している。金ワイヤ３２と金ボール３３とが細い部分３５だけで連続している状態を示した。   See FIG. 3E: The capillary 12 is again raised vertically. The state where the gold wire 32 and the gold ball 33 are continuous only at the thin portion 35 is shown.

図３（Ｆ）参照：今まで解放していた図示せぬクランパを閉じて金ワイヤ３２を挟持し、上方に引き上げることで細い部分３５を完全に切断する。この様な工程により第１のボンディングパッド１２ａ上部にボールバンプ１７が形成される。   See FIG. 3 (F): The clamper (not shown) that has been released so far is closed, the gold wire 32 is clamped, and the thin portion 35 is completely cut by pulling upward. By such a process, the ball bumps 17 are formed on the first bonding pads 12a.

以上に説明した本発明の半導体装置は、第２のボンディングパッド１２ｂを第１のボンディングパッド１２ａに接続することによって、両者の距離が近いので、ボンディングワイヤ１８のループ長さを短くすることが可能である。従って、ループ高さ２２（図１）を低く押さえることができる。これは、第１の半導体チップ１０と第２の半導体チップ１１とのチップサイズの差が大きい場合に特に有効になる。そして、ボンディングワイヤ１８と第１の半導体チップ１０との接触事故を回避することができる。、更には、ボンディングワイヤの交差配置が無くなるので、両者の電気的短絡をも回避することができる。   In the semiconductor device of the present invention described above, the loop length of the bonding wire 18 can be shortened by connecting the second bonding pad 12b to the first bonding pad 12a so that the distance between the two is close. It is. Therefore, the loop height 22 (FIG. 1) can be kept low. This is particularly effective when the difference in chip size between the first semiconductor chip 10 and the second semiconductor chip 11 is large. Then, a contact accident between the bonding wire 18 and the first semiconductor chip 10 can be avoided. Furthermore, since there is no crossing arrangement of the bonding wires, an electrical short circuit between them can be avoided.

以上に説明した通り、本発明によれば、１つのパッケージ内に複数の半導体チップ１０、１１を積層する事により、電子機器の軽薄短小化の要求に沿った高密度実装の製品を提供できる利点を有する。   As described above, according to the present invention, by stacking a plurality of semiconductor chips 10 and 11 in a single package, it is possible to provide a product with high-density mounting that meets the demand for light and thin electronic devices. Have

また、ボンディングワイヤ１８と内部電極１４とを、第１のボンディングパッド１２ａを介して接続するので、パッド１２ｂからパッド１２ａまでのボンディングワイヤ１８の長さを短くできる利点を有する。これにより、ループ高さ２２を低く抑えることができるので、パッケージの厚みを薄形化できる利点を有する。   Further, since the bonding wire 18 and the internal electrode 14 are connected via the first bonding pad 12a, there is an advantage that the length of the bonding wire 18 from the pad 12b to the pad 12a can be shortened. Thereby, since the loop height 22 can be kept low, there is an advantage that the thickness of the package can be reduced.

そして、第２のボンディングパッド１２ｂから内部電極１４に直接ワイヤボンドしないので、ボンディングワイヤ１８の交差が無くなり、電気的短絡という事故を防ぐ他、ボンディングワイヤ１８と第１の半導体チップ１０との接触をも防止することができる。   Since the second bonding pad 12b is not directly wire-bonded to the internal electrode 14, the bonding wire 18 is not crossed to prevent an electrical short circuit, and the contact between the bonding wire 18 and the first semiconductor chip 10 is prevented. Can also be prevented.

更に内部電極１４へのステッチボンドが１本で済むので、ボンディングエリアを小さくすることができ、半導体装置の小型化を図ることができる。   Furthermore, since only one stitch bond to the internal electrode 14 is required, the bonding area can be reduced, and the semiconductor device can be miniaturized.

本発明を説明するための断面図である。It is sectional drawing for demonstrating this invention. 本発明を説明するための断面図である。It is sectional drawing for demonstrating this invention. 本発明を説明するための断面図である。It is sectional drawing for demonstrating this invention. 従来例を説明するための断面図である。It is sectional drawing for demonstrating a prior art example.

Claims (6)

半導体チップ上のボンディングパッドに、ボールバンプを形成する半導体装置の製造方法であり、
前記ボールバンプの形成は、ボンディングワイヤのボールボンディング法が活用され、
前記ボンディングワイヤが挿通され、先端にボールが配置されたキャピラリを使い、前記ボンディングパッドに前記ボールを固着し、
前記ボールの付け根付近の前記ボンディングワイヤが前記キャピラリの内部に収納されないように、前記キャピラリを上昇させ、
前記キャピラリを水平移動させることによって、前記ボンディングワイヤを途中まで剪断して細い部分を形成し、
前記ボンディングワイヤが前記細い部分を通じて前記ボールと連続している状態で、前記キャピラリを上昇させた後に、前記ボンディングワイヤをクランプして前記キャピラリを上昇させることにより、前記細い部分を完全に切断させて前記ボールバンプを形成することを特徴とした半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a ball bump is formed on a bonding pad on a semiconductor chip .
For the formation of the ball bump , a ball bonding method of a bonding wire is utilized,
The bonding wire is inserted, and a capillary with a ball disposed at the tip is used to fix the ball to the bonding pad,
Raise the capillary so that the bonding wire near the base of the ball is not housed inside the capillary,
By moving the capillary horizontally, the bonding wire is sheared halfway to form a thin portion,
In a state where the bonding wire is continuous with the ball through the thin portion , the capillary is raised, and then the bonding wire is clamped and the capillary is raised to completely cut the thin portion. A method of manufacturing a semiconductor device, wherein the ball bump is formed. 前記剪断の位置は、前記ボールから延在される前記ボンディングワイヤの直径を維持した所で、前記ボンディングワイヤの付け根の直ぐ上部である請求項１に記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the shearing position is located immediately above the base of the bonding wire at a position where the diameter of the bonding wire extending from the ball is maintained. 前記ボールバンプの上にボンディングワイヤをボンドする請求項１または請求項２に記載の半導体装置の製造方法。  The method for manufacturing a semiconductor device according to claim 1, wherein a bonding wire is bonded onto the ball bump. 前記半導体チップは、前記半導体チップを支持する基板に固着されている請求項１、請求項２または請求項３に記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is fixed to a substrate that supports the semiconductor chip. 前記半導体チップの表面にはパッシベーション皮膜が設けられると共に、前記ボンディングパッドの上部は前記パッシベーション皮膜が開口され、  A passivation film is provided on the surface of the semiconductor chip, and the upper part of the bonding pad is opened with the passivation film,
前記半導体チップは、絶縁接着剤によりフィルム基板に固着され、  The semiconductor chip is fixed to the film substrate by an insulating adhesive,
前記パッシベーション皮膜の開口された所のボンディングパッドに前記ボールバンプを形成する請求項１〜請求項４のいずれか１項に記載の半導体装置の製造方法。  5. The method of manufacturing a semiconductor device according to claim 1, wherein the ball bump is formed on a bonding pad where the passivation film is opened. 6. 前記半導体チップの表面にはパッシベーション皮膜が設けられると共に、前記ボンディングパッドの上部は前記パッシベーション皮膜が開口され、  A passivation film is provided on the surface of the semiconductor chip, and the upper part of the bonding pad is opened with the passivation film,
前記半導体チップは、前記半導体チップを支持する基板に設けられた絶縁接着剤により固着され、  The semiconductor chip is fixed by an insulating adhesive provided on a substrate that supports the semiconductor chip,
前記半導体チップを支持する基板には、金メッキから成る内部電極が設けられ、金から成る前記金属細線は、前記ボールバンプの上部と前記内部電極の間で接続される請求項１〜請求項４のいずれか１項に記載の半導体装置の製造方法。  5. The substrate supporting the semiconductor chip is provided with an internal electrode made of gold plating, and the fine metal wire made of gold is connected between the upper part of the ball bump and the internal electrode. A manufacturing method of a semiconductor device given in any 1 paragraph.
JP2006172961A 2006-06-22 2006-06-22 Manufacturing method of semiconductor device Expired - Lifetime JP4476247B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006172961A JP4476247B2 (en) 2006-06-22 2006-06-22 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006172961A JP4476247B2 (en) 2006-06-22 2006-06-22 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP29554698A Division JP3869562B2 (en) 1998-10-16 1998-10-16 Manufacturing method of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007079664A Division JP4476308B2 (en) 2007-03-26 2007-03-26 Ball bump manufacturing method and manufacturing apparatus thereof

Publications (2)

Publication Number Publication Date
JP2006253727A JP2006253727A (en) 2006-09-21
JP4476247B2 true JP4476247B2 (en) 2010-06-09

Family

ID=37093789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006172961A Expired - Lifetime JP4476247B2 (en) 2006-06-22 2006-06-22 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4476247B2 (en)

Also Published As

Publication number Publication date
JP2006253727A (en) 2006-09-21

Similar Documents

Publication Publication Date Title
JP3865055B2 (en) Manufacturing method of semiconductor device
US20180025967A1 (en) Flip-chip, face-up and face-down centerbond memory wirebond assemblies
JP3643706B2 (en) Semiconductor device
JP2005183923A (en) Semiconductor device and its manufacturing method
JP3958522B2 (en) Semiconductor device
JP2007134486A (en) Stacked semiconductor device and its manufacturing method
JP3869562B2 (en) Manufacturing method of semiconductor device
JP2000243887A (en) Semiconductor device and its manufacture
JP3378809B2 (en) Semiconductor device
JP3670853B2 (en) Semiconductor device
JP2007214238A (en) Semiconductor device and its manufacturing method
JP3643705B2 (en) Semiconductor device and manufacturing method thereof
JPH10335368A (en) Wire-bonding structure and semiconductor device
JP4476247B2 (en) Manufacturing method of semiconductor device
JP4642047B2 (en) Semiconductor device
JP4476308B2 (en) Ball bump manufacturing method and manufacturing apparatus thereof
JPH10335366A (en) Semiconductor device
JP3888438B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2005167286A (en) Semiconductor device and manufacturing method thereof
JP4007917B2 (en) Semiconductor device and manufacturing method thereof
JP3172472B2 (en) Semiconductor device
US7968993B2 (en) Stacked semiconductor device and semiconductor memory device
JP3172473B2 (en) Semiconductor device
JP3954586B2 (en) Semiconductor device
JP3954585B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060622

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090707

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090904

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100209

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100309

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130319

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140319

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term