JP3643705B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP3643705B2
JP3643705B2 JP21819798A JP21819798A JP3643705B2 JP 3643705 B2 JP3643705 B2 JP 3643705B2 JP 21819798 A JP21819798 A JP 21819798A JP 21819798 A JP21819798 A JP 21819798A JP 3643705 B2 JP3643705 B2 JP 3643705B2
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Prior art keywords
semiconductor chip
semiconductor
main surface
electrode pad
adhesive
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Expired - Fee Related
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JP21819798A
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Japanese (ja)
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JP2000058742A (en
Inventor
誠 坪野谷
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of JP3643705B2 publication Critical patent/JP3643705B2/en
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Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体チップを重ね合わせてモールドしつつ、近似した大きさを持つ半導体チップの組み合わせでも小型化できる半導体装置に関する。
【０００２】
【従来の技術】
半導体装置の封止技術として最も普及しているのが、図６（Ａ）に示したような、半導体チップ１の周囲を熱硬化性のエポキシ樹脂２で封止するトランスファーモールド技術である。半導体チップ１の支持素材としてリードフレームを用いており、リードフレームのアイランド３に半導体チップ１をダイボンドし、半導体チップ１のボンディングパッドとリード４をワイヤ５でワイヤボンドし、所望の外形形状を具備する金型内にリードフレームをセットし、金型内にエポキシ樹脂を注入、これを硬化させることにより製造される。
【０００３】
一方、各種電子機器に対する小型、軽量化の波はとどまるところを知らず、これらに組み込まれる半導体装置にも、一層の大容量、高機能、高集積化が望まれることになる。
【０００４】
そこで、以前から発想としては存在していた（例えば、特開昭５５ー１１１１５１７号）、１つのパッケージ内に複数の半導体チップを封止する技術が注目され、実現化する動きが出てきた。つまり図６（Ｂ）に示すように、アイランド３上に第１の半導体チップ１ａを固着し、第１の半導体チップ１ａの上に第２の半導体チップ１ｂを固着し、対応するボンディングパッドとリード端子４とをボンディングワイヤ５ａ、５ｂで接続し、樹脂２で封止したものである。
【０００５】
【発明が解決しようとする課題】
図６（Ｂ）の構成は、第１の半導体チップ１ａとのワイヤボンディングを確保するため、第２の半導体チップ１ｂを固着したときに第１の半導体チップ１ａの電極パッド部分が露出していること、即ちチップサイズに差のあることが絶対的な条件となる。そのため、例えば同一機種のチップを２個組み込む、或いは別機種のチップであってもそのチップサイズが近似する場合には採用できない欠点があった。２つの半導体チップを十文字に重ね合わせることも考えられるが、これとてチップサイズの縦×横の寸法に差があることが条件となり、依然として制約が残るものである。
【０００６】
これを解決するために、例えば図６（Ｃ）に示すように、アイランド３の両面に各半導体チップ１ａ、１ｂの裏面が対向するようにこれらを固着する手法がある。しかしながら、ボンディングワイヤのループ高さの分が２倍必要になるので、半導体装置全体の厚み（図６（Ｃ）の図示Ｘ）が増して、薄形化できない欠点がある。
【０００７】
【課題を解決するための手段】
本発明は上述した従来の課題に鑑み成されたもので、第１と第２の半導体チップと、前記第１と第２の半導体チップの各表面に形成した電極パッドと、外部接続用の電極手段と、前記第１と第２の半導体チップの電極パッドと前記電極手段とを各々接続するボンディングワイヤとを具備し、前記第１と第２の半導体チップを重畳して１つのパッケージに封止した半導体装置において、
前記第１の半導体チップの電極パッドの上部が前記第２の半導体チップで覆われるように両者を重畳し、
前記第１の半導体チップの電極パッドの上に位置する第２の半導体チップの裏面を局所的に薄くして凹部を形成し、
前記第１の半導体チップの電極パッドに接続するボンディングワイヤが、前記凹部を通過して前記第１の半導体チップの電極パッドにボンディングされ、
前記第１と第２の半導体チップが絶縁性の接着剤で固着されており、且つ前記接着剤が前記凹部にも達して、前記第２の半導体チップの裏面に接していることを特徴とするものである。
【０００８】
【発明の実施の形態】
以下に本発明の一実施の形態を詳細に説明する。
【０００９】
先ず、図１は本発明の半導体装置の主要部を示す断面図、図２（Ａ）は全体を示す断面図、同じく図２（Ｂ）は全体を示す平面図である。
【００１０】
これらの図において、１０、１１は各々第１と第２の半導体チップを示している。第１と第２の半導体チップ１０、１１のシリコン表面には、前工程において各種の拡散熱処理などによって多数の能動、受動回路素子が形成されている。第１と第２の半導体チップ１０、１１のチップ周辺部分には外部接続用の第１と第２の電極パッド１２ａ、１２ｂがアルミ電極によって形成されている。各電極パッド１２ａ、１２ｂの上にはパッシベーション皮膜が形成され、電極パッド１２ａ、１２ｂの上部が電気接続のために開口されている。パッシベーション被膜はシリコン窒化膜、シリコン酸化膜、ポリイミド系絶縁膜などである。図２（Ｂ）の例では、各電極パッド１２ａ、１２ｂは半導体チップ１０、１１の対向する２辺に沿って集約して配置されている。
【００１１】
第１の半導体チップ１０がリードフレームのアイランド１３上に接着剤１４によりダイボンドされる。第２の半導体チップ１１が第１の半導体チップ１０の前記パッシベーション皮膜上に接着剤１５により固着されている。接着剤１４は導電性または絶縁性、接着剤１５は絶縁性のエポキシ系接着剤である。
【００１２】
第１の電極パッド１２ａには、金線からなる第１のボンディングワイヤ１６ａの一端が接続されており、第１のボンディングワイヤ１６ａの他端は外部導出用のリード端子１７にワイヤボンドされている。また、第２の電極パッド１２ｂの表面には、第２のボンディングワイヤ１６ｂの一端がワイヤボンドされており、第２のボンディングワイヤ１６ｂの他端は外部導出用のリード端子１７にワイヤボンドされている。
【００１３】
第１と第２の半導体チップ１０、１１、リード端子１７の一部、および第１と第２のボンディングワイヤ１６ａ、１６ｂを含む主要部は、周囲をエポキシ系の熱硬化樹脂１８でモールドされて半導体装置のパッケージを形成する。リード端子１７はパッケージの側壁から外部に導出されて外部接続端子となる。導出されたリード端子１７はＺ字型に曲げ加工されている。アイランド１３の裏面側は樹脂１８の表面に露出しており、樹脂１８表面と同一平面を形成している。
【００１４】
第１と第２の半導体チップ１０、１１の組み合わせは任意である。例えば、第１と第２の半導体チップ１０、１１としてＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を用いた場合（第１の組み合わせ例）は、１つのパッケージで記憶容量を２倍、３倍・・・にすることができる。また、第１の半導体チップ１０にＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を、第２の半導体チップ１１にはＳＲＡＭ等の半導体記憶装置を形成するような場合（第２の組み合わせ例）ことも考えられる。どちらの組み合わせの場合でも、各チップにはデータの入出力を行うＩ／Ｏ端子と、データのアドレスを指定するアドレス端子、及びデータの入出力を許可するチップイネーブル端子とを具備しており、両チップのピン配列が酷似している。そのため、第１と第２の半導体チップ１０、１１のＩ／Ｏ端子やアドレス端子用のリード端子１７を共用することが可能であり、各チップに排他的なチップイネーブル信号を印加することにより、どちらか一方の半導体チップのメモリセルを排他的に選択することが可能である。
【００１５】
上記第１の組み合わせ例の場合には当然の事ながら、第１の半導体チップ１０と第２の半導体チップ１１が大略同じ大きさと形状を有し、電極パッド１２ａ、１２ｂの配列も同じである。そのため、両者を重ねると、第１の半導体チップ１０の電極パッド１２ａが第２の半導体チップ１１の陰に隠れる。具体的に、図２（Ｂ）の例では第２の電極パッド１２ｂの直下に第１の電極パッド１２ａが位置する。又第２の組み合わせ例の場合でも、チップサイズと形状が近似し且つピン配列が酷似する場合があり得る。
【００１６】
而して、第２の半導体チップ１２ｂの対向する２辺に沿って、第１の電極パッド１２ａの上方に凹部１９を形成し、第２の半導体チップ１１をひさし状に突出させている。凹部１９は第１の半導体チップ１０の端部から第１の電極１２ａを露出するだけの幅（図１：Ｗ）を持ち、更には第１のボンディングワイヤ１６ａのワイヤ高さ（図１：ｔ１）を収納するだけの高さを持つ。本実施の形態では、第２の半導体チップ１１の裏面をダイシングブレードによって厚みの約半分程度（図１：ｔ２）を研削することにより、前記収納する高さを実現している。尚、前記収納する高さは第１の半導体チップ１０の表面からの高さであるから、接着剤１５の膜厚も考慮してダイシングする深さ（ｔ２）を決定する。
【００１７】
凹部１９は第１の電極パッド１２ａの上方に空間を形成し、この空間内で第１のボンディングワイヤ１６ａが第１の電極パッド１２ａにボールボンディングされている。ボール部２０から連続する第１のボンディングワイヤ１６ａは凹部１９を通過し、リード端子１７にセカンドボンドされる。第１の半導体チップ１０の表面の高さに対してリード端子１７の表面が高いような場合には、第１のボンディングワイヤ１６ａは第１の電極１２ａから凹部１９を通過して横方向に導出され、第２の半導体チップ１１の端より外側で上昇し、リード端子１７先端部に到達する様な軌跡を描く。
【００１８】
接着剤１５は第１と第２の半導体チップ１０、１１の間で両者を固着すると共に、凹部１９にも流出し、第１のボンディングワイヤ１２ａのボール部２０周辺を包み込んで凹部１９を充満するように固化している。固化した接着剤１５は、凹部１９で局所的に薄くされた第２の半導体チップ１１の裏面にも接触し、望ましくは第２の電極パッド１２ｂの下部全体で接触しているのがよい。この状態で接着剤１５が固化することにより、第２の電極パッド１２ｂの下に空間を作らずに済むことになる。そのため、第２の電極パッド１２ｂに第２のボンディングワイヤ１６ｂを接着するときに、固化した接着剤１５が第２の半導体チップ１１を支える役割を果たす。
【００１９】
この様に、凹部１９を設けることによって、第１の半導体チップ１０へのワイヤボンディングを可能にし、且つ第１のボンディングワイヤ１６ａが第２の半導体チップ１１の裏面と接触することを回避している。更に、第１のボンディングワイヤ１６ａを凹部１９を通過させることによって、半導体装置全体の高さ（図１：ｔ３）を薄くすることができる。
【００２０】
加えて、接着剤１５が凹部１９まで拡張して固化させることで、第２の電極パッド１２ｂに対するボンダビリティを向上することができるものである。
【００２１】
本実施の形態では、アイランド１３の板厚が１５０〜２００μであり、第１と第２の半導体チップ１０、１１の厚みがバックグラインド工程により２５０〜３００μとなっている、接着剤１４、１５の厚みとして２０〜３０μ必要であり、更にはボンディングワイヤの上部に樹脂の残り厚みとして１５０〜２００μは必要である。本願出願人は、これらの厚みを収納しつつ、パッケージの高さｔ３を１．０ｍｍ以下にまで薄形化した半導体装置を実現した。
【００２２】
以下に本発明の製品の、製造方法を説明する。
【００２３】
第１工程：図３参照
第１と第２の半導体チップ１０、１１を準備する。これらは前工程によって各種回路素子を形成した半導体ウェハから個々をダイシングして分離する事により得られる。そのうち凹部１９を形成する第２の半導体チップ１１は、ダイシング時において以下の特別な処理を行うことで得ることができる。
【００２４】
先ず、第１主面３０と第２主面３１有する半導体ウェハ３２を準備し、第１主面３０に回路素子を形成する。そして、図３（Ａ）に示したように、第２主面３１側からダイシングラインを認識し、幅広（約１．０ｍｍ）の第１のダイシングブレード３３によって、全体のウェハ厚み２８０μに対して１３０μの深さの溝３４を形成する。ダイシングブレード３３の中心線はダイシングラインの中心線に一致する。次いで、図３（Ｂ）に示したように、ダイシングラインに沿って幅狭（約４０μｍ）の第２のダイシングブレード３５によってウェハ３２を完全に切断する。尚、ハーフダイシングによる溝３４は、凹部１９を設ける箇所だけでも良いし、半導体チップ１０、１１の４辺全てに凹部１９を形成するように設けても良い。また、第２のダイシングブレード３５は第１主面３０側から切削する形態でも良いし、第２主面３１側から切削する形態でも良い。
【００２５】
第２工程：図４（Ａ）参照
半導体チップを固着するためのアイランド１３と外部接続用のリード端子１７を有するリードフレームを準備し、接着剤１４によってアイランド１３の上に第１の半導体チップ１０を固着する。接着剤１４はＡｇペーストのような導電性あるいはエポキシ系の絶縁性の接着剤である。そして、第１の半導体チップ１０の第１の電極１２ａとリード端子１７とを第１のボンディングワイヤ１６ａで接続する。第１のボンディングワイヤ１６ａのワイヤループはできるだけ低く形成するものとする。
【００２６】
第３工程：図４（Ｂ）参照
第１の半導体チップ１０の上に、絶縁性の接着剤１５を塗布する。接着剤１５はエポキシ系の粘性を持つ液状の接着剤であり、ディスペンサー５０からあらかじめ定められた量を供給し、２００℃。数十分のベーキング処理を行う。
第４工程：図４（Ｃ）参照
角錐コレットによって第２の半導体チップ１１を搬送し、第１の半導体チップ１０の上に設置する。この時前記角錐コレットによって第２の半導体チップ１１を数十ｇ／ｃｍ２の圧力で下方に押し下げ、第１と第２の半導体チップ１０、１１の間に接着剤１５を均等な厚みで広げると共に、接着剤１５が凹部１９にまで拡大し、その空間を満たすようにする。この時、拡大した接着剤１５は凹部１９においても第２の半導体チップ１１の裏面５１に接触し、望ましくは第２の電極パッド１２ｂの直下全体で接触しているように形成する。この制御は接着剤１５を塗布したときの量、粘度、ベーキング温度等による。そして、接着剤１５に含まれる有機溶剤を蒸発させ固化させるためのベーキング処理を２００℃、数十分行う。
【００２７】
第５工程：図４（Ｄ）参照
第２の電極パッド１２ｂとリード端子１７とをボールボンディングによりワイヤボンドする。ワイヤの先端にボール５２を形成した第２のボンディングワイヤ１６ｂをキャピラリ５３で押し下げ、第２の電極パッド１２ｂの表面に所定の圧力と超音波振動を与えることによりボール５２を固着し（１ｓｔボンディング）、続いてキャピラリ５３の動作によってリード端子１７に第２のボンディングワイヤ１６ｂを固着する（２ｎｄボンディング）。前記１ｓｔボンディングの時に、凹部１９まで拡張させて固化した接着剤１５が、キャピラリ５３の押し下げる圧力に対する土台となる。これにより、ワイヤボンディング時において第２の半導体チップ１１の凹部１９に割れ、欠けが生じることを防止し、ボンダビリティを改善する。
【００２８】
しかる後、全体を樹脂モールドし、リードフレームから個々の半導体装置を分離して製品が完成する。
【００２９】
図５に第２の実施の形態を示した。リードフレームに代えてテープキャリアと半田ボールを用いた例である。第１の半導体チップ１０がポリイミド系のベースフィルム４０の上に接着固定され、第１の半導体チップ１０の上に第２の半導体チップ１１が固着される。ベースフィルム４０の表面にはリード端子１７に相当する導電パターン４１が形成されており、第１と第２の電極パッド１２ａ、１２ｂと導電パターン４１とが各々第１と第２のボンディングワイヤ１６ａ、１６ｂで接続されている。ベースフィルム４０には貫通穴が形成され、該貫通穴を介して、ベースフィルム４０の裏面に形成した半田ボール４２と接続されている、そして、周囲を熱硬化性の樹脂でモールドされている。
【００３０】
尚、上記実施例は半導体チップが２個の場合を記載したが、３個、４個を積層する場合でも同様に実施できることは言うまでもない。
【００３１】
【発明の効果】
以上に説明した通り、本発明によれば、第２の半導体チップ１１の裏面を研削して凹部１９を設け、凹部１９が形成する空間を利用して第１の電極１２ａに第１のボンディングワイヤ１２ａをボンディングするので、半導体チップ１０、１１の大きさと形状が近似した場合でも複数の半導体チップを積層してワイヤボンディングが可能になる利点を有する。これにより、例えば１つのパッケージに２倍の記憶容量を持たせることが可能になる。
【００３２】
更に、凹部１９を利用することによって第１のボンディングワイヤ１６ａのループ高さを吸収できるので、パッケージの厚みを薄形化できる利点を有する。
【００３３】
更に、接着剤１５を凹部１９にまで拡張し、固化させたことにより、第２の電極パッド１２ｂの下が中空にならない構造にできる。このことにより、ワイヤボンディング時におけるボンダビリティの悪化を防止できる利点を有する。
【００３４】
更に、半導体チップ１０、１１としてどのようなサイズ、形状のものでも組み合わせが可能になり、製品展開の自由度が増す利点をも有する。
【図面の簡単な説明】
【図１】本発明を説明するための断面図である。
【図２】本発明を説明するための（Ａ）断面図、（Ｂ）平面図である。
【図３】凹部１９の製造方法を示す断面図である。
【図４】本発明の製造方法を説明する断面図である。
【図５】本発明の、第２の実施の形態を示す断面図である。
【図６】従来例を説明するための断面図である。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that can be miniaturized even by a combination of semiconductor chips having approximate sizes while superposing and molding a plurality of semiconductor chips.
[0002]
[Prior art]
The most widespread as a sealing technique for a semiconductor device is a transfer mold technique for sealing the periphery of the semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. A lead frame is used as a support material for the semiconductor chip 1, the semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pad of the semiconductor chip 1 and the lead 4 are wire-bonded with the wire 5 to have a desired outer shape. The lead frame is set in a mold to be manufactured, and an epoxy resin is injected into the mold and is cured.
[0003]
On the other hand, the wave of miniaturization and weight reduction for various electronic devices is not limited, and further higher capacity, higher functionality, and higher integration are desired for semiconductor devices incorporated therein.
[0004]
Therefore, a technique that has existed as an idea for a long time (for example, Japanese Patent Application Laid-Open No. 55-1111517) has been attracting attention and a movement to realize it has attracted attention. That is, as shown in FIG. 6B, the first semiconductor chip 1a is fixed on the island 3, the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and leads are fixed. The terminal 4 is connected with bonding wires 5 a and 5 b and sealed with a resin 2.
[0005]
[Problems to be solved by the invention]
In the configuration of FIG. 6B, in order to secure wire bonding with the first semiconductor chip 1a, the electrode pad portion of the first semiconductor chip 1a is exposed when the second semiconductor chip 1b is fixed. That is, the difference in chip size is an absolute condition. For this reason, for example, there are disadvantages that cannot be adopted when two chips of the same model are incorporated, or even if the chip size is similar even if the chips are of different models. It is conceivable to superimpose two semiconductor chips on a cross, but this still requires that there is a difference in the vertical and horizontal dimensions of the chip size, and there are still restrictions.
[0006]
In order to solve this problem, for example, as shown in FIG. 6C, there is a method of fixing these so that the back surfaces of the semiconductor chips 1a and 1b face the both surfaces of the island 3. However, since it is necessary to double the loop height of the bonding wire, the thickness of the entire semiconductor device (shown X in FIG. 6C) increases, and there is a drawback that it cannot be thinned.
[0007]
[Means for Solving the Problems]
The present invention has been made in view of the above-described conventional problems, and includes first and second semiconductor chips, electrode pads formed on the surfaces of the first and second semiconductor chips, and electrodes for external connection. And a bonding wire for connecting the electrode pads of the first and second semiconductor chips and the electrode means, respectively, and the first and second semiconductor chips are overlapped and sealed in one package In the semiconductor device
Both are superimposed so that the upper part of the electrode pad of the first semiconductor chip is covered with the second semiconductor chip,
Forming a recess by locally thinning the back surface of the second semiconductor chip located on the electrode pad of the first semiconductor chip;
A bonding wire connected to the electrode pad of the first semiconductor chip is bonded to the electrode pad of the first semiconductor chip through the recess;
The first and second semiconductor chips are fixed with an insulating adhesive, and the adhesive also reaches the recess and is in contact with the back surface of the second semiconductor chip. Is.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail.
[0009]
First, FIG. 1 is a sectional view showing the main part of the semiconductor device of the present invention, FIG. 2A is a sectional view showing the whole, and FIG. 2B is a plan view showing the whole.
[0010]
In these drawings, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. A large number of active and passive circuit elements are formed on the silicon surfaces of the first and second semiconductor chips 10 and 11 by various diffusion heat treatments in the previous step. First and second electrode pads 12a and 12b for external connection are formed of aluminum electrodes in the peripheral portions of the first and second semiconductor chips 10 and 11. A passivation film is formed on each electrode pad 12a, 12b, and the upper part of electrode pad 12a, 12b is opened for electrical connection. The passivation film is a silicon nitride film, a silicon oxide film, a polyimide insulating film, or the like. In the example of FIG. 2B, the electrode pads 12a and 12b are collectively arranged along two opposing sides of the semiconductor chips 10 and 11.
[0011]
The first semiconductor chip 10 is die-bonded with an adhesive 14 on the island 13 of the lead frame. A second semiconductor chip 11 is fixed on the passivation film of the first semiconductor chip 10 with an adhesive 15. The adhesive 14 is conductive or insulating, and the adhesive 15 is an insulating epoxy adhesive.
[0012]
One end of a first bonding wire 16a made of a gold wire is connected to the first electrode pad 12a, and the other end of the first bonding wire 16a is wire-bonded to an external lead terminal 17. . One end of the second bonding wire 16b is wire-bonded to the surface of the second electrode pad 12b, and the other end of the second bonding wire 16b is wire-bonded to the lead terminal 17 for external lead-out. Yes.
[0013]
The main parts including the first and second semiconductor chips 10 and 11, a part of the lead terminal 17, and the first and second bonding wires 16 a and 16 b are molded with an epoxy-based thermosetting resin 18. A semiconductor device package is formed. The lead terminal 17 is led out from the side wall of the package and becomes an external connection terminal. The derived lead terminal 17 is bent into a Z-shape. The back side of the island 13 is exposed on the surface of the resin 18 and forms the same plane as the surface of the resin 18.
[0014]
The combination of the first and second semiconductor chips 10 and 11 is arbitrary. For example, when a semiconductor storage device such as an EEPROM (flash memory) is used as the first and second semiconductor chips 10 and 11 (first combination example), the storage capacity is doubled, tripled,・ ・In some cases, a semiconductor memory device such as an EEPROM (flash memory) is formed on the first semiconductor chip 10 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 (second combination example). Conceivable. In either combination, each chip has an I / O terminal for inputting / outputting data, an address terminal for designating an address of data, and a chip enable terminal for permitting input / output of data, The pin arrangement of both chips is very similar. Therefore, it is possible to share the I / O terminal of the first and second semiconductor chips 10 and 11 and the lead terminal 17 for the address terminal, and by applying an exclusive chip enable signal to each chip, It is possible to exclusively select the memory cells of either one of the semiconductor chips.
[0015]
In the case of the first combination example, as a matter of course, the first semiconductor chip 10 and the second semiconductor chip 11 have substantially the same size and shape, and the arrangement of the electrode pads 12a and 12b is also the same. Therefore, when both are overlapped, the electrode pad 12 a of the first semiconductor chip 10 is hidden behind the second semiconductor chip 11. Specifically, in the example of FIG. 2B, the first electrode pad 12a is located immediately below the second electrode pad 12b. Even in the case of the second combination example, the chip size and shape may be approximated and the pin arrangement may be very similar.
[0016]
Thus, the concave portion 19 is formed above the first electrode pad 12a along the two opposing sides of the second semiconductor chip 12b, and the second semiconductor chip 11 is projected in an eaves shape. The recess 19 has a width (FIG. 1: W) sufficient to expose the first electrode 12a from the end of the first semiconductor chip 10, and further has a wire height (FIG. 1: t1) of the first bonding wire 16a. ) Enough to store. In the present embodiment, the height of the second semiconductor chip 11 is realized by grinding the back surface of the second semiconductor chip 11 by about a half of the thickness (FIG. 1: t2) with a dicing blade. Since the height to be stored is the height from the surface of the first semiconductor chip 10, the dicing depth (t 2) is determined in consideration of the film thickness of the adhesive 15.
[0017]
The recess 19 forms a space above the first electrode pad 12a, and the first bonding wire 16a is ball-bonded to the first electrode pad 12a in this space. The first bonding wire 16 a continuous from the ball portion 20 passes through the recess 19 and is second-bonded to the lead terminal 17. When the surface of the lead terminal 17 is higher than the height of the surface of the first semiconductor chip 10, the first bonding wire 16a passes through the recess 19 from the first electrode 12a and is led out laterally. Then, a locus is drawn that rises outside the end of the second semiconductor chip 11 and reaches the tip of the lead terminal 17.
[0018]
The adhesive 15 fixes both the first and second semiconductor chips 10 and 11, and also flows out into the recess 19, wraps around the ball portion 20 of the first bonding wire 12 a and fills the recess 19. So that it is solidified. The solidified adhesive 15 is also in contact with the back surface of the second semiconductor chip 11 locally thinned by the recess 19, and preferably in contact with the entire lower portion of the second electrode pad 12 b. When the adhesive 15 is solidified in this state, it is not necessary to create a space under the second electrode pad 12b. Therefore, when the second bonding wire 16 b is bonded to the second electrode pad 12 b, the solidified adhesive 15 plays a role of supporting the second semiconductor chip 11.
[0019]
In this manner, by providing the recess 19, wire bonding to the first semiconductor chip 10 is possible, and the first bonding wire 16 a is prevented from coming into contact with the back surface of the second semiconductor chip 11. . Further, by passing the first bonding wire 16a through the recess 19, the height of the entire semiconductor device (FIG. 1: t3) can be reduced.
[0020]
In addition, the bondability with respect to the second electrode pad 12b can be improved by expanding and solidifying the adhesive 15 to the recess 19.
[0021]
In the present embodiment, the thickness of the island 13 is 150 to 200 μm, and the thickness of the first and second semiconductor chips 10 and 11 is 250 to 300 μm by the back grinding process. The thickness needs to be 20-30 μm, and further, the remaining thickness of the resin needs to be 150-200 μm above the bonding wire. The applicant of the present application has realized a semiconductor device in which the thickness t3 of the package is reduced to 1.0 mm or less while accommodating these thicknesses.
[0022]
The production method of the product of the present invention will be described below.
[0023]
First step: See FIG. 3 First and second semiconductor chips 10 and 11 are prepared. These are obtained by dicing and separating individual semiconductor wafers on which various circuit elements have been formed in the previous process. Among them, the second semiconductor chip 11 in which the recess 19 is formed can be obtained by performing the following special process during dicing.
[0024]
First, a semiconductor wafer 32 having a first main surface 30 and a second main surface 31 is prepared, and circuit elements are formed on the first main surface 30. Then, as shown in FIG. 3A, the dicing line is recognized from the second main surface 31 side, and a wide (about 1.0 mm) first dicing blade 33 is used for the entire wafer thickness of 280 μm. A groove 34 having a depth of 130 μ is formed. The center line of the dicing blade 33 coincides with the center line of the dicing line. Next, as shown in FIG. 3B, the wafer 32 is completely cut by the second dicing blade 35 having a narrow width (about 40 μm) along the dicing line. Note that the groove 34 by half dicing may be provided only at a location where the recess 19 is provided, or may be provided so that the recess 19 is formed on all four sides of the semiconductor chips 10 and 11. Further, the second dicing blade 35 may be cut from the first main surface 30 side or may be cut from the second main surface 31 side.
[0025]
Second Step: See FIG. 4A. A lead frame having an island 13 for fixing the semiconductor chip and a lead terminal 17 for external connection is prepared, and the first semiconductor chip 10 is formed on the island 13 by an adhesive 14. To fix. The adhesive 14 is a conductive or epoxy insulating adhesive such as an Ag paste. Then, the first electrode 12a of the first semiconductor chip 10 and the lead terminal 17 are connected by the first bonding wire 16a. The wire loop of the first bonding wire 16a is formed as low as possible.
[0026]
Third step: See FIG. 4B. An insulating adhesive 15 is applied on the first semiconductor chip 10. The adhesive 15 is a liquid adhesive having an epoxy-based viscosity, and is supplied in a predetermined amount from the dispenser 50 at 200 ° C. Do several tens of minutes of baking.
4th process: The 2nd semiconductor chip 11 is conveyed with the pyramid collet with reference to FIG.4 (C), and it installs on the 1st semiconductor chip 10. FIG. At this time, the pyramid collet pushes down the second semiconductor chip 11 with a pressure of several tens of g / cm 2, spreads the adhesive 15 between the first and second semiconductor chips 10 and 11 with an equal thickness, The adhesive 15 expands to the recess 19 so as to fill the space. At this time, the enlarged adhesive 15 is formed so as to be in contact with the back surface 51 of the second semiconductor chip 11 also in the recess 19, and preferably in contact with the entire area directly below the second electrode pad 12 b. This control depends on the amount when the adhesive 15 is applied, the viscosity, the baking temperature, and the like. Then, baking treatment for evaporating and solidifying the organic solvent contained in the adhesive 15 is performed at 200 ° C. for several tens of minutes.
[0027]
Fifth step: See FIG. 4D. The second electrode pad 12b and the lead terminal 17 are wire-bonded by ball bonding. The second bonding wire 16b in which the ball 52 is formed at the tip of the wire is pushed down by the capillary 53, and the ball 52 is fixed by applying predetermined pressure and ultrasonic vibration to the surface of the second electrode pad 12b (1st bonding). Subsequently, the second bonding wire 16b is fixed to the lead terminal 17 by the operation of the capillary 53 (2nd bonding). At the time of the first bonding, the adhesive 15 that has been expanded and solidified to the concave portion 19 serves as a foundation for the pressure to push down the capillary 53. As a result, the concave portion 19 of the second semiconductor chip 11 is prevented from being cracked or chipped during wire bonding, and bondability is improved.
[0028]
Thereafter, the whole is resin-molded, and individual semiconductor devices are separated from the lead frame to complete the product.
[0029]
FIG. 5 shows a second embodiment. In this example, a tape carrier and solder balls are used instead of the lead frame. The first semiconductor chip 10 is bonded and fixed onto the polyimide base film 40, and the second semiconductor chip 11 is fixed onto the first semiconductor chip 10. A conductive pattern 41 corresponding to the lead terminal 17 is formed on the surface of the base film 40, and the first and second electrode pads 12a, 12b and the conductive pattern 41 are respectively connected to the first and second bonding wires 16a, 16b. A through hole is formed in the base film 40 and connected to a solder ball 42 formed on the back surface of the base film 40 through the through hole, and the periphery is molded with a thermosetting resin.
[0030]
In the above embodiment, the case where there are two semiconductor chips is described, but it goes without saying that the present invention can be similarly implemented even when three or four semiconductor chips are stacked.
[0031]
【The invention's effect】
As described above, according to the present invention, the back surface of the second semiconductor chip 11 is ground to provide the recess 19, and the first bonding wire is applied to the first electrode 12 a using the space formed by the recess 19. Since 12a is bonded, there is an advantage that even when the sizes and shapes of the semiconductor chips 10 and 11 are approximated, a plurality of semiconductor chips can be stacked to perform wire bonding. As a result, for example, one package can have twice the storage capacity.
[0032]
Furthermore, since the loop height of the first bonding wire 16a can be absorbed by using the recess 19, there is an advantage that the thickness of the package can be reduced.
[0033]
Further, the adhesive 15 is expanded to the recess 19 and solidified, so that the structure below the second electrode pad 12b is not hollow. This has the advantage that deterioration of bondability during wire bonding can be prevented.
[0034]
Further, any size and shape of the semiconductor chips 10 and 11 can be combined, and there is an advantage that the degree of freedom of product development is increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining the present invention.
2A is a sectional view and FIG. 2B is a plan view for explaining the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing the recess 19;
FIG. 4 is a cross-sectional view illustrating the manufacturing method of the present invention.
FIG. 5 is a cross-sectional view showing a second embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (4)

第１の半導体チップ及び前記第１の半導体チップ上に積層して接着剤により固着された第２の半導体チップと、前記第１及び第２の半導体チップの各第１主面に形成された電極パッドと、前記電極パッドの各々とボンディングワイヤにより電気的に接続された外部接続用の電極手段と、前記第１及び第２の半導体チップを樹脂モールドして形成されたパッケージと、を具備し、A first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip and fixed by an adhesive, and electrodes formed on the first main surfaces of the first and second semiconductor chips A pad, an electrode means for external connection electrically connected to each of the electrode pads by a bonding wire, and a package formed by resin-molding the first and second semiconductor chips,
少なくとも前記第１の半導体チップの電極パッド上方に位置する前記第２の半導体チップの第２主面には、その周囲に凹部が形成され、  A recess is formed around the second main surface of the second semiconductor chip located at least above the electrode pad of the first semiconductor chip,
前記第１の半導体チップの電極パッドと前記電極手段とを接続するボンディングワイヤの接続部は、前記第１の半導体チップと前記凹部とで形成される空間内に配置され、  A connecting portion of a bonding wire that connects the electrode pad of the first semiconductor chip and the electrode means is disposed in a space formed by the first semiconductor chip and the recess,
前記接着剤は、前記接続部を覆い、且つ前記凹部に位置する前記第２の半導体チップの第２主面に接触するように、前記空間を充填していることを特徴とする半導体装置。  The semiconductor device is characterized in that the adhesive fills the space so as to cover the connection portion and to contact a second main surface of the second semiconductor chip located in the recess. 前記電極手段は、前記パッケージから導出されたリード端子、または前記第１の半導体チップが固着されるフィルム上に形成された導電パターンであることを特徴とする請求項１に記載の半導体装置。The semiconductor device according to claim 1, wherein the electrode means is a lead pattern derived from the package or a conductive pattern formed on a film to which the first semiconductor chip is fixed. 第１の半導体チップを準備し、所定の固着部に前記第１の半導体チップを固着し、前記第１の半導体チップの電極パッドと外部接続用の電極手段とをボンディングワイヤで接続した後、前記第１の半導体チップの第１主面に接着剤を塗布する工程と、After preparing a first semiconductor chip, fixing the first semiconductor chip to a predetermined fixing portion, and connecting an electrode pad of the first semiconductor chip and an electrode means for external connection with a bonding wire, Applying an adhesive to the first main surface of the first semiconductor chip;
第１主面に電極パッドが形成され、該電極パッドの下方に位置する第２主面の周囲に凹部が形成された第２の半導体チップを準備し、前記第２の半導体チップの電極パッド下方まで前記接着剤が充填するように、前記第２の半導体チップにより前記接着剤を押し広げながら、前記第１の半導体チップ上に第２の半導体チップを固着する工程と、  A second semiconductor chip is prepared in which an electrode pad is formed on the first main surface, and a recess is formed around the second main surface located below the electrode pad, and below the electrode pad of the second semiconductor chip Fixing the second semiconductor chip on the first semiconductor chip while spreading the adhesive by the second semiconductor chip so that the adhesive is filled up to,
前記第２の半導体チップの電極パッド下方を固化した前記接着剤により支持した状態で、前記第２の半導体チップの電極パッドと外部接続用の電極手段とをボンディングワイヤで接続した後、前記第１及び第２の半導体チップを樹脂モールドし、パッケージに封止する工程と、を具備することを特徴とする半導体装置の製造方法。  After the electrode pad of the second semiconductor chip and the electrode means for external connection are connected by a bonding wire in a state where the lower part of the electrode pad of the second semiconductor chip is supported by the solidified adhesive, the first semiconductor chip And a step of resin-molding the second semiconductor chip and sealing it in a package. 第１主面及び第２主面を有する半導体ウエハを準備し、第１のダイシングブレードを用いて、前記第２主面側からダイシングラインに沿ってハーフダイシングを行った後、前記第１のダイシングブレードより幅狭な第２のダイシングブレードを用いて、前記第２主面側から前記ハーフダイシングした領域をダイシングし、前記半導体ウエハを個々の半導体チップに分離し、前記半導体チップの第２主面の周囲に前記凹部を形成する工程と、を具備することを特徴とする請求項３に記載の半導体装置の製造方法。A semiconductor wafer having a first main surface and a second main surface is prepared, and half dicing is performed along a dicing line from the second main surface side using a first dicing blade, and then the first dicing is performed. Using a second dicing blade narrower than the blade, the half-diced region is diced from the second main surface side, the semiconductor wafer is separated into individual semiconductor chips, and the second main surface of the semiconductor chip Forming the recess around the periphery of the semiconductor device. The method of manufacturing a semiconductor device according to claim 3.
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