JP2001332684A - Resin-sealed semiconductor device and manufacturing method thereof - Google Patents
Resin-sealed semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2001332684A JP2001332684A JP2000149253A JP2000149253A JP2001332684A JP 2001332684 A JP2001332684 A JP 2001332684A JP 2000149253 A JP2000149253 A JP 2000149253A JP 2000149253 A JP2000149253 A JP 2000149253A JP 2001332684 A JP2001332684 A JP 2001332684A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- semiconductor device
- lead frame
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、複数のチップを
高密度に収納するため、１つのチップをＬＯＣ型、他の
チップをＣＯＬ型にして、２つ以上のチップを１つのパ
ッケージに収納することで、高密度化を達成した樹脂封
止型半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention accommodates a plurality of chips at a high density by setting one chip to a LOC type and the other chip to a COL type to store two or more chips in one package. Thus, the present invention relates to a resin-encapsulated semiconductor device that has achieved high density.
【０００２】[0002]
【従来の技術】図８は、従来の樹脂封止型半導体装置を
示す断面図である。この樹脂封止型半導体装置は、電極
を兼ねたリード１１の上下両面に接着部材であるポリイ
ミドテープ１２，１３がそれぞれ設けられ、そのリード
１１の下面側のポリイミドテープ１３によって半導体チ
ップ１４が固定されている。この半導体チップ１４の上
面にはポリイミドテープ１５が設けられ、さらに半導体
チップ１４上の電極とリード１１の上面とがボンディン
グワイヤ１６を介して接合されている。2. Description of the Related Art FIG. 8 is a sectional view showing a conventional resin-sealed semiconductor device. In this resin-encapsulated semiconductor device, polyimide tapes 12 and 13 as adhesive members are respectively provided on the upper and lower surfaces of a lead 11 also serving as an electrode, and a semiconductor chip 14 is fixed by the polyimide tape 13 on the lower surface side of the lead 11. ing. A polyimide tape 15 is provided on the upper surface of the semiconductor chip 14, and the electrodes on the semiconductor chip 14 are bonded to the upper surfaces of the leads 11 via bonding wires 16.
【０００３】さらに、リード１１の上面側のポリイミド
テープ１２と、半導体チップ１４の上面に設けられたポ
リイミドテープ１５とにより、リード１１の上面側に半
導体チップ１７が固定され、該半導体チップ１７上の電
極とリード１１の上面側とがボンディングワイヤ１８を
介して接合されている。そして、リード１１の一部を外
部に引き出す形で、半導体チップ１４，１７を含む全体
が樹脂１９によってモールドされている。Further, a semiconductor chip 17 is fixed on the upper surface side of the lead 11 by a polyimide tape 12 on the upper surface side of the lead 11 and a polyimide tape 15 provided on the upper surface of the semiconductor chip 14. The electrode and the upper surface of the lead 11 are joined via a bonding wire 18. Then, the entirety including the semiconductor chips 14 and 17 is molded with the resin 19 so that a part of the lead 11 is pulled out to the outside.
【０００４】[0004]
【発明が解決しようとする課題】従来の樹脂封止型半導
体装置は以上のように構成されていたので、チップ，ダ
イボンド層の厚さ、フレームリードの厚さが全て集積さ
れ、結果として半導体装置全体の高さを増加させてい
た。また、この高さを抑制するため、チップを薄く研磨
する等の手段で全体の高さを抑える方法がとられていた
が、この方法ではそれぞれのチップの布線は２回に分け
て実施する必要があるという問題点があった。さらに、
第１のチップの布線のダメージ防止や第２のチップとの
電気的接触を防止するため、厚いスペーサをチップ間に
挿入することが必要であるという問題点もあった。Since the conventional resin-encapsulated semiconductor device is constructed as described above, the thickness of the chip, the die bond layer, and the thickness of the frame lead are all integrated, resulting in the semiconductor device. Had increased the overall height. Further, in order to suppress this height, a method of suppressing the entire height by means such as polishing the chip thinly has been adopted. However, in this method, the wiring of each chip is performed twice. There was a problem that it was necessary. further,
There is also a problem that it is necessary to insert a thick spacer between the chips to prevent damage to the wiring of the first chip and to prevent electrical contact with the second chip.
【０００５】この発明は上記のような問題点を解決する
ためになされたものであり、スタック型実装ＩＣの全高
を抑え、パッケージ全体を薄型にすることを目的とす
る。The present invention has been made to solve the above problems, and has as its object to reduce the overall height of a stack type mounting IC and reduce the thickness of the entire package.
【０００６】[0006]
【課題を解決するための手段】この発明の請求項１に係
る樹脂封止型半導体装置は、複数のチップをリードフレ
ームを挟んで積層するとともに、チップとリードフレー
ムとを布線し、全体を封止樹脂で覆ったものであって、
リードフレームの先端部分であって、チップと接触する
部分を薄く構成したものである。According to a first aspect of the present invention, there is provided a resin-encapsulated semiconductor device in which a plurality of chips are stacked with a lead frame interposed therebetween, and the chips and the lead frame are wired. Covered with a sealing resin,
The tip portion of the lead frame, which is in contact with the chip, is made thin.
【０００７】この発明の請求項２に係る樹脂封止型半導
体装置は、複数のチップをリードフレームを挟んで積層
するとともに、チップとリードフレームとを布線し、全
体を封止樹脂で覆ったものであって、リードフレームの
先端部分であって、チップと接触する部分を折り曲げて
構成したものである。In a resin-sealed semiconductor device according to a second aspect of the present invention, a plurality of chips are stacked with a lead frame interposed therebetween, the chips and the lead frame are wired, and the whole is covered with a sealing resin. In this structure, a tip portion of a lead frame, which is in contact with a chip, is bent.
【０００８】この発明の請求項３に係る樹脂封止型半導
体装置は、下部のチップとして中央に電極を有するメモ
リを配置し、上部のチップとしてロジック等の大型チッ
プを配置したものである。According to a third aspect of the present invention, there is provided a resin-encapsulated semiconductor device in which a memory having an electrode in the center is arranged as a lower chip, and a large chip such as logic is arranged as an upper chip.
【０００９】この発明の請求項４に係る樹脂封止型半導
体装置は、封止樹脂中に配合したフィラの粒径をチップ
間隔より小さく構成したものである。According to a fourth aspect of the present invention, there is provided a resin-encapsulated semiconductor device in which a filler mixed in the encapsulating resin has a particle diameter smaller than a chip interval.
【００１０】この発明の請求項５に係る樹脂封止型半導
体装置の製造方法は、複数のチップを同時に布線するも
のである。According to a fifth aspect of the present invention, there is provided a method of manufacturing a resin-encapsulated semiconductor device, in which a plurality of chips are simultaneously wired.
【００１１】[0011]
【発明の実施の形態】実施の形態１．以下、この発明の
一実施形態を図に基づいて説明する。図１はこの発明の
実施の形態１によるＴＳＯＰ形の樹脂封止型半導体装置
を示す断面図、図２は同じく平面図である。図におい
て、１は第１のチップ、２は第２のチップ、３はリード
フレーム、１ａ，２ａはそれぞれ第１のチップ１及び第
２のチップ２とリードフレーム３とを接続する布線、４
は第１のチップ１とリードフレーム３とを固着する固着
テープ（ＬＯＣ型）、５は第２のチップ２とリードフレ
ーム３とを固着するための固着テープ（ＣＯＬ型）、６
は全体を覆う封止樹脂、７は封止樹脂６中に混合された
フィラ群であり、フィラの粒径は第１のチップ１と第２
のチップ２との間隔より小さく形成している。又、図３
は固着テープ４を第１のチップ１に貼り付けた状態を示
す平面図であり、固着テープ４は第１のチップ１の電極
を避けるとともに、リードフレーム３の下部を支える形
状をしている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a TSOP type resin-sealed semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a plan view of the same. In the drawing, 1 is a first chip, 2 is a second chip, 3 is a lead frame, 1a and 2a are wirings for connecting the first chip 1 and the second chip 2 to the lead frame 3, respectively.
Is a fixing tape (LOC type) for fixing the first chip 1 and the lead frame 3; 5 is a fixing tape (COL type) for fixing the second chip 2 and the lead frame 3;
Is a sealing resin covering the whole, 7 is a filler group mixed in the sealing resin 6, and the particle size of the filler is the first chip 1 and the second chip.
Is formed smaller than the distance from the chip 2. FIG.
FIG. 3 is a plan view showing a state in which the fixing tape 4 is attached to the first chip 1. The fixing tape 4 is shaped to support the lower part of the lead frame 3 while avoiding the electrodes of the first chip 1.
【００１２】第１のチップ１は、先端部が薄くされたリ
ードフレーム３にＬＯＣ（Lead onChip）方式で第１の
チップ１上に設けられたパッド（電極）を回避するよう
に配設され、リードフレーム３の先端部に固着テープ４
等のダイボンド材によって固着されている。さらに、第
１のチップ１上に設けられた電極と、所定のリードフレ
ーム３の部位とを金線等の布線１ａで電気的に接続して
いる。第２のチップ２は、リードフレーム３にＣＯＬ
（Chip on Lead）方式により、固着テープ５等で固着
され、それぞれ所定の部位間を金線等の布線２ａで接続
されている。The first chip 1 is disposed on a lead frame 3 having a thinned tip so as to avoid pads (electrodes) provided on the first chip 1 by a LOC (Lead on Chip) method. Sticking tape 4 to the end of lead frame 3
And the like. Further, the electrode provided on the first chip 1 and a predetermined part of the lead frame 3 are electrically connected by a wiring 1a such as a gold wire. The second chip 2 has COL
By a (Chip on Lead) method, the components are fixed with a fixing tape 5 or the like, and predetermined portions are connected to each other with a wiring 2a such as a gold wire.
【００１３】更に図２に示すように、第１のチップ１の
電極が上面より露見する程、第２のチップ２が小さい場
合は、布線１ａ，２ａのボンディング作業は、２回に分
けることなく、１回のボンディング工程によって、あた
かも一チップのごとく作業が実施できるようになる。こ
のように、リードフレーム３先端部を薄くした部位に、
第１と第２のチップ１，２をダイボンド（フレームへの
固着）したことにより、半導体装置の全体を薄くでき
る。また、リードフレーム３の先端を薄くしたことによ
るリードフレーム３の強度不足に関しては、リードフレ
ーム３の先端部をチップ１，２に接続固着することによ
り一体構造化したので、ワイヤボンディング中にも十分
な剛性を有する構造となる。Further, as shown in FIG. 2, when the second chip 2 is small enough that the electrodes of the first chip 1 are exposed from the upper surface, the bonding operation of the wirings 1a and 2a is divided into two. Instead, the operation can be performed as if it were one chip by one bonding process. In this way, at the part where the tip of the lead frame 3 is thinned,
Since the first and second chips 1 and 2 are die-bonded (fixed to a frame), the entire semiconductor device can be thinned. Regarding insufficient strength of the lead frame 3 due to thinning of the tip of the lead frame 3, the leading end of the lead frame 3 is connected and fixed to the chips 1 and 2 to form an integral structure. The structure has high rigidity.
【００１４】さらに、第１のチップ１の布線１ａはリー
ドフレーム３の間にあるため、第２のチップ２をＣＯＬ
方式でリードフレーム３に固着したときも、布線１ａと
第２のチップ２との電気的な接触回避が容易であり、特
開平８−１０７１７８号公報に示されたスペーサ作用を
するポリイミドテープ等の厚いテープ材を必要としな
い。Further, since the wiring 1a of the first chip 1 is located between the lead frames 3, the second chip 2 is
Even when it is fixed to the lead frame 3 by the method, the electrical contact between the wiring 1a and the second chip 2 can be easily avoided, and a polyimide tape or the like which acts as a spacer as disclosed in JP-A-8-107178 Does not require thick tape material.
【００１５】実施の形態２．図４，図５はこの発明の実
施の形態２による樹脂封止型半導体装置を示す断面図、
図６，図７は同じく平面図である。図４においては、ほ
ぼ同一サイズのチップ１，２を重ねて組立てる場合であ
り、第１のチップ１の布線１ａの間隔を十分にとるた
め、リードフレーム３の先端を曲げ加工し、第１，第２
のチップ１，２をそれぞれＬＯＣ，ＣＯＬ方式でリード
フレーム３に固定したものである。第２のチップ２は、
先端曲げ加工を施されたリードフレーム３の端面部に固
着されている。Embodiment 2 4 and 5 are sectional views showing a resin-sealed semiconductor device according to a second embodiment of the present invention.
6 and 7 are plan views of the same. FIG. 4 shows a case where the chips 1 and 2 of substantially the same size are stacked and assembled. In order to secure a sufficient space between the wiring lines 1a of the first chip 1, the tip of the lead frame 3 is bent and the first chip 1 is bent. , Second
Are fixed to the lead frame 3 by the LOC and COL systems, respectively. The second chip 2
The lead frame 3 is fixed to the end face of the lead frame 3 which has been subjected to the bending process.
【００１６】また、第１のチップ１の電極がチップの中
央に設けられたメモリ等では、図５に示したように、リ
ードフレーム３のリード先端をチップ１内部に届くよう
に加工し、第１のチップ１をメモリ、第２のチップ２を
ロジック等大型で多ピンを必要とするものに構成し、ス
タック構造にしたものである。このように組み合わせる
チップの特徴により、リードフレーム３の先端の形状を
最適化することにより、多機能な半導体装置を極めて小
型で提供できる。In a memory or the like in which the electrode of the first chip 1 is provided at the center of the chip, as shown in FIG. 5, the leading end of the lead of the lead frame 3 is processed so as to reach the inside of the chip 1. One chip 1 is configured as a memory, and the second chip 2 is configured as a large-sized, multi-pin requiring device such as a logic, and has a stack structure. By optimizing the shape of the tip of the lead frame 3 by the characteristics of the chips combined in this manner, a multifunctional semiconductor device can be provided in an extremely small size.
【００１７】図６においては、第１のチップ１との接合
用端子群の状況を示しており、また図７においては、第
１のチップ１が長尺の場合、安定的に固着するため、電
気的接続を必要としないダミー端子３ａを設けた場合を
示している。図示はしていないが、上下のリードフレー
ム３を第１のチップ１上面まで延在させ、さらに安定的
に固着することもできる。更に、このダミー端子３ａ
は、例えばロジックチップ等の第２のチップ２への電気
的接続用としても用いることができる。FIG. 6 shows the condition of the terminal group for joining to the first chip 1. In FIG. 7, when the first chip 1 is long, it is stably fixed. This shows a case where dummy terminals 3a that do not require electrical connection are provided. Although not shown, the upper and lower lead frames 3 can be extended to the upper surface of the first chip 1 and fixed more stably. Further, the dummy terminal 3a
Can also be used for electrical connection to the second chip 2 such as a logic chip.
【００１８】[0018]
【発明の効果】この発明の請求項１に係る樹脂封止型半
導体装置によれば、複数のチップをリードフレームを挟
んで積層するとともに、チップとリードフレームとを布
線し、全体を封止樹脂で覆ったものであって、リードフ
レームの先端部分であって、チップと接触する部分を薄
く構成したので、半導体装置全体を薄く構成することが
できる。According to the resin-encapsulated semiconductor device according to the first aspect of the present invention, a plurality of chips are stacked with the lead frame interposed therebetween, and the chips and the lead frame are wired and the whole is sealed. Since the portion which is covered with resin and which is in contact with the chip, that is, the tip portion of the lead frame, is formed thin, the whole semiconductor device can be formed thin.
【００１９】この発明の請求項２に係る樹脂封止型半導
体装置によれば、複数のチップをリードフレームを挟ん
で積層するとともに、チップとリードフレームとを布線
し、全体を封止樹脂で覆ったものであって、リードフレ
ームの先端部分であって、チップと接触する部分を折り
曲げて構成したので、封止樹脂中に配材したフィラの影
響を回避し、信頼性の高い半導体装置を提供することが
できる。According to the resin-sealed semiconductor device of the second aspect of the present invention, a plurality of chips are stacked with the lead frame interposed therebetween, and the chips and the lead frame are wired, and the whole is made of sealing resin. It is covered, and the tip of the lead frame, which is in contact with the chip, is bent, so that the effect of fillers distributed in the sealing resin is avoided, and a highly reliable semiconductor device is provided. Can be provided.
【００２０】この発明の請求項３に係る樹脂封止型半導
体装置によれば、下部のチップとして中央に電極を有す
るメモリを配置し、上部のチップとしてロジック等の大
型チップを配置したので、多機能な半導体装置を極めて
小型で提供することができる。According to the resin-encapsulated semiconductor device of the third aspect of the present invention, a memory having an electrode at the center is arranged as a lower chip, and a large chip such as a logic is arranged as an upper chip. An extremely small functional semiconductor device can be provided.
【００２１】この発明の請求項４に係る樹脂封止型半導
体装置によれば、封止樹脂中に配合したフィラの粒径を
チップ間隔より小さく構成したので、チップへの圧力を
緩和することができる。According to the resin-encapsulated semiconductor device of the fourth aspect of the present invention, since the particle diameter of the filler mixed in the encapsulation resin is made smaller than the chip interval, the pressure on the chip can be reduced. it can.
【００２２】この発明の請求項５に係る樹脂封止型半導
体装置の製造方法によれば、複数のチップを同時に布線
するので、作業を簡略化することができる。According to the method of manufacturing a resin-encapsulated semiconductor device according to the fifth aspect of the present invention, since a plurality of chips are wired at the same time, the operation can be simplified.
【図１】 この発明の実施の形態１による樹脂封止型半
導体装置を示す断面図である。FIG. 1 is a sectional view showing a resin-sealed semiconductor device according to a first embodiment of the present invention.
【図２】 この発明の実施の形態１による樹脂封止型半
導体装置を示す平面図である。FIG. 2 is a plan view showing the resin-sealed semiconductor device according to the first embodiment of the present invention.
【図３】 テープの形状を示す断面図である。FIG. 3 is a sectional view showing the shape of a tape.
【図４】 この発明の実施の形態２による樹脂封止型半
導体装置を示す断面図である。FIG. 4 is a sectional view showing a resin-sealed semiconductor device according to a second embodiment of the present invention;
【図５】 この発明の実施の形態２による樹脂封止型半
導体装置を示す断面図である。FIG. 5 is a sectional view showing a resin-sealed semiconductor device according to a second embodiment of the present invention.
【図６】 この発明の実施の形態２による樹脂封止型半
導体装置を示す平面図である。FIG. 6 is a plan view showing a resin-sealed semiconductor device according to a second embodiment of the present invention.
【図７】 この発明の実施の形態２による樹脂封止型半
導体装置を示す平面図である。FIG. 7 is a plan view showing a resin-sealed semiconductor device according to a second embodiment of the present invention.
【図８】 従来の樹脂封止型半導体装置を示す断面図で
ある。FIG. 8 is a sectional view showing a conventional resin-encapsulated semiconductor device.
１，２ チップ、３ リードフレーム、６ 封止樹脂、
７ フィラ。1, 2 chips, 3 lead frames, 6 sealing resin,
7 Fira.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 板東 晃司 東京都千代田区丸の内二丁目２番３号 三 菱電機株式会社内 Ｆターム(参考） 5F044 AA01 AA19 GG03 5F067 AA01 AA18 AB02 BB04 BB08 BE10 CC02 CC08 CD01 DF02 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Koji Bando, Inventor 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5F044 AA01 AA19 GG03 5F067 AA01 AA18 AB02 BB04 BB08 BE10 CC02 CC08 CD01 DF02
Claims (5)
積層するとともに、上記チップとリードフレームとを布
線し、全体を封止樹脂で覆った樹脂封止型半導体装置に
おいて、上記リードフレームの先端部分であって、上記
チップと接触する部分を薄く構成したことを特徴とする
樹脂封止型半導体装置。1. A resin-encapsulated semiconductor device in which a plurality of chips are stacked with a lead frame interposed therebetween, the chips and the lead frame are wired, and the whole is covered with a sealing resin. A resin-encapsulated semiconductor device, wherein a portion that contacts the chip is configured to be thin.
積層するとともに、上記チップとリードフレームとを布
線し、全体を封止樹脂で覆った樹脂封止型半導体装置に
おいて、上記リードフレームの先端部分であって、上記
チップと接触する部分を折り曲げて構成したことを特徴
とする樹脂封止型半導体装置。2. A resin-encapsulated semiconductor device in which a plurality of chips are stacked with a lead frame interposed therebetween, the chips and the lead frame are wired, and the whole is covered with a sealing resin. A resin-encapsulated semiconductor device, wherein a portion that contacts the chip is bent.
メモリを配置し、上部のチップとしてロジック等の大型
チップを配置したことを特徴とする請求項２記載の樹脂
封止型半導体装置。3. The resin-encapsulated semiconductor device according to claim 2, wherein a memory having an electrode in the center is disposed as a lower chip, and a large chip such as a logic is disposed as an upper chip.
ップ間隔より小さく構成したことを特徴とする請求項１
から請求項３のいずれか1項に記載の樹脂封止型半導体
装置。4. The filler according to claim 1, wherein the filler has a particle diameter smaller than a chip interval.
The resin-sealed semiconductor device according to any one of claims 1 to 3.
記載の樹脂封止型半導体装置の製造方法であって、複数
のチップを同時に布線することを特徴とする樹脂封止型
半導体装置の製造方法。5. The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein a plurality of chips are wired simultaneously. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000149253A JP2001332684A (en) | 2000-05-22 | 2000-05-22 | Resin-sealed semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000149253A JP2001332684A (en) | 2000-05-22 | 2000-05-22 | Resin-sealed semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001332684A true JP2001332684A (en) | 2001-11-30 |
Family
ID=18655138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000149253A Pending JP2001332684A (en) | 2000-05-22 | 2000-05-22 | Resin-sealed semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001332684A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007157826A (en) * | 2005-12-01 | 2007-06-21 | Oki Electric Ind Co Ltd | Semiconductor device, manufacturing method thereof, and lead frame thereof |
| US7368320B2 (en) | 2003-08-29 | 2008-05-06 | Micron Technology, Inc. | Method of fabricating a two die semiconductor assembly |
| JP2009111401A (en) * | 2001-12-27 | 2009-05-21 | Samsung Electronics Co Ltd | Stack semiconductor chip package |
| WO2011030516A1 (en) * | 2009-09-08 | 2011-03-17 | 住友ベークライト株式会社 | Semiconductor device |
-
2000
- 2000-05-22 JP JP2000149253A patent/JP2001332684A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009111401A (en) * | 2001-12-27 | 2009-05-21 | Samsung Electronics Co Ltd | Stack semiconductor chip package |
| US7368320B2 (en) | 2003-08-29 | 2008-05-06 | Micron Technology, Inc. | Method of fabricating a two die semiconductor assembly |
| US7372129B2 (en) | 2003-08-29 | 2008-05-13 | Micron Technology, Inc. | Two die semiconductor assembly and system including same |
| JP2007157826A (en) * | 2005-12-01 | 2007-06-21 | Oki Electric Ind Co Ltd | Semiconductor device, manufacturing method thereof, and lead frame thereof |
| WO2011030516A1 (en) * | 2009-09-08 | 2011-03-17 | 住友ベークライト株式会社 | Semiconductor device |
| US8766420B2 (en) | 2009-09-08 | 2014-07-01 | Sumitomo Bakelite Co., Ltd. | Semiconductor device |
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