JP2009100005A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems relating to a yield and reliability caused by the cracks of a glass substrate or the like due to the exposure of the entire cutting area during dicing, in a method of manufacturing a semiconductor device, which has a process of bonding the glass substrate on the first surface of a semiconductor substrate, and etching the semiconductor substrate from the second surface of the semiconductor substrate. <P>SOLUTION: In the method of manufacturing the semiconductor device, as shown in Fig. 12, in a semiconductor substrate 302, a window 303 which can expose first wiring 301 and the cutting area 304 during dicing is formed only in a region where the first wiring 301 is present. This increases a region where the semiconductor substrate 302 and the glass substrate not shown are bonded through an insulating film or resin, and prevents the occurrence of the cracks or peeling. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a package having an outer dimension approximately the same as the outer dimension of a semiconductor chip.

  In recent years, CSP (Chip Size Package) has attracted attention as a package technology. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip. Conventionally, a BGA type semiconductor device is known as a kind of CSP. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package, and electrically connected to a semiconductor chip formed on the other surface of the package. Is connected to.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such a BGA type semiconductor device is provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. And has the advantage of being able to be downsized. This BGA type semiconductor device has an application as an image sensor chip of a digital camera mounted on a mobile phone, for example.

  FIG. 13 shows a schematic configuration of a conventional BGA type semiconductor device, and FIG. 13A is a perspective view of the surface side of this BGA type semiconductor device. FIG. 13B is a perspective view of the back side of the BGA type semiconductor device.

  In the BGA type semiconductor device 100, the semiconductor chip 101 is sealed between the first and second glass substrates 104a and 104b via resins 105a and 105b. On one main surface of the second glass substrate 104b, that is, on the back surface of the BGA type semiconductor device 100, a plurality of ball-shaped terminals (hereinafter referred to as conductive terminals 111) are arranged in a lattice shape. The conductive terminal 111 is connected to the semiconductor chip 101 via the second wiring 109. Aluminum wires drawn from the inside of the semiconductor chip 101 are connected to the plurality of second wirings 109, respectively, and electrical connection between each conductive terminal 111 and the semiconductor chip 101 is made.

  The cross-sectional structure of the BGA type semiconductor device 100 will be described in more detail with reference to FIG. FIG. 14 shows a cross-sectional view of the BGA type semiconductor device 100 divided into individual chips along the dicing line.

  A first wiring 103 is provided on the insulating film 102 disposed on the surface of the semiconductor chip 101. The semiconductor chip 101 is bonded to the first glass substrate 104a with a resin 105a. The back surface of the semiconductor chip 101 is bonded to the second glass substrate 104b with a resin 105b. One end of the first wiring 103 is connected to the second wiring 109. The second wiring 109 extends from one end of the first wiring 103 to the surface of the second glass substrate 104b. A ball-shaped conductive terminal 111 is formed on the second wiring 109 extending on the second glass substrate 104b.

  The technique described above is described in Patent Document 1 below.

Patent Publication 2002-512436

  Since the semiconductor device described above uses glass substrates on both sides of the semiconductor device, the semiconductor device becomes thicker and the cost increases. Therefore, a method of bonding the glass substrate only to the side where the first wiring is formed has been studied. In that case, since the side to which the glass substrate is not bonded becomes a semiconductor substrate, etching processing becomes easier as compared with the glass substrate. Taking advantage of this advantage, in order to connect the first wiring and the second wiring, the semiconductor substrate and the insulating film in the scribe region are etched to expose the first wiring. As a result, the contact area between the first wiring and the second wiring can be increased as compared with the method using glass substrates on both sides of the semiconductor chip. Thereafter, a second wiring, a protective film, a conductive terminal, and the like are formed, and the glass substrate is finally cut to separate the semiconductor devices individually.

  On the other hand, after the first wiring is exposed, the scribe region is exposed to the insulating film formed when the circuit is formed on the semiconductor substrate. At this time, only the insulating film, resin, and glass substrate exist in the scribe region. Considering the thickness of each part, substantially all the semiconductor chips are supported only by the glass substrate. Furthermore, since the coefficient of thermal expansion is different between the material of the semiconductor substrate and the glass substrate, the glass substrate is greatly warped. Therefore, a load such as a semiconductor chip bonded to the glass substrate is applied to the glass substrate by handling during the operation. As a result, as shown in FIG. 11, separation 204 occurs between the semiconductor chip and a glass substrate (not shown) at the outer periphery of the semiconductor chip, or a crack 205 occurs on the glass substrate 202. As a result, there arises a problem that the yield and reliability of the semiconductor device are lowered.

The method of manufacturing a semiconductor device of the present invention is formed on a first surface of a semiconductor substrate including a plurality of semiconductor chips, and covers a first wiring disposed in the vicinity of the boundary between the plurality of semiconductor chips. A step of adhering a support plate through an adhesive, and an opening so as to selectively remove a portion of the semiconductor substrate from the second surface and expose an insulating film under the first wiring And a step of forming. In this case, since it is a means for solving the problems associated with the exposure of the entire dicing area, it is clear that the opening is formed so that the entire dicing area is not exposed. The local form is as shown in FIG.

  The present invention has an effect of improving the yield and reliability of a semiconductor device by preventing the occurrence of cracks in the glass substrate and the peeling at the periphery of the semiconductor chip. Further, by omitting the glass substrate on the back surface side of the semiconductor chip, it is possible to reduce the thickness and cost of the semiconductor device.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a top view in the middle of manufacture of the conventional semiconductor device. It is a top view in the middle of manufacture of the semiconductor device concerning the embodiment of the present invention. It is a perspective view of the BGA type semiconductor device which concerns on a prior art example. It is sectional drawing of the BGA type semiconductor device which concerns on the past.

  Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to cross-sectional views of the semiconductor device of FIGS. 1 to 10 and a plan view of the semiconductor device of FIG.

  First, as shown in FIG. 1, a semiconductor substrate 1 is prepared. These semiconductor substrates 1 are obtained by forming, for example, a CCD image sensor or a semiconductor memory on the semiconductor substrate 1 by a semiconductor process. A first wiring having a predetermined gap in the vicinity of a boundary S (referred to as a dicing line or a scribe line) to be divided for each semiconductor chip later through the first insulating film 2 on the surface. 3 is formed. Here, the first wiring 3 is a pad extended from the bonding pad of the semiconductor device to the vicinity of the boundary S. That is, the first wiring 3 is an external connection pad and is electrically connected to a circuit (not shown) of the semiconductor device.

  Next, a glass substrate 4 used as a support plate is bonded onto the semiconductor substrate 1 on which the first wiring 3 is formed using a resin 5 (for example, epoxy resin) as a transparent adhesive. Here, a glass substrate is used as the support plate and an epoxy resin is used as the adhesive, but a silicon substrate or a plastic plate may be used as the support plate, and the adhesive is suitable for these support plates. What is necessary is just to select an adhesive agent.

  Thereafter, the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded is back-ground to reduce the thickness of the substrate. On the back-ground surface of the semiconductor substrate 1, scratches are generated, and irregularities with a width and depth of about several μm are formed. In order to reduce this, wet etching is performed using a chemical having a higher etching selectivity than silicon that is the material of the semiconductor substrate 1 and silicon oxide that is the material of the first insulating film 2.

  As described above, the chemical solution is not particularly limited as long as it has a higher etching selectivity than silicon and the silicon oxide film. For example, in the present invention, a solution of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water is used as the silicon etching solution.

  In addition, although it is more preferable to perform the said wet etching, this invention does not restrict | limit that wet etching is not performed.

  Next, as shown in FIGS. 2A and 2B, a part of the first wiring 3 is formed on the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded. Isotropic etching (or anisotropic etching) of the semiconductor substrate 1 is performed using a resist pattern (not shown) provided with an opening so as to be exposed as a mask. As a result, in the portion where the first wiring 3 exists, as shown in FIG. 2A, a window 20 opening at the boundary S is formed, and the first insulating film 2 is exposed. On the other hand, in the portion where the first wiring 3 does not exist, the semiconductor substrate 1 remains as shown in FIG. As a result, when the semiconductor device of FIGS. 2A and 2B is viewed from the semiconductor substrate 1 side, the entire cutting region 304 during dicing is not etched as shown in the plan view of FIG. A window 303 exposing a part of the cutting region 304 at the time of dicing is formed together with the first wiring 301. As a result, most of the glass substrate (not shown) is kept in a state of being bonded to the semiconductor substrate 302 via a resin or insulating film (not shown).

  As described above, by providing the window 20 that can expose only the position corresponding to the first wiring, a region where the semiconductor substrate 1 and the glass substrate 4 are bonded via the first insulating film 2 and the resin 5 is provided. Increase. Thereby, the support strength by the glass substrate 4 is raised. Moreover, the increase in the curvature of the glass substrate 4 by the difference in the thermal expansion coefficient of the semiconductor substrate 1 and the glass substrate 4 is reduced, and the crack and peeling which arise in a semiconductor device are reduced.

  Note that the etching may be performed by either dry etching or wet etching. In the description of the subsequent steps, as in FIGS. 2A and 2B, the sectional view of the portion where the window 20 is formed is the figure number (a), and the window 20 is not formed. A sectional view of the portion is shown as a drawing number (b).

  The etched surface of the semiconductor substrate 1 has in-plane irregularities, residues, and foreign matter. Further, as shown in circles 1a and 1b in FIG. It has a pointed shape.

  Therefore, as shown in FIGS. 3A and 3B, wet etching is performed to remove residues and foreign matters and to round off the tip of the sharp portion. As a result, the sharp portions of 1a and 1b circled in FIG. 2 (a) have a smooth shape as shown in 1a and 1b circled in FIG. 3 (a).

  Next, as shown in FIGS. 4A and 4B, the second insulating film 6 is formed on the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded. I do. In this embodiment, a silane-based oxide film is formed to a thickness of about 3 μm.

  Next, a resist (not shown) is applied to the surface of the semiconductor substrate 1 opposite to the surface to which the glass substrate 4 is bonded, and patterning is performed so as to open a portion along the boundary S in the window 20. Then, a resist film is formed. Then, as shown in FIGS. 5A and 5B, the second insulating film 6 and the first insulating film 2 are etched using the resist film (not shown) as a mask, and the first wiring A part of 3 is exposed.

  Next, as shown in FIGS. 6A and 6B, a flexible buffer member 7 is formed so as to correspond to a position where the conductive terminal 10 is formed later. Although the buffer member 7 has a function of absorbing the force applied to the conductive terminal 10 and relieving stress when the conductive terminal 10 is joined, the present invention does not limit the non-use of the buffer member 7. .

  Next, the second wiring 8 is formed on the opposite surface of the glass substrate 4. Thereby, the first wiring 3 and the second wiring 8 are electrically connected.

  Thereafter, a resist (not shown) is applied to the opposite surface of the glass substrate 4. Here, in a portion where the window 20 is formed, a resist film pattern is formed so as to open a portion along the boundary S in the window 20. On the other hand, in a portion where the window 20 is not opened, a resist film pattern is formed so as to expose the second wiring 8. Then, etching is performed using the resist film (not shown) as a mask, and the second wiring 8 near the boundary S is removed. Further, the portion of the second wiring 8 where the window 20 is not formed is removed.

  Next, as shown in FIGS. 7A and 7B, the notch 30 (inverted V-shaped groove) is formed so as to cut the glass substrate 4 at a depth of, for example, about 30 μm along the boundary S. Form.

  That is, in the portion where the first wiring 3 exists on the semiconductor substrate 1 (that is, the portion along the boundary S in the window 20), the resin 5 and a part of the glass substrate 4 are cut to form the cuts 30. Is done. At this time, it is necessary to use a blade having a width that does not contact the second wiring in the window 20.

  On the other hand, in a region where the first wiring 3 does not exist on the semiconductor substrate 1 (that is, a region where the window 20 is not formed), a part of the semiconductor substrate 1, the first insulating film 2, the resin 5, and the glass substrate 4 is cut. Thus, the cut 30 is formed.

  In the present embodiment, the cut 30 has a wedge-shaped cross-sectional shape, but may have a rectangular cross-sectional shape. Further, the present invention does not force the process of making the cut 30 as described above.

  Next, as shown in FIGS. 8A and 8B, the surface opposite to the glass substrate 4 is subjected to electroless plating, and the second wiring 8 is plated with Ni—Au. A film 9 is formed. Since this film is plated, it is formed only on the portion where the second wiring 8 exists.

  Next, as shown in FIGS. 9A and 9B, a protective film 10 is formed on the opposite surface of the glass substrate 4. In order to form the protective film 10, a thermosetting organic resin is dropped from above with the opposite surface of the glass substrate 4 facing upward, and the semiconductor substrate itself is rotated. The organic resin is spread on the substrate surface using centrifugal force. Thereby, the protective film 10 is formed on the back surface side of the semiconductor substrate 1 including the inner wall of the notch 30 formed along the boundary S.

  That is, in a portion where the first wiring 3 exists on the semiconductor substrate 1 (that is, a portion along the boundary S in the window 20), the resin 5 exposed on the inner wall of the cut 30 from the surface of the second insulating film 6; And the protective film 10 is formed so that the glass substrate 4 may be covered. On the other hand, in the region other than the portion where the first wiring 3 exists on the semiconductor substrate 1 (that is, the region where the window 20 is not formed), the second exposed from the surface of the second insulating film 6 on the inner wall of the cut 30. A protective film 10 is formed so as to cover the exposed portions of the insulating film 6, the semiconductor substrate 1, the first insulating film 2, the resin 5, and the glass substrate 4.

  Thereafter, the portion of the protective film 10 where the conductive terminal 11 is to be formed is removed by etching using a resist mask (not shown) (having an opening at a position corresponding to the buffer member 7), and Ni− corresponding to the buffer member 7. Conductive terminals 11 are formed at positions on the Au plating film 9. The conductive terminal 11 is electrically connected to the second wiring 8 through the Ni—Au plating film 9. The conductive terminal 11 is made of a solder bump or a gold bump. In particular, when gold bumps are used, the thickness of the conductive terminal 11 can be reduced from 160 μm to several μm to several tens of μm.

  Then, as shown in FIGS. 10A and 10B, dicing is performed along the boundary S from the portion where the notch 30 is provided, and the semiconductor device is separated into each semiconductor chip. At this time, the width of the blade used for dicing needs to be a width that can cut only the glass substrate 4 and the protective film in the cut 30.

  As described above, according to the method for manufacturing a semiconductor device of the present embodiment, dicing is performed after two-stage dicing, that is, the cut 30 is formed, and the protective film 10 covering the cut 30 is further formed. Thereby, when dicing the semiconductor device into individual semiconductor chips, the inner wall of the cut 30 formed along the boundary S (ie, the dicing line) is covered with the protective film 10, so that the glass substrate 4 and the protective film are protected. Separation can be performed by dicing only the membrane 10. That is, the blade does not come into contact with layers other than the glass substrate 4 and the protective film 10 (the resin 5 and the second wiring 8). Therefore, it is possible to suppress the separation of the separated semiconductor device, that is, the semiconductor chip due to the contact of the blade during dicing, as much as possible.

  As a result, the yield and reliability of the semiconductor device can be improved. In addition, since the semiconductor device of the present invention is composed of a single glass substrate, it is possible to reduce the thickness and reduce the cost of the semiconductor device.

  In the present embodiment, the conductive terminal 11 electrically connected to the second wiring 8 is formed, but the present invention is not limited to this. That is, the present invention may be applied to a semiconductor device (for example, LGA; Land Grid Array type package) in which a conductive terminal is not formed.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st insulating film 3 1st wiring 4 Glass substrate 5 Resin 6 2nd insulating film 7 Buffer member 8 2nd wiring 9 Ni-Au plating 10 Protective film 11 Conductive terminal

Claims (8)

A support plate is bonded via an adhesive so as to cover the first wiring formed on the first surface of the semiconductor substrate including the plurality of semiconductor chips and disposed in the vicinity of the boundary between the plurality of semiconductor chips. Process,
And a step of selectively removing a part of the semiconductor substrate from the second surface to form an opening so as to expose an insulating film under the first wiring. A method for manufacturing a semiconductor device. The said opening part is extended to the dicing area | region adjacent to the said 1st wiring from the lower part of the said 1st wiring discontinuously for every said 1st wiring. Semiconductor device manufacturing method. The first wirings are arranged in a pair so as to sandwich the boundary of the semiconductor chip, and the openings exist discontinuously for each pair of first wirings. A method for manufacturing a semiconductor device according to claim 1.   4. The semiconductor device according to claim 1, further comprising a step of grinding the second surface of the semiconductor substrate before the step of forming the opening exposing the insulating film. Manufacturing method.   5. The method according to claim 1, further comprising a step of forming a second insulating film on the second surface of the semiconductor substrate after the step of forming the opening exposing the insulating film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   6. The step of etching the first insulating film and the second insulating film to expose the first wiring after the step of forming the second insulating film. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a second wiring connected to the first wiring after the step of exposing the first wiring. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of dicing along the boundary of the semiconductor chip to separate each of the semiconductor chips.

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