JPH0669381A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0669381A JPH0669381A JP22113192A JP22113192A JPH0669381A JP H0669381 A JPH0669381 A JP H0669381A JP 22113192 A JP22113192 A JP 22113192A JP 22113192 A JP22113192 A JP 22113192A JP H0669381 A JPH0669381 A JP H0669381A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- semiconductor chip
- resin
- lead frame
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特に封止用樹脂によってパッケージされた半導体
集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device packaged with a sealing resin.
【０００２】[0002]
【従来の技術】図４に示すように、従来の封止用樹脂８
によってパッケージされた半導体集積回路装置は、熱膨
張係数の違う素材の組み合せによって構成されている
為、半導体チップ２に応力が加わり、クラックが発生す
る可能性がある。その対策の１つとして、半導体チップ
２表面に薄膜樹脂（以下、ポリイミドと記す）膜５を被
覆している。2. Description of the Related Art As shown in FIG. 4, a conventional sealing resin 8 is used.
Since the semiconductor integrated circuit device packaged by is composed of a combination of materials having different thermal expansion coefficients, stress may be applied to the semiconductor chip 2 and cracks may occur. As one of the countermeasures, the surface of the semiconductor chip 2 is covered with a thin film resin (hereinafter referred to as polyimide) film 5.
【０００３】従来のポリイミド膜５の被覆方法は、パッ
シベーション膜４で覆われた半導体チップ２の上部にポ
リイミド膜５を形成する。その後、ボンディングパッド
上部をホトリソグラフィ技術によって開孔し、次に、ボ
ンディングパッドとリードフレーム１とをボンディング
接続を行なってから封止用樹脂８にて封止される。In the conventional method of coating the polyimide film 5, the polyimide film 5 is formed on the semiconductor chip 2 covered with the passivation film 4. After that, the upper portion of the bonding pad is opened by a photolithography technique, and then the bonding pad and the lead frame 1 are bonded and then sealed with the sealing resin 8.
【０００４】[0004]
【発明が解決しようとする課題】上述したように従来の
技術では、ほぼ全面に表面が均一なポリイミド膜５を形
成しているため、封止用樹脂８と半導体チップ２の熱膨
張係数の違いにより応力がかかり、密着性の弱いポリイ
ミド膜５と封止用樹脂８との間にはがれ部分９が発生す
るという問題点がある。As described above, in the conventional technique, since the polyimide film 5 having a uniform surface is formed on almost the entire surface, the difference in the coefficient of thermal expansion between the sealing resin 8 and the semiconductor chip 2 is obtained. Therefore, there is a problem that a peeling portion 9 is generated between the polyimide film 5 having a weak adhesion and the sealing resin 8 due to the stress.
【０００５】本発明の目的は、ポリイミド膜と封止用樹
脂との間にはがれ部分の発生のない半導体集積回路装置
を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device in which there is no peeling between the polyimide film and the sealing resin.
【０００６】[0006]
【課題を解決するための手段】本発明は、リードフレー
ムと、該リードフレーム上に搭載された半導体チップ
と、該半導体チップ上に形成されたボンディングパッド
と、該ボンディングパッドを残して前記半導体チップ表
面に形成されたパッシベーション膜と、該パッシベーシ
ョン膜を被覆する薄膜樹脂と、前記ボンディングパッド
と前記リードフレームを接続するボンディングワイヤ
と、前記半導体チップと前記ボンディングパッドと前記
パッシベーション膜と前記薄膜樹脂と前記ボンディング
ワイヤと前記リードフレームの一部を封止する封止用樹
脂とを有する半導体集積回路装置において、前記薄膜樹
脂の外周部に複数の溝を設ける。According to the present invention, there is provided a lead frame, a semiconductor chip mounted on the lead frame, a bonding pad formed on the semiconductor chip, and the semiconductor chip leaving the bonding pad. A passivation film formed on the surface, a thin film resin that covers the passivation film, a bonding wire that connects the bonding pad and the lead frame, the semiconductor chip, the bonding pad, the passivation film, the thin film resin, and the thin film resin. In a semiconductor integrated circuit device having a bonding wire and a sealing resin that seals a part of the lead frame, a plurality of grooves are provided in the outer peripheral portion of the thin film resin.
【０００７】[0007]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００８】図１は本発明の第１の実施例の部分拡大断
面図、図２は図１の樹脂封止前の外周部の平面図であ
る。FIG. 1 is a partially enlarged sectional view of a first embodiment of the present invention, and FIG. 2 is a plan view of the outer peripheral portion of FIG. 1 before resin sealing.
【０００９】第１の実施例は、図１に示すように、ま
ず、半導体チップ２上のボンディングパッド３と対応す
る位置に開孔部を有するように窒化膜からなるパッシベ
ーション膜４を形成する。次に、パッシベーション膜４
全面にポリイミド膜５を形成し、ボンディングパット３
上に開孔部及び溝６をホトエッチング法を用い形成す
る。尚、溝６は図２に示すように、外周部に複数個形成
する。その後、ボンディングパット３とリードフレーム
１をボンディングワイヤ７により接続させ封止用樹脂８
により樹脂封止を行なう。In the first embodiment, as shown in FIG. 1, first, a passivation film 4 made of a nitride film is formed so as to have an opening at a position corresponding to the bonding pad 3 on the semiconductor chip 2. Next, the passivation film 4
A polyimide film 5 is formed on the entire surface, and a bonding pad 3
An opening and a groove 6 are formed on the top by a photoetching method. In addition, as shown in FIG. 2, a plurality of grooves 6 are formed in the outer peripheral portion. After that, the bonding pad 3 and the lead frame 1 are connected by the bonding wire 7, and the sealing resin 8
The resin is sealed by.
【００１０】図３は本発明の第２の実施例の溝の部分の
断面図である。FIG. 3 is a sectional view of the groove portion of the second embodiment of the present invention.
【００１１】第２の実施例は、図３に示すように、ま
ず、ポリイミド膜５を全面に形成したのち、ボンディン
グパット（図示せず）上部を完全に開孔する。In the second embodiment, as shown in FIG. 3, first, the polyimide film 5 is formed on the entire surface, and then the upper portion of the bonding pad (not shown) is completely opened.
【００１２】次に、溝６の部分をポリイミド膜５の厚み
の途中まで形成する。その後、第１の実施例と同一方法
でボンディングパッドとリードフレームをボンディング
ワイヤ７により接続させ封止用樹脂により樹脂封止を行
う。Next, the groove 6 is formed up to the middle of the thickness of the polyimide film 5. After that, the bonding pad and the lead frame are connected by the bonding wire 7 in the same manner as in the first embodiment, and the resin is sealed with the sealing resin.
【００１３】本実施例では、ポリイミド膜５に形成する
溝６の底部にパッシベーション膜４が露出することがな
いため、α線の浸入を防ぐことができる効果がある。In this embodiment, since the passivation film 4 is not exposed at the bottom of the groove 6 formed in the polyimide film 5, there is an effect that the penetration of α rays can be prevented.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、半導体チ
ップ上の外周部に複数の溝を有するポリイミド膜を形成
しているため、封止用樹脂とポリイミド膜との間に生ず
る外周部での密着性を向上させ、ポリイミド膜と封止用
樹脂との間のはがれを防止することができるという効果
を有する。As described above, according to the present invention, since the polyimide film having the plurality of grooves is formed on the outer peripheral portion on the semiconductor chip, the outer peripheral portion formed between the sealing resin and the polyimide film is formed. It has the effect of improving the adhesiveness of and preventing peeling between the polyimide film and the sealing resin.
【図１】本発明の第１の実施例の部分拡大断面図であ
る。FIG. 1 is a partially enlarged sectional view of a first embodiment of the present invention.
【図２】図１の樹脂封止前の外周部の平面図である。FIG. 2 is a plan view of an outer peripheral portion of FIG. 1 before resin sealing.
【図３】本発明の第２の実施例の溝の部分の断面図であ
る。FIG. 3 is a sectional view of a groove portion according to a second embodiment of the present invention.
【図４】従来の半導体集積回路装置の一例の部分拡大断
面図である。FIG. 4 is a partially enlarged sectional view of an example of a conventional semiconductor integrated circuit device.
１ リードフレーム ２ 半導体チップ ３ ボンディングパット ４ パッシベーション膜 ５ ポリイミド膜 ６ 溝 ７ ボンディングワイヤ ８ 封止用樹脂 ９ はがれ部分 1 Lead Frame 2 Semiconductor Chip 3 Bonding Pad 4 Passivation Film 5 Polyimide Film 6 Groove 7 Bonding Wire 8 Sealing Resin 9 Peeling Part
Claims (2)
に搭載された半導体チップと、該半導体チップ上に形成
されたボンディングパッドと、該ボンディングパッドを
残して前記半導体チップ表面に形成されたパッシベーシ
ョン膜と、該パッシベーション膜を被覆する薄膜樹脂
と、前記ボンディングパッドと前記リードフレームを接
続するボンディングワイヤと、前記半導体チップと前記
ボンディングパッドと前記パッシベーション膜と前記薄
膜樹脂と前記ボンディングワイヤと前記リードフレーム
の一部を封止する封止用樹脂とを有する半導体集積回路
装置において、前記薄膜樹脂の外周部に複数の溝を設け
たことを特徴とする半導体集積回路装置。1. A lead frame, a semiconductor chip mounted on the lead frame, a bonding pad formed on the semiconductor chip, and a passivation film formed on the surface of the semiconductor chip while leaving the bonding pad. A thin film resin that covers the passivation film, a bonding wire that connects the bonding pad and the lead frame, a semiconductor chip, the bonding pad, the passivation film, the thin film resin, the bonding wire, and the lead frame. A semiconductor integrated circuit device having a sealing resin for sealing a portion, wherein a plurality of grooves are provided in an outer peripheral portion of the thin film resin.
ことを特徴とする請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the thin film resin is a polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22113192A JPH0669381A (en) | 1992-08-20 | 1992-08-20 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22113192A JPH0669381A (en) | 1992-08-20 | 1992-08-20 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0669381A true JPH0669381A (en) | 1994-03-11 |
Family
ID=16761945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22113192A Pending JPH0669381A (en) | 1992-08-20 | 1992-08-20 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669381A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012199A1 (en) * | 1997-09-03 | 1999-03-11 | Siemens Aktiengesellschaft | Packaged integrated circuit |
| WO2014122892A1 (en) * | 2013-02-06 | 2014-08-14 | 三菱電機株式会社 | Semiconductor module |
-
1992
- 1992-08-20 JP JP22113192A patent/JPH0669381A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999012199A1 (en) * | 1997-09-03 | 1999-03-11 | Siemens Aktiengesellschaft | Packaged integrated circuit |
| WO2014122892A1 (en) * | 2013-02-06 | 2014-08-14 | 三菱電機株式会社 | Semiconductor module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980929 |