JPH08306744A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPH08306744A JPH08306744A JP7112894A JP11289495A JPH08306744A JP H08306744 A JPH08306744 A JP H08306744A JP 7112894 A JP7112894 A JP 7112894A JP 11289495 A JP11289495 A JP 11289495A JP H08306744 A JPH08306744 A JP H08306744A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- carrier tape
- chip
- substrate
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、バンプを備えた電子部
品に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component having bumps.
【０００２】[0002]
【従来の技術】バンプを備えた電子部品には、ＢＧＡ−
Ｔ、ＢＧＡ−Ｐと呼ばれるタイプのものがある。図４
（ａ）、（ｂ）は、従来の電子部品の断面図である。こ
こで、図４（ａ）の電子部品はＢＧＡ−Ｔ、図４（ｂ）
の電子部品はＢＧＡ−Ｐと呼ばれるものである。2. Description of the Related Art BGA-
There is a type called T, BGA-P. FIG.
(A), (b) is sectional drawing of the conventional electronic component. Here, the electronic component of FIG. 4A is BGA-T, and FIG.
The electronic component of is called BGA-P.
【０００３】図４（ａ）のうち、１はキャリアテープ、
２はキャリアテープ１のインナーリード３にボンディン
グされたチップ、４はキャリアテープ１の下面に複数突
出するように設けられるバンプ、５はインナーリード３
などを保護するために塗布された後硬化した樹脂であ
る。In FIG. 4A, 1 is a carrier tape,
2 is a chip bonded to the inner lead 3 of the carrier tape 1, 4 is a bump provided on the lower surface of the carrier tape 1 so as to project in plurality, and 5 is an inner lead 3.
It is a resin that has been applied and then cured to protect it.
【０００４】図４（ｂ）のうち、６はガラスエポキシな
どからなる基板であり、基板６の中央部はざぐってあ
り、肉薄になっている。この肉薄になっている中央部に
チップ７が収納され、チップ７はワイヤ８によって基板
６にボンディングされている。９は基板６の下面に複数
設けられたバンプである。１０はワイヤ８などを保護す
るために塗布された後硬化した樹脂である。In FIG. 4 (b), 6 is a substrate made of glass epoxy or the like, and the central portion of the substrate 6 is roughened and thin. The chip 7 is housed in the thinned central portion, and the chip 7 is bonded to the substrate 6 by the wire 8. A plurality of bumps 9 are provided on the lower surface of the substrate 6. Reference numeral 10 is a resin which is applied to protect the wires 8 and the like and then hardened.
【０００５】ところで、従来の電子部品では、図４に示
すように、樹脂５、１０はインナーリード３、ワイヤ８
を保護するために、電子部品の片側にのみ設けてあり、
樹脂５、１０が硬化して収縮する際に、図４に示すよう
なキャリアテープ１、基板６が樹脂５、１０側に反って
しまう。By the way, in the conventional electronic component, as shown in FIG. 4, the resins 5 and 10 are the inner leads 3 and the wires 8.
It is provided only on one side of the electronic component to protect the
When the resins 5 and 10 harden and shrink, the carrier tape 1 and the substrate 6 as shown in FIG. 4 warp toward the resins 5 and 10.
【０００６】[0006]
【発明が解決しようとする課題】バンプ４、９はキャリ
アテープ１、基板６がフラットな形状であることを前提
に形成されている。そして、バンプ４、９の下部が、電
子部品が搭載される基板の電極に接して接合が行われる
ものである。The bumps 4 and 9 are formed on the assumption that the carrier tape 1 and the substrate 6 are flat. Then, the lower portions of the bumps 4 and 9 are in contact with the electrodes of the substrate on which the electronic component is mounted for bonding.
【０００７】したがって、上述したような反りがある
と、バンプ４、９の一部が、電極から浮いてしまい（オ
ープン）、接合不良を招くという問題点があった。Therefore, if there is the above-mentioned warp, a part of the bumps 4 and 9 floats (opens) from the electrode, leading to a defective joint.
【０００８】そこで本発明は、接合不良を抑制できる電
子部品を提供することを目的とする。[0008] Therefore, an object of the present invention is to provide an electronic component capable of suppressing defective bonding.
【０００９】[0009]
【課題を解決するための手段】本発明の電子部品は、キ
ャリアテープと、キャリアテープのインナーリードにボ
ンディングされたチップと、キャリアテープの下面に設
けられる複数のバンプと、キャリアテープの上下両面に
塗布された樹脂とを備える。The electronic component of the present invention comprises a carrier tape, a chip bonded to an inner lead of the carrier tape, a plurality of bumps provided on the lower surface of the carrier tape, and upper and lower surfaces of the carrier tape. And the applied resin.
【００１０】[0010]
【作用】上記構成により、キャリアテープの上下両面に
樹脂が塗布されており、樹脂が硬化して収縮する際の反
りが、キャリアテープの上下両面でキャンセルされ、キ
ャリアテープをフラットな形状にすることができる。With the above structure, the resin is applied to the upper and lower surfaces of the carrier tape, and the warp caused when the resin is cured and contracted is canceled on the upper and lower surfaces of the carrier tape to make the carrier tape flat. You can
【００１１】これにより、バンプの位置を所期の位置の
通りにすることができ、電子部品のバンプを基板の電極
に接合するときの接合不良を抑制することができる。This makes it possible to position the bumps at the desired positions, and to prevent defective bonding when the bumps of the electronic component are bonded to the electrodes on the substrate.
【００１２】[0012]
【実施例】以下、本発明の実施例について図面を参照し
ながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は、本発明の一実施例における電子部
品の製造工程を示す流れ図である。なお、本実施例にお
いて従来の構成を示す図４の同様の構成要素について
は、同一符号を付すことにより説明を省略する。FIG. 1 is a flow chart showing a manufacturing process of an electronic component in an embodiment of the present invention. Note that, in the present embodiment, the same components as those of FIG. 4 showing the conventional configuration are denoted by the same reference numerals and the description thereof will be omitted.
【００１４】まず図３（ａ）に示すような、ＢＧＡ−Ｔ
タイプの電子部品では、キャリアテープ１にチップ２を
インナーリードボンディングする。一方、図３（ｂ）に
示すような、ＢＧＡ−Ｐタイプの電子部品では、基板６
にチップ７をボンディングし、基板６とチップ７をワイ
ヤ８で電気的に接続する。First, a BGA-T as shown in FIG.
In a type of electronic component, the chip 2 is inner lead bonded to the carrier tape 1. On the other hand, in the BGA-P type electronic component as shown in FIG.
The chip 7 is bonded to the substrate and the substrate 6 and the chip 7 are electrically connected by the wire 8.
【００１５】次に、チップ側（ＢＧＡ−Ｔではインナー
リード３側、ＢＧＡ−Ｐではワイヤ８側）に樹脂Ａをポ
ッティングする。この樹脂Ａは、インナーリード３、ワ
イヤ８などを保護するためにチップ７を覆うように塗布
するものであり、ほぼべた塗りの状態で塗布する。次に
この樹脂Ａを硬化させる。その後、表裏を反転させ、樹
脂Ａの反対側の面に樹脂Ｂを塗布する。Next, the resin A is potted to the chip side (inner lead 3 side in BGA-T, wire 8 side in BGA-P). The resin A is applied so as to cover the chip 7 in order to protect the inner leads 3, wires 8 and the like, and is applied in a substantially solid state. Next, the resin A is cured. Then, the front and back are reversed, and the resin B is applied to the surface opposite to the resin A.
【００１６】図２（ａ），（ｂ），（ｃ）は、樹脂Ｂの
塗布する際の要領を例示するものであり、図２（ａ）で
示すようにべた塗りの状態で塗ってもよいし、図２
（ｂ）に示すような十字形あるいは図２（ｃ）に示すよ
うなチップをさけて一周するような形状で塗ってもよ
い。ただしＢＧＡ−Ｔの場合は、樹脂Ｂが少なくともチ
ップ２とキャリアテープ１の両方に接触するように塗布
する。2 (a), (b), and (c) illustrate the procedure for applying the resin B, even if it is applied in a solid state as shown in FIG. 2 (a). Okay, Figure 2
The cross shape as shown in (b) or the shape as shown in FIG. However, in the case of BGA-T, the resin B is applied so that it contacts at least both the chip 2 and the carrier tape 1.
【００１７】このとき樹脂Ａ，Ｂとしては、銀ペースト
または窒化アルミペーストを用いることが好適である。
これらを用いれば、チップ２、７が動作して熱を帯びた
際にこの熱をスムーズに放熱させることができる。At this time, it is preferable to use silver paste or aluminum nitride paste as the resins A and B.
By using these, when the chips 2 and 7 operate and take heat, this heat can be radiated smoothly.
【００１８】次に樹脂Ｂを硬化させる。ここで、樹脂Ａ
が硬化した際に、キャリアテープ１または基板６は、樹
脂Ａ側に反っているが、樹脂Ｂが硬化収縮する際にこの
反りがキャンセルされ、図３に示すように、キャリアテ
ープ１、基板６はフラットな形状になる。Next, the resin B is cured. Where resin A
Although the carrier tape 1 or the substrate 6 is warped toward the resin A side when the resin is cured, this warpage is canceled when the resin B is cured and shrunk, and as shown in FIG. Has a flat shape.
【００１９】そして、バンプ４、９をキャリアテープ
１、基板６の所定の位置に形成して電子部品とするもの
である。Then, the bumps 4 and 9 are formed at predetermined positions on the carrier tape 1 and the substrate 6 to form an electronic component.
【００２０】なお上述した実施例では、樹脂Ａを硬化さ
せた後、樹脂Ｂを塗布して硬化させているが樹脂Ａ，Ｂ
を同時硬化させてもよい。In the above embodiment, the resin A is cured and then the resin B is applied and cured.
May be co-cured.
【００２１】[0021]
【発明の効果】本発明の電子部品は、キャリアテープ
と、キャリアテープのインナーリードにボンディングさ
れたチップと、キャリアテープの下面に設けられる多数
のバンプと、キャリアテープの上下両面に塗布された樹
脂とを備えるので、キャリアテープの上下両面に樹脂を
塗布して硬化させるすることで、キャリアテープの反り
を上下でキャンセルして、キャリアテープをフラットな
形状にすることができる。その結果、バンプの位置を所
期の位置の通りとして、バンプの接合不良を回避するこ
とができる。The electronic component of the present invention includes a carrier tape, a chip bonded to the inner leads of the carrier tape, a large number of bumps provided on the lower surface of the carrier tape, and a resin applied on both upper and lower surfaces of the carrier tape. By including and curing resin on both upper and lower surfaces of the carrier tape, it is possible to cancel the warp of the carrier tape on the upper and lower sides and form the carrier tape into a flat shape. As a result, the bump position can be set to the intended position and the bump bonding failure can be avoided.
【図１】本発明の一実施例における電子部品の製造工程
を示す流れ図FIG. 1 is a flow chart showing a manufacturing process of an electronic component according to an embodiment of the present invention.
【図２】（ａ）本発明の一実施例における樹脂の塗布要
領を示す平面図 （ｂ）本発明の一実施例における樹脂の塗布要領を示す
平面図 （ｃ）本発明の一実施例における樹脂の塗布要領を示す
平面図FIG. 2A is a plan view showing a resin application procedure in one embodiment of the present invention. FIG. 2B is a plan view showing a resin application procedure in one embodiment of the present invention. Plan view showing the resin application procedure
【図３】（ａ）本発明の一実施例における電子部品の断
面図 （ｂ）本発明の一実施例における電子部品の断面図3A is a sectional view of an electronic component according to an embodiment of the present invention. FIG. 3B is a sectional view of an electronic component according to an embodiment of the present invention.
【図４】（ａ）従来の電子部品の断面図 （ｂ）従来の電子部品の断面図4A is a sectional view of a conventional electronic component, and FIG. 4B is a sectional view of a conventional electronic component.
１ キャリアテープ ２ チップ ３ インナーリード ４ バンプ ５ 樹脂 ６ 基板 ７ チップ ８ ワイヤ ９ バンプ １０ 樹脂 1 Carrier Tape 2 Chip 3 Inner Lead 4 Bump 5 Resin 6 Substrate 7 Chip 8 Wire 9 Bump 10 Resin
Claims (2)
インナーリードにボンディングされたチップと、前記キ
ャリアテープの下面に設けられる複数のバンプと、前記
キャリアテープの上下両面に塗布された樹脂とを備える
ことを特徴とする電子部品。1. A carrier tape, a chip bonded to an inner lead of the carrier tape, a plurality of bumps provided on a lower surface of the carrier tape, and a resin applied on both upper and lower surfaces of the carrier tape. An electronic component characterized by.
つ前記基板に電気的に接続されたチップと、前記基板の
片面に設けられる複数のバンプと、前記チップを覆うよ
うに基板に塗布された樹脂Ａと、前記樹脂Ａが塗布され
た基板の面とは反対側の面に塗布された樹脂Ｂとを備え
ることを特徴とする電子部品。2. A substrate, a chip bonded to the substrate and electrically connected to the substrate, a plurality of bumps provided on one surface of the substrate, and a substrate coated so as to cover the chip. An electronic component comprising: a resin A; and a resin B applied on a surface opposite to a surface of a substrate on which the resin A is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11289495A JP3232954B2 (en) | 1995-05-11 | 1995-05-11 | Electronic component manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11289495A JP3232954B2 (en) | 1995-05-11 | 1995-05-11 | Electronic component manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08306744A true JPH08306744A (en) | 1996-11-22 |
| JP3232954B2 JP3232954B2 (en) | 2001-11-26 |
Family
ID=14598176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11289495A Expired - Fee Related JP3232954B2 (en) | 1995-05-11 | 1995-05-11 | Electronic component manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3232954B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997030475A1 (en) * | 1996-02-19 | 1997-08-21 | Toray Industries, Inc. | Adhesive sheet for semiconductor connecting substrate, adhesive-backed tape for tab, adhesive-backed tape for wire-bonding connection, semiconductor connecting substrate, and semiconductor device |
| KR100520443B1 (en) * | 1997-09-13 | 2006-03-14 | 삼성전자주식회사 | Chip scale package and its manufacturing method |
-
1995
- 1995-05-11 JP JP11289495A patent/JP3232954B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997030475A1 (en) * | 1996-02-19 | 1997-08-21 | Toray Industries, Inc. | Adhesive sheet for semiconductor connecting substrate, adhesive-backed tape for tab, adhesive-backed tape for wire-bonding connection, semiconductor connecting substrate, and semiconductor device |
| KR100520443B1 (en) * | 1997-09-13 | 2006-03-14 | 삼성전자주식회사 | Chip scale package and its manufacturing method |
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| Publication number | Publication date |
|---|---|
| JP3232954B2 (en) | 2001-11-26 |
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