JP3232954B2 - Electronic component manufacturing method - Google Patents
Electronic component manufacturing methodInfo
- Publication number
- JP3232954B2 JP3232954B2 JP11289495A JP11289495A JP3232954B2 JP 3232954 B2 JP3232954 B2 JP 3232954B2 JP 11289495 A JP11289495 A JP 11289495A JP 11289495 A JP11289495 A JP 11289495A JP 3232954 B2 JP3232954 B2 JP 3232954B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- carrier tape
- electronic component
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、バンプを備えた電子部
品の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component having bumps.
【０００２】[0002]
【従来の技術】バンプを備えた電子部品には、ＢＧＡ−
Ｔ、ＢＧＡ−Ｐと呼ばれるタイプのものがある。図４
（ａ）、（ｂ）は、従来の電子部品の断面図である。こ
こで、図４（ａ）の電子部品はＢＧＡ−Ｔ、図４（ｂ）
の電子部品はＢＧＡ−Ｐと呼ばれるものである。2. Description of the Related Art BGA-type electronic components are provided with bumps.
There is a type called T, BGA-P. FIG.
(A), (b) is sectional drawing of the conventional electronic component. Here, the electronic component in FIG. 4A is a BGA-T, and FIG.
Is an electronic component called BGA-P.
【０００３】図４（ａ）のうち、１はキャリアテープ、
２はキャリアテープ１のインナーリード３にボンディン
グされたチップ、４はキャリアテープ１の下面に複数突
出するように設けられるバンプ、５はインナーリード３
などを保護するために塗布された後硬化した樹脂であ
る。In FIG. 4A, reference numeral 1 denotes a carrier tape,
2 denotes a chip bonded to the inner lead 3 of the carrier tape 1, 4 denotes a bump provided on the lower surface of the carrier tape 1 so as to protrude a plurality of times, 5 denotes an inner lead 3
It is a resin that has been applied and then cured to protect it.
【０００４】図４（ｂ）のうち、６はガラスエポキシな
どからなる基板であり、基板６の中央部はざぐってあ
り、肉薄になっている。この肉薄になっている中央部に
チップ７が収納され、チップ７はワイヤ８によって基板
６にボンディングされている。９は基板６の下面に複数
設けられたバンプである。１０はワイヤ８などを保護す
るために塗布された後硬化した樹脂である。In FIG. 4 (b), reference numeral 6 denotes a substrate made of glass epoxy or the like, and the central portion of the substrate 6 is hollow and thin. The chip 7 is accommodated in the thin center portion, and the chip 7 is bonded to the substrate 6 by wires 8. Reference numeral 9 denotes a plurality of bumps provided on the lower surface of the substrate 6. Reference numeral 10 denotes a resin that is applied to protect the wires 8 and the like and then cured.
【０００５】ところで、従来の電子部品では、図４に示
すように、樹脂５、１０はインナーリード３、ワイヤ８
を保護するために、電子部品の片側にのみ設けてあり、
樹脂５、１０が硬化して収縮する際に、図４に示すよう
なキャリアテープ１、基板６が樹脂５、１０側に反って
しまう。[0005] In conventional electronic components, as shown in FIG.
Is provided on only one side of the electronic component to protect
When the resins 5 and 10 cure and shrink, the carrier tape 1 and the substrate 6 as shown in FIG.
【０００６】[0006]
【発明が解決しようとする課題】バンプ４、９はキャリ
アテープ１、基板６がフラットな形状であることを前提
に形成されている。そして、バンプ４、９の下部が、電
子部品が搭載される基板の電極に接して接合が行われる
ものである。The bumps 4 and 9 are formed on the assumption that the carrier tape 1 and the substrate 6 are flat. Then, the lower portions of the bumps 4 and 9 are in contact with the electrodes of the substrate on which the electronic components are mounted, and the bonding is performed.
【０００７】したがって、上述したような反りがある
と、バンプ４、９の一部が、電極から浮いてしまい（オ
ープン）、接合不良を招くという問題点があった。[0007] Therefore, if the above-mentioned warping is present, a part of the bumps 4 and 9 floats (open) from the electrodes, resulting in a problem that a bonding failure is caused.
【０００８】そこで本発明は、接合不良を抑制できる電
子部品の製造方法を提供することを目的とする。Accordingly, an object of the present invention is to provide a method of manufacturing an electronic component capable of suppressing poor bonding.
【０００９】[0009]
【課題を解決するための手段】本発明の電子部品の製造
方法は、キャリアテープにチップをインナーリードボン
ディングする工程と、チップ側にチップを覆うように樹
脂を塗布する工程と、この樹脂を硬化させる工程と、表
裏反転させて前記樹脂と反対側の面に樹脂を塗布する工
程と、この樹脂を硬化させる工程と、前記キャリアテー
プにバンプを形成する工程とを含む。また本発明の電子
部品の製造方法は、基板にチップをボンディングする工
程と、チップ側にチップを覆うように樹脂を塗布する工
程と、この樹脂を硬化させる工程と、表裏反転させて前
記樹脂と反対側の面に樹脂を塗布する工程と、この樹脂
を硬化させる工程と、前記基板にバンプを形成する工程
とを含む。 また望ましくは、前記樹脂が銀ペーストまた
は窒化アルミペーストである。 SUMMARY OF THE INVENTION Manufacturing of the electronic component of the present invention
How To Inner Lead Bones Chips On Carrier Tape
The process of loading
A step of applying a fat, a step of curing the resin,
Invert the back and apply the resin to the surface opposite to the resin.
Curing the resin and the carrier table.
Forming a bump on the bump . In addition, the electron of the present invention
The method of manufacturing components is based on the process of bonding chips to a substrate.
And apply resin on the chip side to cover the chip.
And the process of curing this resin,
Applying a resin to the surface opposite to the resin,
Curing and forming a bump on the substrate
And Preferably, the resin is a silver paste or
Is an aluminum nitride paste.
【００１０】[0010]
【作用】上記構成により、キャリアテープや基板の上下
両面に樹脂が塗布されており、樹脂が硬化して収縮する
際の反りが、キャリアテープや基板の上下両面でキャン
セルされ、キャリアテープや基板をフラットな形状にす
ることができる。According to the above configuration, the resin is applied to both the upper and lower surfaces of the carrier tape and the substrate , and the warpage when the resin cures and contracts is canceled by the upper and lower surfaces of the carrier tape and the substrate . It can be made flat.
【００１１】これにより、バンプの位置を所期の位置の
通りにすることができ、電子部品のバンプを基板の電極
に接合するときの接合不良を抑制することができる。[0011] This makes it possible to set the position of the bumps as intended, thereby suppressing bonding failure when bonding the bumps of the electronic component to the electrodes of the substrate.
【００１２】[0012]
【実施例】以下、本発明の実施例について図面を参照し
ながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は、本発明の一実施例における電子部
品の製造工程を示す流れ図である。なお、本実施例にお
いて従来の構成を示す図４の同様の構成要素について
は、同一符号を付すことにより説明を省略する。FIG. 1 is a flowchart showing a process of manufacturing an electronic component according to an embodiment of the present invention. In this embodiment, the same components as those in FIG. 4 showing the conventional configuration are denoted by the same reference numerals, and the description is omitted.
【００１４】まず図３（ａ）に示すような、ＢＧＡ−Ｔ
タイプの電子部品では、キャリアテープ１にチップ２を
インナーリードボンディングする。一方、図３（ｂ）に
示すような、ＢＧＡ−Ｐタイプの電子部品では、基板６
にチップ７をボンディングし、基板６とチップ７をワイ
ヤ８で電気的に接続する。First, a BGA-T as shown in FIG.
In a type of electronic component, the chip 2 is inner-lead bonded to the carrier tape 1. On the other hand, in a BGA-P type electronic component as shown in FIG.
The chip 7 is bonded to the substrate 7 and the substrate 6 and the chip 7 are electrically connected by wires 8.
【００１５】次に、チップ側（ＢＧＡ−Ｔではインナー
リード３側、ＢＧＡ−Ｐではワイヤ８側）に樹脂Ａをポ
ッティングする。この樹脂Ａは、インナーリード３、ワ
イヤ８などを保護するためにチップ７を覆うように塗布
するものであり、ほぼべた塗りの状態で塗布する。次に
この樹脂Ａを硬化させる。その後、表裏を反転させ、樹
脂Ａの反対側の面に樹脂Ｂを塗布する。Next, the resin A is potted on the chip side (the inner lead 3 side in the case of BGA-T, and the wire 8 side in the case of BGA-P). The resin A is applied so as to cover the chip 7 to protect the inner leads 3 and the wires 8 and the like, and is applied in a substantially solid state. Next, the resin A is cured. Then, the resin B is applied to the surface on the opposite side of the resin A, with the front and back reversed.
【００１６】図２（ａ），（ｂ），（ｃ）は、樹脂Ｂの
塗布する際の要領を例示するものであり、図２（ａ）で
示すようにべた塗りの状態で塗ってもよいし、図２
（ｂ）に示すような十字形あるいは図２（ｃ）に示すよ
うなチップをさけて一周するような形状で塗ってもよ
い。ただしＢＧＡ−Ｔの場合は、樹脂Ｂが少なくともチ
ップ２とキャリアテープ１の両方に接触するように塗布
する。FIGS. 2 (a), 2 (b) and 2 (c) illustrate the procedure for applying the resin B, and the resin B may be applied in a solid state as shown in FIG. 2 (a). OK, Figure 2
It may be applied in a cross shape as shown in FIG. 2B or in such a shape as to make a round around the tip as shown in FIG. 2C. However, in the case of BGA-T, the resin B is applied so as to contact at least both the chip 2 and the carrier tape 1.
【００１７】このとき樹脂Ａ，Ｂとしては、銀ペースト
または窒化アルミペーストを用いることが好適である。
これらを用いれば、チップ２、７が動作して熱を帯びた
際にこの熱をスムーズに放熱させることができる。At this time, it is preferable to use silver paste or aluminum nitride paste as the resins A and B.
If these are used, when the chips 2 and 7 operate and become hot, the heat can be smoothly radiated.
【００１８】次に樹脂Ｂを硬化させる。ここで、樹脂Ａ
が硬化した際に、キャリアテープ１または基板６は、樹
脂Ａ側に反っているが、樹脂Ｂが硬化収縮する際にこの
反りがキャンセルされ、図３に示すように、キャリアテ
ープ１、基板６はフラットな形状になる。Next, the resin B is cured. Here, resin A
When the resin is cured, the carrier tape 1 or the substrate 6 is warped toward the resin A. However, when the resin B is cured and contracted, the warpage is canceled, and as shown in FIG. Has a flat shape.
【００１９】そして、バンプ４、９をキャリアテープ
１、基板６の所定の位置に形成して電子部品とするもの
である。Then, the bumps 4 and 9 are formed at predetermined positions on the carrier tape 1 and the substrate 6 to form an electronic component.
【００２０】なお上述した実施例では、樹脂Ａを硬化さ
せた後、樹脂Ｂを塗布して硬化させているが樹脂Ａ，Ｂ
を同時硬化させてもよい。In the above-described embodiment, after the resin A is cured, the resin B is applied and cured.
May be simultaneously cured.
【００２１】[0021]
【発明の効果】本発明の電子部品の製造方法によれば、
キャリアテープや基板の反りを上下でキャンセルして、
キャリアテープや基板をフラットな形状にすることがで
きる。その結果、バンプの位置を所期の位置の通りとし
て、バンプの接合不良を回避することができる。 According to the method for manufacturing an electronic component of the present invention ,
Cancel the warping of the carrier tape or the board up and down,
The carrier tape and the substrate can be made flat. As a result, the position of the bump is set as the expected position, and the bonding failure of the bump can be avoided.
【図１】本発明の一実施例における電子部品の製造工程
を示す流れ図FIG. 1 is a flowchart showing a manufacturing process of an electronic component according to an embodiment of the present invention.
【図２】（ａ）本発明の一実施例における樹脂の塗布要
領を示す平面図 （ｂ）本発明の一実施例における樹脂の塗布要領を示す
平面図 （ｃ）本発明の一実施例における樹脂の塗布要領を示す
平面図FIG. 2A is a plan view showing a resin application procedure in one embodiment of the present invention. FIG. 2B is a plan view showing a resin application procedure in one embodiment of the present invention. Plan view showing resin application procedure
【図３】（ａ）本発明の一実施例における電子部品の断
面図 （ｂ）本発明の一実施例における電子部品の断面図3A is a cross-sectional view of an electronic component according to one embodiment of the present invention. FIG. 3B is a cross-sectional view of an electronic component according to one embodiment of the present invention.
【図４】（ａ）従来の電子部品の断面図 （ｂ）従来の電子部品の断面図4A is a cross-sectional view of a conventional electronic component. FIG. 4B is a cross-sectional view of a conventional electronic component.
１ キャリアテープ ２ チップ ３ インナーリード ４ バンプ ５ 樹脂 ６ 基板 ７ チップ ８ ワイヤ ９ バンプ １０ 樹脂 DESCRIPTION OF SYMBOLS 1 Carrier tape 2 Chip 3 Inner lead 4 Bump 5 Resin 6 Substrate 7 Chip 8 Wire 9 Bump 10 Resin
フロントページの続き (56)参考文献 特開 平６−275676（ＪＰ，Ａ) 特開 平７−22538（ＪＰ，Ａ) 特開 平８−148526（ＪＰ，Ａ) 特開 昭64−11357（ＪＰ，Ａ) 特開 平２−185051（ＪＰ，Ａ) 特開 平２−281746（ＪＰ，Ａ) 特開 平５−102350（ＪＰ，Ａ) 実開 昭55−42351（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/56 H01L 23/12 Continuation of front page (56) References JP-A-6-275676 (JP, A) JP-A-7-22538 (JP, A) JP-A-8-148526 (JP, A) JP-A-64-11357 (JP) JP-A-2-185051 (JP, A) JP-A-2-281746 (JP, A) JP-A-5-102350 (JP, A) JP-A-55-42351 (JP, U) (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 H01L 21/56 H01L 23/12
Claims (3)
ボンディングする工程と、インナーリードボンディング
されたこのチップ側にこのチップを覆うように樹脂を塗
布する工程と、この樹脂を硬化させる工程と、表裏反転
させて前記樹脂と反対側の面に樹脂を塗布する工程と、
この樹脂を硬化させる工程と、前記キャリアテープにバ
ンプを形成する工程とを含むことを特徴とする電子部品
の製造方法。1. An inner lead for a chip on a carrier tape.
Bonding process and inner lead bonding
Apply resin to this chip side to cover this chip.
Cloth process, curing this resin, reversing
And applying a resin to the surface opposite to the resin,
Curing the resin and applying a carrier to the carrier tape.
An electronic component , comprising the steps of:
Manufacturing method .
ボンディングされたこのチップ側にこのチップを覆うよ
うに樹脂を塗布する工程と、この樹脂を硬化させる工程
と、表裏反転させて前記樹脂と反対側の面に樹脂を塗布
する工程と、この樹脂を硬化させる工程と、前記基板に
バンプを形成する工程とを含むことを特徴とする電子部
品の製造方法。2. A step of bonding a chip to a substrate ;
Cover this chip on the bonded chip side
Applying resin and curing the resin
And then apply the resin on the surface opposite to the resin
Performing a step of curing the resin; and
Method of manufacturing an electronic component which comprises a step of forming a bump.
ーストであることを特徴とする請求項１または２記載の3. The method according to claim 1, wherein
電子部品の製造方法。Manufacturing method of electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11289495A JP3232954B2 (en) | 1995-05-11 | 1995-05-11 | Electronic component manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11289495A JP3232954B2 (en) | 1995-05-11 | 1995-05-11 | Electronic component manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08306744A JPH08306744A (en) | 1996-11-22 |
| JP3232954B2 true JP3232954B2 (en) | 2001-11-26 |
Family
ID=14598176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11289495A Expired - Fee Related JP3232954B2 (en) | 1995-05-11 | 1995-05-11 | Electronic component manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3232954B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW340967B (en) * | 1996-02-19 | 1998-09-21 | Toray Industries | An adhesive sheet for a semiconductor to connect with a substrate, and adhesive sticking tape for tab, an adhesive sticking tape for wire bonding connection, a substrate for connecting with a semiconductor and a semiconductor device |
| KR100520443B1 (en) * | 1997-09-13 | 2006-03-14 | 삼성전자주식회사 | Chip scale package and its manufacturing method |
-
1995
- 1995-05-11 JP JP11289495A patent/JP3232954B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08306744A (en) | 1996-11-22 |
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