JP3472342B2 - Method of manufacturing semiconductor device package - Google Patents

Method of manufacturing semiconductor device package

Info

Publication number
JP3472342B2
JP3472342B2 JP11254894A JP11254894A JP3472342B2 JP 3472342 B2 JP3472342 B2 JP 3472342B2 JP 11254894 A JP11254894 A JP 11254894A JP 11254894 A JP11254894 A JP 11254894A JP 3472342 B2 JP3472342 B2 JP 3472342B2
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
manufacturing
conductive material
protruding contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11254894A
Other languages
Japanese (ja)
Other versions
JPH07321162A (en
Inventor
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP11254894A priority Critical patent/JP3472342B2/en
Publication of JPH07321162A publication Critical patent/JPH07321162A/en
Application granted granted Critical
Publication of JP3472342B2 publication Critical patent/JP3472342B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の実装体の
製造方法に係り、特にフェースダウンで半導体装置を実
装する技術の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting body.
The present invention relates to a manufacturing method , and more particularly, to improvement of a technique for mounting a semiconductor device face down.

【0002】[0002]

【従来の技術】従来、フェースダウンによる半導体装置
の回路基板への実装方法としては、あらかじめメッキ技
術により半導体装置の電極パッド上に半田用合金からな
る突出接点を形成しておき、この突出接点を回路基板の
接続電極に半田付けする方法が用いられていたが、近年
では導電性接着剤を用いて半導体装置を回路基板に接続
する方法が用いられつつある。
2. Description of the Related Art Conventionally, as a method of mounting a semiconductor device on a circuit board by face down, a protruding contact made of a soldering alloy is previously formed on an electrode pad of the semiconductor device by a plating technique, and this protruding contact is used. The method of soldering to the connection electrode of the circuit board has been used, but in recent years, a method of connecting the semiconductor device to the circuit board using a conductive adhesive is being used.

【0003】このような導電性接着剤を用いた半導体装
置の実装方法として、例えば米国特許第4661192
号公報に開示されるように、導電性接着剤を用いてフェ
ースダウンにより半導体装置を回路基板に簡易的に接続
する技術がある。以下、図面を参照しながら、従来の半
導体装置の実装技術について説明する。
As a method of mounting a semiconductor device using such a conductive adhesive, for example, US Pat. No. 4,661,192 is used.
As disclosed in the publication, there is a technique for simply connecting a semiconductor device to a circuit board by face down using a conductive adhesive. Hereinafter, a conventional mounting technique of a semiconductor device will be described with reference to the drawings.

【0004】図3は、半導体装置の実装工程の一部を示
し、半導体装置の突出接点に導電性接着剤を転写する工
程を示す図である。また、図4は、上述の工程によって
形成される半導体装置の実装体の要部断面図である。
FIG. 3 is a diagram showing a part of the mounting process of the semiconductor device, showing the process of transferring the conductive adhesive to the protruding contacts of the semiconductor device. Further, FIG. 4 is a cross-sectional view of a main part of a semiconductor device package formed by the above-described process.

【0005】図3および図4において、9は半導体装
置、10は半導体装置9上の所定部位に形成された端子
電極、11は該端子電極10上に形成された導電性材料
からなる突出接点、12は導電性エポキシ樹脂を塗布し
てなる塗膜、13は支持基体、14は回路基板、15は
回路基板上の接続電極、16は導電性エポキシ樹脂を突
出接点10に転写してなる転写部である。
In FIGS. 3 and 4, 9 is a semiconductor device, 10 is a terminal electrode formed on a predetermined portion of the semiconductor device 9, 11 is a protruding contact made of a conductive material, formed on the terminal electrode 10. Reference numeral 12 is a coating film formed by applying a conductive epoxy resin, 13 is a supporting substrate, 14 is a circuit board, 15 is a connecting electrode on the circuit board, and 16 is a transfer portion formed by transferring the conductive epoxy resin to the protruding contact 10. Is.

【0006】以上のように構成された従来の導電性接着
剤を用いた半導体装置の実装方法およびその実装体につ
いて、以下その概略を説明する。
The outline of a conventional semiconductor device mounting method using the above-described conductive adhesive and its mounting body will be described below.

【0007】まず、支持基体13の上に導電性エポキシ
樹脂の塗膜10を形成しておき、図3に示すように、こ
の支持基体13の上方から、半導体装置9を突出接点1
1を下方にした状態で下降させて、両者を接触させる。
そして、半導体装置9の突出接点11の先端を支持基体
13上に形成した導電性エポキシ樹脂の塗膜12に接触
させることにより、突出接点11に導電性エポキシ樹脂
を転写する。
First, a conductive epoxy resin coating film 10 is formed on a support base 13, and the semiconductor device 9 is connected to the protruding contact 1 from above the support base 13 as shown in FIG.
1 is lowered and the two are brought into contact with each other.
Then, the tip of the protruding contact 11 of the semiconductor device 9 is brought into contact with the coating film 12 of the conductive epoxy resin formed on the support base 13 to transfer the conductive epoxy resin to the protruding contact 11.

【0008】その後、突出接点11上に導電性エポキシ
樹脂の転写部16を付着した半導体装置9を、回路基板
14上の接続電極15に位置合わせして積載した後、導
電性エポキシ樹脂を硬化させることにより、図4に示す
ように、導電性エポキシ樹脂を用いた半導体装置9の実
装体を得るものである。
After that, the semiconductor device 9 in which the transfer portion 16 of the conductive epoxy resin is attached on the protruding contact 11 is aligned with the connection electrode 15 on the circuit board 14 and stacked, and then the conductive epoxy resin is cured. As a result, as shown in FIG. 4, a mounting body of the semiconductor device 9 using the conductive epoxy resin is obtained.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、上記の
ような半導体装置の実装方法とその実装体においては、
導電性接着剤として導電性エポキシ樹脂を用いるため、
半導体装置9を回路基板14に積載した後に導電性エポ
キシ樹脂を硬化するのに必要な時間が長く、半導体装置
9の実装体の生産性に欠けるという問題があった。すな
わち、一般的に、導電性エポキシ樹脂の硬化には150
℃程度の熱と1時間以上の時間が必要となるからであ
る。
However, in the mounting method of the semiconductor device and the mounting body thereof as described above,
Since a conductive epoxy resin is used as a conductive adhesive,
There is a problem that the time required to cure the conductive epoxy resin after the semiconductor device 9 is loaded on the circuit board 14 is long, and the productivity of the package of the semiconductor device 9 is low. That is, in general, 150 is required to cure the conductive epoxy resin.
This is because heat of about ° C and time of 1 hour or more are required.

【0010】本発明は上記の課題に鑑みてなされたもの
であり、その目的とするところは、半導体装置を回路基
板に生産性良く簡易的に実装することのできる半導体装
置の実装体の製造方法を提供することにある。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device mounting body capable of easily mounting a semiconductor device on a circuit board with high productivity. To provide.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するた
め、本発明の講じた手段は、回路基板に熱可塑性の樹脂
硬化型導電性材料からなる接続電極を形成しておき、半
導体装置の突出接点を接続電極に熱圧着する技術であ
る。
Means for Solving the Problems In order to achieve the above-mentioned object, the means taken by the present invention is such that a connecting electrode made of a thermoplastic resin-curable conductive material is formed on a circuit board, and a semiconductor device is projected. This is a technique of thermocompression bonding the contact to the connection electrode.

【0012】具体的に請求項1の発明の講じた手段は、
半導体装置をフェースダウンで回路基板に実装する半導
体装置の実装体の製造方法として、半導体装置の端子電
極に突出接点を形成する工程と、熱可塑性の樹脂硬化型
導電性材料を用いて、上記回路基板の表面が平坦な金属
配線パターン上に半導体装置実装用の接続電極を形成す
る工程と、上記半導体装置の突出接点を上記回路基板の
表面が平坦な金属配線パターン上の接続電極に熱圧着し
て半導体装置と回路基板とを接合する工程とを設ける方
法である。
Specifically, the means taken by the invention of claim 1 is as follows.
As a method for manufacturing a semiconductor device mounting body in which a semiconductor device is mounted face down on a circuit board, a step of forming a protruding contact on a terminal electrode of the semiconductor device and a circuit using the thermoplastic resin-curable conductive material A step of forming connection electrodes for mounting a semiconductor device on a metal wiring pattern having a flat surface on the substrate;
And a step of joining the semiconductor device and the circuit board by thermocompression bonding to the connection electrode on the metal wiring pattern having a flat surface .

【0013】請求項2の発明の講じた手段は、請求項1
の発明において、上記半導体装置の端子電極に突出接点
を形成する工程では、メッキ法により突出接点を形成す
る方法である。
The means taken by the invention of claim 2 is defined by claim 1.
In the invention, the step of forming the protruding contact on the terminal electrode of the semiconductor device is a method of forming the protruding contact by a plating method.

【0014】請求項3の発明の講じた手段は、請求項1
の発明において、上記半導体装置の端子電極に突出接点
を形成する工程では、ワイヤボンディング法により突出
接点を形成する方法である。
The means taken by the invention of claim 3 is the method of claim 1.
In the invention, the step of forming the protruding contact on the terminal electrode of the semiconductor device is a method of forming the protruding contact by a wire bonding method.

【0015】請求項4の発明の講じた手段は、請求項
1,2又は3の発明において、上記金属配線パターン
は、焼結型導電性材料を用いて上記回路基板の一部位に
形成されている方法である。
The means taken by the invention of claim 4 is the metal wiring pattern according to the invention of claim 1, 2 or 3.
Is a part of the circuit board that is made of sintered conductive material.
It is a method that has been formed .

【0016】請求項5の発明の講じた手段は、請求項
1,2又は3の発明において、上記金属配線パターン
は、導電性材料の金属箔を用いて上記回路基板の一部位
に形成されている方法である。
The means taken by the invention of claim 5 is the metal wiring pattern according to the invention of claim 1, 2 or 3.
Is a part of the above circuit board using a metal foil of a conductive material.
It is a method that is formed in .

【0017】請求項6の発明の講じた手段は、請求項
1,2,3,4又は5の発明において、上記半導体装置
と回路基板とを接合する工程では、半導体装置を回路基
板の接続電極が可塑状態となる温度以上の温度に加熱す
る方法である。
According to a sixth aspect of the invention, in the method of the first, second, third, fourth or fifth aspect of the invention, in the step of joining the semiconductor device and the circuit board, the semiconductor device is connected to a connection electrode of the circuit board. It is a method of heating to a temperature equal to or higher than the temperature at which is plastic.

【0018】請求項7の発明の講じた手段は、請求項
1,2,3,4又は5の発明において、上記半導体装置
と回路基板とを接合する工程では、回路基板を接続電極
が可塑状態となる温度以上の温度に加熱する方法であ
る。
According to a seventh aspect of the invention, in the method of the first, second, third, fourth or fifth aspect of the invention, in the step of joining the semiconductor device and the circuit board, the connection electrode of the circuit board is in a plastic state. It is a method of heating to a temperature equal to or higher than that.

【0019】請求項8の発明の講じた手段は、請求項
1,2,3,4,5,6又は7の発明において、上記熱
可塑性の樹脂硬化型導電性材料として、少なくとも熱可
塑性樹脂と導電性フィラーとを含む材料を用いる方法で
ある。
According to the invention of claim 8, in the invention of claim 1, 2, 3, 4, 5, 6 or 7, at least a thermoplastic resin is used as the thermoplastic resin-curable conductive material. This is a method of using a material containing a conductive filler.

【0020】[0020]

【作用】以上の方法により、請求項1の発明では、フェ
ースダウンで実装する半導体装置の突出接点が熱可塑性
の樹脂硬化型導電性材料からなる回路基板の接続電極に
熱圧着によって接合されるので、熱硬化型樹脂を用いた
接合のごとく反応に長時間を要することなく、冷却だけ
で熱可塑性樹脂が硬化し、半導体装置の実装が極めて短
時間で完了する。また、熱可塑性の樹脂硬化型導電性材
料は比較的低温で可塑状態となるので、半導体装置と回
路基板の熱膨張係数の差により生じる熱応力も極めて小
さく抑制される。
According to the above method, in the invention of claim 1, the protruding contact of the semiconductor device mounted face down is bonded to the connection electrode of the circuit board made of the thermoplastic resin-curable conductive material by thermocompression bonding. The thermoplastic resin is hardened only by cooling and the mounting of the semiconductor device is completed in an extremely short time without requiring a long time for the reaction unlike the bonding using the thermosetting resin. Further, since the thermoplastic resin-curable conductive material is in a plastic state at a relatively low temperature, the thermal stress caused by the difference in thermal expansion coefficient between the semiconductor device and the circuit board can be suppressed to an extremely small level.

【0021】請求項2,3の発明では、簡易に半導体装
置の突出接点が形成され、突出接点と熱可塑性の樹脂硬
化型導電性材料からなる回路基板の接続電極との接着性
も良好となる。
According to the second and third aspects of the present invention, the protruding contact of the semiconductor device is easily formed, and the adhesiveness between the protruding contact and the connection electrode of the circuit board made of the thermoplastic resin-curable conductive material becomes good. .

【0022】請求項4の発明では、セラミック等の高温
における耐久性の高い材料で構成される回路基板に適し
実装体の製造方法となり、信頼性が向上する。
According to the fourth aspect of the invention, the method of manufacturing a mounting body suitable for a circuit board made of a material having high durability at high temperature such as ceramics is provided, and reliability is improved.

【0023】請求項5の発明では、ガラスエポキシ等の
樹脂材料で構成される回路基板に適した実装体の製造方
となり、製造コストが低減する。
According to the invention of claim 5, a method of manufacturing a mounting body suitable for a circuit board made of a resin material such as glass epoxy.
Method , which reduces manufacturing costs.

【0024】請求項6,7の発明では、接続電極を構成
する熱可塑性の導電性樹脂硬化型材料が容易に可塑状態
に維持され、熱圧着が円滑に行われることになる。その
際、半導体装置を吸着するツールや回路基板の支持部材
を利用して加熱を行うことが可能となり、装置の構成が
簡素化される。
According to the sixth and seventh aspects of the invention, the thermoplastic conductive resin curable material forming the connection electrode is easily maintained in a plastic state, and thermocompression bonding is smoothly performed. At that time, it is possible to perform heating by using a tool for adsorbing the semiconductor device or a support member for the circuit board, and the structure of the device is simplified.

【0025】請求項8の発明では、熱可塑性樹脂の導電
性フィラーとによって、接続電極に必要な機能が簡易に
確保される。
According to the eighth aspect of the present invention, the function required for the connection electrode is easily ensured by the conductive filler of the thermoplastic resin.

【0026】[0026]

【実施例】以下、本発明の実施例に係る半導体装置の実
装工程と、その結果得られる半導体装置の実装体とにつ
いて、図面を参照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device mounting process according to an embodiment of the present invention and a resulting semiconductor device mounting body will be described below with reference to the drawings.

【0027】図1(a)〜(c)は実施例における半導
体装置の実装方法を説明する工程図、図2は上記図1の
実装方法により作製される半導体装置の実装体の要部断
面図である。
FIGS. 1A to 1C are process drawings for explaining a method of mounting a semiconductor device according to an embodiment, and FIG. 2 is a cross-sectional view of a main part of a semiconductor device mounting body manufactured by the mounting method of FIG. Is.

【0028】図1および図2において、1は半導体装
置、2は該半導体装置1の所定部位に形成された端子電
極、3は該端子電極2の上に形成された突出接点、4は
回路基板、5は該回路基板4の所定部位に形成された焼
結型導電性材料からなる配線パターン、6は熱可塑性の
樹脂硬化型導電性材料からなる接続電極、7は熱圧着ツ
ールである。本実施例では、熱可塑性の樹脂硬化型導電
性材料として、ポリエステル樹脂などの熱可塑性樹脂に
Agなどの導電フィラーを含んだものを用いている。
In FIGS. 1 and 2, 1 is a semiconductor device, 2 is a terminal electrode formed on a predetermined portion of the semiconductor device 1, 3 is a protruding contact formed on the terminal electrode 2, and 4 is a circuit board. Reference numeral 5 is a wiring pattern made of a sintered conductive material formed at a predetermined portion of the circuit board 4, 6 is a connecting electrode made of a thermoplastic resin-curable conductive material, and 7 is a thermocompression bonding tool. In this embodiment, as the thermoplastic resin-curable conductive material, a thermoplastic resin such as polyester resin containing a conductive filler such as Ag is used.

【0029】以上のように構成された半導体装置の実装
方法とその実装体について、以下、図面を用いて説明す
る。
A method of mounting the semiconductor device configured as described above and a mounting body thereof will be described below with reference to the drawings.

【0030】まず、図1(a)に示すように、半導体装
置1の端子電極2上に公知の方法により突出接点3を形
成する。突出接点3の形成にはメッキ法やワイヤボンデ
ィング法などを用いることができる。突出接点3はその
表面に酸化膜のないことが望ましく、その材質としては
Auが最適である。
First, as shown in FIG. 1A, a protruding contact 3 is formed on the terminal electrode 2 of the semiconductor device 1 by a known method. A plating method, a wire bonding method, or the like can be used to form the protruding contact 3. It is desirable that the protruding contact 3 has no oxide film on its surface, and Au is the most suitable material.

【0031】一方、図1(b)に示すように、セラミッ
クからなる回路基板4上に焼結型導電性材料により配線
パターン5を形成した後、焼結型導電性材料の配線パタ
ーン5の上に、熱可塑性の樹脂硬化型導電性材料からな
る半導体装置実装用の接続電極6を形成する。この接続
電極6の形成にはスクリーン印刷法や転写法などを用い
ることができる。なお、回路基板4がガラスエポキシな
どの樹脂基材からなる場合には、回路基板4上に形成す
る配線パターン5はCuなどの金属箔を用いて形成し、
その上に熱可塑性の樹脂硬化型導電性材料の印刷等を行
って半導体装置実装用の接続電極6を形成してもよい。
On the other hand, as shown in FIG. 1B, after a wiring pattern 5 is formed of a sintered conductive material on a circuit board 4 made of ceramic, the wiring pattern 5 of a sintered conductive material is formed on the wiring pattern 5. Then, the connection electrode 6 for mounting the semiconductor device, which is made of a thermoplastic resin-curable conductive material, is formed. A screen printing method, a transfer method, or the like can be used to form the connection electrode 6. When the circuit board 4 is made of a resin base material such as glass epoxy, the wiring pattern 5 formed on the circuit board 4 is formed by using a metal foil such as Cu,
The connection electrode 6 for mounting the semiconductor device may be formed by printing a thermoplastic resin-curable conductive material on it.

【0032】次に、図1(c)に示すように、半導体装
置1を裏面から熱圧着ツール7によって吸着,保持しな
がら回路基板4の上方から下降させ、半導体装置1の突
出接点3と回路基板4の接続電極を位置合わせして両者
を接触させた後、半導体装置1を裏面から熱圧着ツール
7により加熱しながら加圧する。この際、接続電極6を
構成する樹脂硬化型導電性材料が可塑状態となる温度以
上の温度に加熱することによって、半導体装置1の突出
接点3の表面に可塑状態となった熱可塑性の樹脂硬化型
導電性材料が付着する。
Next, as shown in FIG. 1C, the semiconductor device 1 is lowered from above the circuit board 4 while adsorbing and holding the semiconductor device 1 from the backside by the thermocompression bonding tool 7, and the protruding contact 3 of the semiconductor device 1 and the circuit. After the connection electrodes of the substrate 4 are aligned and brought into contact with each other, the semiconductor device 1 is pressed from the backside while being heated by the thermocompression bonding tool 7. At this time, by heating the resin-curable conductive material forming the connection electrode 6 to a temperature equal to or higher than a temperature at which the resin-curable conductive material is in a plastic state, the surface of the protruding contact 3 of the semiconductor device 1 is cured of the thermoplastic resin in a plastic state The mold conductive material adheres.

【0033】その後、熱圧着ツール7を半導体装置3か
ら離すと、熱可塑性の樹脂硬化型導電性材料が冷却され
短時間で硬化して、両者が接合される。そして、図2に
示すように、半導体装置1の突出接点3と熱可塑性の樹
脂硬化型導電性材料で構成される回路基板4の接続電極
6とが接合されてなる半導体装置1の実装体を得ること
ができる。
After that, when the thermocompression bonding tool 7 is separated from the semiconductor device 3, the thermoplastic resin-curable conductive material is cooled and cured in a short time, and the two are joined. Then, as shown in FIG. 2, a mounting body of the semiconductor device 1 in which the protruding contacts 3 of the semiconductor device 1 and the connection electrodes 6 of the circuit board 4 made of a thermoplastic resin-curable conductive material are joined together Obtainable.

【0034】上記実施例では、回路基板4の上の半導体
装置実装用の接続電極6を熱可塑性の樹脂硬化型導電性
材料で形成するようにしたので、半導体装置1を回路基
板4に実装する際に、熱硬化型樹脂のように反応のため
に長時間を要することがなく、冷却によって速やかに硬
化し接合が完了する。したがって、フェースダウンによ
る半導体装置の実装体を生産性良く得ることができる。
In the above embodiment, the connection electrode 6 for mounting the semiconductor device on the circuit board 4 is formed of the thermoplastic resin-curable conductive material, so that the semiconductor device 1 is mounted on the circuit board 4. At this time, unlike a thermosetting resin, it does not take a long time for the reaction, and upon cooling, the resin is rapidly cured to complete the joining. Therefore, a face-down semiconductor device package can be obtained with high productivity.

【0035】また、上記実施例では、半導体装置1を回
路基板4に熱可塑性の樹脂硬化型導電性材料を用いて実
装するために、半導体装置1と回路基板4の熱膨張係数
の差に起因する熱応力を極めて小さく抑制することがで
き、信頼性の高い半導体装置の実装体を得ることができ
る。
Further, in the above embodiment, since the semiconductor device 1 is mounted on the circuit board 4 by using the thermoplastic resin-curable conductive material, the difference in the thermal expansion coefficient between the semiconductor device 1 and the circuit board 4 is caused. The thermal stress generated can be suppressed to an extremely small level, and a highly reliable semiconductor device package can be obtained.

【0036】なお、上記実施例では、半導体装置1を実
装する際に、熱圧着工程で熱圧着ツール7によって半導
体装置1を加熱するようにしたが、本発明はかかる実施
例に限定されるものではない。熱圧着を、例えば回路基
板4へ回路基板4を加熱した状態で行ってもよく、或い
は赤外線を照射する等によって接続電極6及びその付近
のみを加熱するようにしてもよい。
In the above embodiment, when the semiconductor device 1 is mounted, the semiconductor device 1 is heated by the thermocompression bonding tool 7 in the thermocompression bonding process, but the present invention is not limited to this embodiment. is not. The thermocompression bonding may be performed, for example, in a state where the circuit board 4 is heated to the circuit board 4, or only the connection electrode 6 and its vicinity may be heated by irradiating infrared rays.

【0037】また、上記実施例では、熱可塑性の樹脂硬
化型導電性材料として、ポリエステル樹脂などの熱可塑
性樹脂にAgなどの導電フィラーを含んだものを用いた
が、熱可塑性を有する樹脂硬化型導電性材料であればい
かなるものでもよい。
Further, in the above embodiment, as the thermoplastic resin-curable conductive material, a thermoplastic resin such as polyester resin containing a conductive filler such as Ag is used. Any conductive material may be used.

【0038】[0038]

【発明の効果】以上に説明したように、本発明の半導体
装置の実装体の製造方法によれば、半導体装置の突出接
点を回路基板上の熱可塑性の樹脂硬化型導電性材料から
なる半導体実装用の接続電極に熱圧着により接合するた
、工程に要する時間が短縮され、半導体装置の実装体
の生産性の向上を図ることができる。
As described above, according to the method for manufacturing a semiconductor device mounting body of the present invention, the semiconductor contact mounted on the circuit board is made of a thermoplastic resin-curable conductive material on the circuit board. for joining by thermocompression bonding connection electrodes of use, it reduces the time required for enough engineering, it is possible to improve the implementation of the productivity of the semiconductor device.

【0039】また、熱圧着のための加熱温度は比較的低
温で済むので、半導体装置と回路基板の熱膨張係数の差
に起因する熱応力を極めて小さく抑制することができ、
よって、信頼性の向上を図ることができる。
Further, since the heating temperature for thermocompression bonding is relatively low, the thermal stress due to the difference in thermal expansion coefficient between the semiconductor device and the circuit board can be suppressed to an extremely small level,
Therefore, the reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例である半導体装置の実装工程における半
導体装置等の状態を示す部分断面図である。
FIG. 1 is a partial cross-sectional view showing a state of a semiconductor device or the like in a mounting process of a semiconductor device according to an embodiment.

【図2】実施例における半導体装置の実装体の部分断面
図である。
FIG. 2 is a partial cross-sectional view of a mounted body of a semiconductor device in an example.

【図3】従来の半導体装置の実装方法における半導体装
置の突出接点に導電性接着剤を転写する際の状態を示す
部分断面図である。
FIG. 3 is a partial cross-sectional view showing a state when a conductive adhesive is transferred to a protruding contact of a semiconductor device in a conventional semiconductor device mounting method.

【図4】従来の半導体装置の実装方法で得られる実装体
の部分断面図である。
FIG. 4 is a partial cross-sectional view of a mounting body obtained by a conventional semiconductor device mounting method.

【符号の説明】[Explanation of symbols]

1 半導体装置 2 端子電極 3 突出接点 4 回路基板 5 配線パターン 6 接続電極 7 熱圧着ツール 9 半導体装置 10 端子電極 11 突出接点 12 塗膜 13 支持基体 14 回路基板 15 接続電極 16 転写部 1 Semiconductor device 2 terminal electrode 3 protruding contact 4 circuit board 5 wiring patterns 6 connection electrodes 7 Thermocompression bonding tool 9 Semiconductor devices 10 terminal electrodes 11 protruding contact 12 coating 13 Support substrate 14 circuit board 15 Connection electrode 16 Transfer part

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平6−61305(JP,A) 特開 昭63−287026(JP,A) 特開 平5−21523(JP,A) 特開 平4−37146(JP,A) 特開 平5−283480(JP,A) 特開 平5−36760(JP,A)   ─────────────────────────────────────────────────── ─── Continued front page       (56) Reference JP-A-6-61305 (JP, A)                 JP 63-287026 (JP, A)                 JP-A-5-21523 (JP, A)                 JP-A-4-37146 (JP, A)                 JP-A-5-283480 (JP, A)                 JP-A-5-36760 (JP, A)

Claims (8)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体装置をフェースダウンで回路基板
に実装する半導体装置の実装方法において、 半導体装置の端子電極に突出接点を形成する工程と、 熱可塑性の樹脂硬化型導電性材料を用いて、上記回路基
板の表面が平坦な金属配線パターン上に半導体装置実装
用の接続電極を形成する工程と、 上記半導体装置の突出接点を上記回路基板の表面が平坦
金属配線パターン上の接続電極に熱圧着して半導体装
置と回路基板とを接合する工程と を備えたことを特徴とする半導体装置の実装体の製造方
法。
1. A semiconductor device mounting method for mounting a semiconductor device face down on a circuit board, comprising the steps of forming a protruding contact on a terminal electrode of the semiconductor device, and using a thermoplastic resin-curable conductive material. a step of the surface of the circuit board to form a connection electrode for the semiconductor device mounted on a flat metal wiring pattern, a protruding contact point of the semiconductor device the surface of the circuit board flat
And a step of joining the semiconductor device and the circuit board by thermocompression bonding to the connection electrode on the metal wiring pattern.
【請求項2】 請求項1記載の半導体装置の実装体の製
造方法において、 上記半導体装置の端子電極に突出接点を形成する工程で
は、メッキ法により突出接点を形成することを特徴とす
る半導体装置の実装体の製造方法。
2. The semiconductor device mounting method according to claim 1, wherein in the step of forming the protruding contact on the terminal electrode of the semiconductor device, the protruding contact is formed by a plating method. Manufacturing method of mounting body of.
【請求項3】 請求項1記載の半導体装置の実装体の製
造方法において、 上記半導体装置の端子電極に突出接点を形成する工程で
は、ワイヤボンディング法により突出接点を形成するこ
とを特徴とする半導体装置の実装体の製造方法。
3. The semiconductor device mounting method according to claim 1, wherein in the step of forming the protruding contact on the terminal electrode of the semiconductor device, the protruding contact is formed by a wire bonding method. A method for manufacturing a device assembly.
【請求項4】 請求項1,2又は3記載の半導体装置の
実装体の製造方法において、 上記金属配線パターンは、焼結型導電性材料を用いて上
記回路基板の一部位に形成されていることを特徴とする
半導体装置の実装体の製造方法。
4. The method for manufacturing a semiconductor device package according to claim 1, 2, or 3, wherein the metal wiring pattern is formed at one portion of the circuit board by using a sintered conductive material. A method for manufacturing a semiconductor device package, comprising:
【請求項5】 請求項1,2又は3記載の半導体装置の
実装体の製造方法において、 上記金属配線パターンは、導電性材料の金属箔を用いて
上記回路基板の一部位に形成されていることを特徴とす
る半導体装置の実装体の製造方法。
5. The method for manufacturing a semiconductor device package according to claim 1, 2, or 3, wherein the metal wiring pattern is formed on a part of the circuit board by using a metal foil of a conductive material. A method for manufacturing a semiconductor device package, comprising:
【請求項6】 請求項1,2,3,4又は5記載の半導
体装置の実装体の製造方法において、 上記半導体装置と回路基板とを接合する工程では、半導
体装置を回路基板の接続電極が可塑状態となる温度以上
の温度に加熱することを特徴とする半導体装置の実装体
の製造方法。
6. The method of manufacturing a semiconductor device package according to claim 1, 2, 3, 4, or 5, wherein in the step of joining the semiconductor device and the circuit board, the semiconductor device is connected to a connection electrode of the circuit board. A method for manufacturing a semiconductor device package, comprising heating to a temperature not lower than a plastic state.
【請求項7】 請求項1,2,3,4又は5記載の半導
体装置の実装体の製造方法において、 上記半導体装置と回路基板とを接合する工程では、回路
基板を接続電極が可塑状態となる温度以上の温度に加熱
することを特徴とする半導体装置の実装体の製造方法。
7. The method of manufacturing a semiconductor device package according to claim 1, 2, 3, 4, or 5, wherein in the step of joining the semiconductor device and the circuit board, the connection electrode of the circuit board is in a plastic state. A method for manufacturing a semiconductor device package, comprising heating the semiconductor device to a temperature equal to or higher than the following temperature.
【請求項8】 請求項1,2,3,4,5,6又は7記
載の半導体装置の実装体の製造方法において、 上記熱可塑性の樹脂硬化型導電性材料として、少なくと
も熱可塑性樹脂と導電性フィラーとを含む材料を用いる
ことを特徴とする半導体装置の実装体の製造方法。
8. The method for manufacturing a semiconductor device mounting body according to claim 1, 2, 3, 4, 5, 6 or 7, wherein at least a thermoplastic resin and a conductive material are used as the thermoplastic resin-curable conductive material. A method of manufacturing a semiconductor device package, comprising using a material containing a conductive filler.
JP11254894A 1994-05-26 1994-05-26 Method of manufacturing semiconductor device package Expired - Fee Related JP3472342B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11254894A JP3472342B2 (en) 1994-05-26 1994-05-26 Method of manufacturing semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11254894A JP3472342B2 (en) 1994-05-26 1994-05-26 Method of manufacturing semiconductor device package

Publications (2)

Publication Number Publication Date
JPH07321162A JPH07321162A (en) 1995-12-08
JP3472342B2 true JP3472342B2 (en) 2003-12-02

Family

ID=14589421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11254894A Expired - Fee Related JP3472342B2 (en) 1994-05-26 1994-05-26 Method of manufacturing semiconductor device package

Country Status (1)

Country Link
JP (1) JP3472342B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001005602A1 (en) * 1999-07-21 2001-01-25 Ibiden Co., Ltd. Pc card and method for manufacturing the same
JP2004140169A (en) 2002-10-17 2004-05-13 Rohm Co Ltd Packaged semiconductor device

Also Published As

Publication number Publication date
JPH07321162A (en) 1995-12-08

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