JPH09266227A - Bonding method of electronic parts - Google Patents

Bonding method of electronic parts

Info

Publication number
JPH09266227A
JPH09266227A JP8073531A JP7353196A JPH09266227A JP H09266227 A JPH09266227 A JP H09266227A JP 8073531 A JP8073531 A JP 8073531A JP 7353196 A JP7353196 A JP 7353196A JP H09266227 A JPH09266227 A JP H09266227A
Authority
JP
Japan
Prior art keywords
conductive
substrate
bump
circuit pattern
bonding agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8073531A
Other languages
Japanese (ja)
Other versions
JP3264173B2 (en
Inventor
Hideki Nagafuku
秀喜 永福
Tadahiko Sakai
忠彦 境
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP07353196A priority Critical patent/JP3264173B2/en
Publication of JPH09266227A publication Critical patent/JPH09266227A/en
Application granted granted Critical
Publication of JP3264173B2 publication Critical patent/JP3264173B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To restrict bad bonding at electronic parts by intervening a conductive anaerobic bonding agent between a bump and a circuit pattern, and hardening the conductive anaerobic bonding agent. SOLUTION: A copper bump 6 is protruded on the lower surface of electronic parts 8, and a circuit pattern 12 of a substrate 11 also comprises copper. Herein, the bump 9 is directed downward, and a conductive anaerobic bonding agent 11 is applied on a lower part of the bump 9. As the conductive anaerobic bonding agent there is used one where a catalyst such as organic peroxide, a stabilizer such as qunone, and charged particles of noble metal including silver or silver palladium are added to a main agent such as urethaneacrylate, for example. A ceramics substrate unlikely to thermally deform is preferable as the substrate 11. The electronic parts 8 are pressed downward, and the conductive anaerobic bonding agent 10 applied on the lower part of the bump 9 is pressed against the circuit pattern, and hardened in the state where air is interrupted nearer to come into the conductive anaerobic bonding agent 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、接着剤を用いて電
子部品に備えられたバンプを基板の回路パターンに接合
する電子部品の接合方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for joining electronic components, in which bumps provided on the electronic components are joined to a circuit pattern on a substrate using an adhesive.

【0002】[0002]

【従来の技術】近年、電子部品には下面に金属からなる
バンプを備えたものが出現し、この電子部品のバンプを
導電性を有する接着剤を用いて基板の回路パターンに接
合する工法が実用化するに至っている。
2. Description of the Related Art In recent years, some electronic components have bumps made of metal on their lower surfaces, and a method of bonding the bumps of this electronic component to a circuit pattern on a substrate by using a conductive adhesive is put into practical use. Has come to change.

【0003】次に図2を参照しながら、従来の電子部品
の接合方法について説明する。図2(a)において、1
はガラスエポキシ又はセラミックスなどからなる基板、
2,3は基板1の表面に形成された回路パターンであ
り、これらの回路パターン2,3には接着剤4が塗布さ
れている。また5は半導体チップを主体とする電子部品
であり、その下面には複数のバンプ6,7が突設されて
いる。
Next, a conventional method for joining electronic components will be described with reference to FIG. In FIG. 2A, 1
Is a substrate made of glass epoxy or ceramics,
Circuit patterns 2 and 3 are formed on the surface of the substrate 1, and an adhesive 4 is applied to these circuit patterns 2 and 3. Reference numeral 5 is an electronic component mainly composed of a semiconductor chip, and a plurality of bumps 6 and 7 are projectingly provided on the lower surface thereof.

【0004】そして、従来の電子部品の接合方法では、
図2(b)に示すように、バンプ6,7を接着剤4に接
触させ、150°C以上に加温して接着剤4を硬化させ
る。これにより、バンプ6,7を回路パターン2,3に
固着させると共に、両者を電気的に接続するというもの
である。
In the conventional method of joining electronic parts,
As shown in FIG. 2B, the bumps 6 and 7 are brought into contact with the adhesive 4 and heated to 150 ° C. or higher to cure the adhesive 4. As a result, the bumps 6 and 7 are fixed to the circuit patterns 2 and 3, and the both are electrically connected.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
電子部品の接合方法では、接着剤4として銀あるいは
銀,パラジウムを含有する熱硬化性接着剤を用いてお
り、この接着剤4の硬化温度は150°C以上というよ
うに、室温に対して相当高い。また、基板1と電子部品
5とにおいて、線膨張係数に大きな差がある。もちろ
ん、基板1の方が電子部品5よりもはるかに熱的な変形
を起こしやすい。
However, in the conventional method of joining electronic components, a thermosetting adhesive containing silver or silver or palladium is used as the adhesive 4, and the curing temperature of the adhesive 4 is It is considerably higher than room temperature, such as above 150 ° C. Further, there is a large difference in linear expansion coefficient between the substrate 1 and the electronic component 5. Of course, the substrate 1 is much more susceptible to thermal deformation than the electronic component 5.

【0006】このため、図2(b)に示すように、硬化
温度に達して接着剤4が硬化した後、室温に戻すと、電
子部品5はほとんど変形しないが基板1はかなり変形し
て反ってしまう。したがって図2(c)あるいは図2
(c)のA部を拡大した図2(d)に示すように、基板
1と電子部品5の接合部にあたるところの、硬化した接
着剤4と回路パターン2との界面付近で接着剤4が破断
してしまい、接合不良を発生することがあった。
Therefore, as shown in FIG. 2B, when the adhesive 4 is hardened and hardened and then returned to room temperature, the electronic component 5 is hardly deformed, but the substrate 1 is considerably deformed and warped. Will end up. Therefore, as shown in FIG.
As shown in FIG. 2D in which the portion A of FIG. 2C is enlarged, the adhesive 4 is formed near the interface between the cured adhesive 4 and the circuit pattern 2 at the joint between the substrate 1 and the electronic component 5. There was a case where it was broken and a defective joint was generated.

【0007】そこで本発明は、接合不良を抑制できる電
子部品の接合方法を提供することを目的とする。
[0007] Therefore, an object of the present invention is to provide a method for joining electronic components, which can suppress joining defects.

【0008】[0008]

【課題を解決するための手段】本発明の電子部品の接合
方法は、電子部品の下面に形成されたバンプを基板の回
路パターンに接合する電子部品の接合方法であって、バ
ンプと回路パターンとの間に導電性嫌気接着剤を介在さ
せ、導電性嫌気接着剤を硬化させるものである。
A method for joining electronic components according to the present invention is a method for joining electronic components in which bumps formed on the lower surface of the electronic component are joined to a circuit pattern on a substrate. The conductive anaerobic adhesive is interposed between the two to cure the conductive anaerobic adhesive.

【0009】[0009]

【発明の実施の形態】請求項1では、電子部品の下面に
形成されたバンプを基板の回路パターンに接合する電子
部品の接合方法であって、バンプと回路パターンとの間
に導電性嫌気接着剤を介在させ、導電性嫌気接着剤を硬
化させることにしているので、従来技術に比べより低温
で接着剤による接合を行うことができ、温度差に起因す
る接着剤の破断現象を少なくすることができる。
According to a first aspect of the present invention, there is provided a method of joining an electronic component, wherein a bump formed on a lower surface of the electronic component is joined to a circuit pattern of a substrate, which is a conductive anaerobic bond between the bump and the circuit pattern. Since the conductive anaerobic adhesive is to be cured with the agent interposed, it is possible to perform the bonding with the adhesive at a lower temperature than the conventional technology, and to reduce the fracture phenomenon of the adhesive due to the temperature difference. You can

【0010】次に図面を参照しながら、本発明の実施の
形態について説明する。図1は、本発明の一実施の形態
における電子部品の接合方法の工程説明図である。本形
態では、電子部品8の下面に銅からなるバンプ9を突設
してあり、図1(c)に示すように基板11の回路パタ
ーン12も銅から構成している。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a process explanatory diagram of a method for joining electronic components according to an embodiment of the present invention. In this embodiment, bumps 9 made of copper are provided on the lower surface of the electronic component 8, and the circuit pattern 12 of the substrate 11 is also made of copper, as shown in FIG.

【0011】さてまず図1(a)に示すようにバンプ9
を下向きにして、バンプ9の下部に導電性嫌気接着剤1
0を塗布する。この導電性嫌気接着剤10としては、例
えば次表の成分を有するものが好適である。
First, as shown in FIG.
With the conductive anaerobic adhesive 1 on the bottom of the bump 9.
Apply 0. As the conductive anaerobic adhesive 10, for example, one having the components shown in the following table is suitable.

【0012】[0012]

【表1】 [Table 1]

【0013】この導電性嫌気接着剤10の硬化温度は、
基板11としてガラスエポキシ基板を用いた際の基板1
1のガラス転移温度(約120°C)よりも低い。ま
た、基板11としてセラミックス基板を用いると、セラ
ミックス基板はガラスエポキシ基板よりも熱的変形を起
こしにくいので、一層好適である。即ち、本発明の基板
11としては、ガラスエポキシ基板、セラミックス基板
のいずれを用いてもよい。
The curing temperature of the conductive anaerobic adhesive 10 is
Substrate 1 when a glass epoxy substrate is used as the substrate 11
Below the glass transition temperature of 1 (about 120 ° C). Further, when a ceramics substrate is used as the substrate 11, the ceramics substrate is less likely to be thermally deformed than the glass epoxy substrate, and thus is more preferable. That is, as the substrate 11 of the present invention, either a glass epoxy substrate or a ceramic substrate may be used.

【0014】そして、図1(c)に示すように、矢印N
1で示すように、電子部品8を下向きに押圧して、バン
プ9の下部に塗布された導電性嫌気接着剤10を回路パ
ターン12に押し付ける。これにより、空気が遮断さ
れ、導電性嫌気接着剤10の内部は空気に触れない状態
となり硬化を開始する。
Then, as shown in FIG. 1C, an arrow N
As indicated by 1, the electronic component 8 is pressed downward to press the conductive anaerobic adhesive 10 applied on the lower portion of the bump 9 against the circuit pattern 12. As a result, the air is blocked, and the inside of the conductive anaerobic adhesive 10 does not come into contact with air, and the curing starts.

【0015】ここで、図1(c)の状態において、室温
のまま導電性嫌気接着剤10を硬化させてもよい。この
ようにしても、回路パターン12及びバンプ9が銅から
構成されており、銅から生成するイオンは導電性嫌気接
着剤10の硬化を促進する触媒としての作用を奏するか
らである。このような金属としては、銅の他に、ニッケ
ル,アルミニウムなどがあり、ニッケル等の金属を用い
てもよい。
Here, in the state of FIG. 1C, the conductive anaerobic adhesive 10 may be cured at room temperature. Even in this case, the circuit pattern 12 and the bumps 9 are made of copper, and the ions generated from copper act as a catalyst for promoting the curing of the conductive anaerobic adhesive 10. Examples of such a metal include nickel and aluminum in addition to copper, and a metal such as nickel may be used.

【0016】さらに導電性嫌気接着剤10の硬化を促進
するには、温度を室温以上基板11のガラス転移温度
(約120°C)以下に加温する。上述した導電性嫌気
接着剤10を用いると、従来の電子部品の接合方法のよ
うに、ガラス転移温度を超えない高温まで加熱しなくと
もよい。したがって、室温に戻しても基板11が大きく
反るようなことはなく、接着剤の破断を防止できる。
Further, in order to accelerate the curing of the conductive anaerobic adhesive 10, the temperature is heated to room temperature or higher and the glass transition temperature (about 120 ° C.) or lower of the substrate 11. When the conductive anaerobic adhesive 10 described above is used, it is not necessary to heat to a high temperature that does not exceed the glass transition temperature, unlike the conventional method for joining electronic components. Therefore, even if the temperature is returned to room temperature, the substrate 11 does not largely warp, and the breakage of the adhesive can be prevented.

【0017】[0017]

【発明の効果】本発明の電子部品の接合方法は、電子部
品の下面に形成されたバンプを基板の回路パターンに接
合する電子部品の接合方法であって、バンプと回路パタ
ーンとの間に導電性嫌気接着剤を介在させ、導電性嫌気
接着剤を硬化させるので、基板の熱的変形が問題となら
ない低温で接合を行うことができ、接合不良を抑制する
ことができる。
The method for joining electronic components of the present invention is a method for joining electronic components in which bumps formed on the lower surface of the electronic component are joined to the circuit pattern of the substrate, and the bumps and the circuit pattern are electrically conductive. Since the conductive anaerobic adhesive is cured by interposing the anaerobic anaerobic adhesive, it is possible to perform the bonding at a low temperature at which the thermal deformation of the substrate does not pose a problem, and it is possible to suppress the bonding failure.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)本発明の一実施の形態における電子部品
の接合方法の工程説明図 (b)本発明の一実施の形態における電子部品の接合方
法の工程説明図 (c)本発明の一実施の形態における電子部品の接合方
法の工程説明図
FIG. 1A is a process explanatory diagram of a method for joining electronic components according to an embodiment of the present invention. FIG. 1B is a process explanatory diagram of a method for joining electronic components according to an embodiment of the present invention. Process explanatory drawing of the joining method of the electronic component in one Embodiment

【図2】(a)従来の電子部品の接合方法の工程説明図 (b)従来の電子部品の接合方法の工程説明図 (c)従来の電子部品の接合方法の工程説明図 (d)従来の電子部品の接合方法の工程説明図FIG. 2A is a process explanatory view of a conventional electronic component joining method. FIG. 2B is a process explanatory diagram of a conventional electronic component joining method. Of process steps for joining electronic components

【符号の説明】[Explanation of symbols]

8 電子部品 9 バンプ 10 導電性嫌気接着剤 11 基板 12 回路パターン 8 Electronic Components 9 Bumps 10 Conductive Anaerobic Adhesive 11 Substrate 12 Circuit Pattern

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】電子部品の下面に形成されたバンプを基板
の回路パターンに接合する電子部品の接合方法であっ
て、前記バンプと前記回路パターンとの間に導電性嫌気
接着剤を介在させ、前記導電性嫌気接着剤を硬化させる
ことを特徴とする電子部品の接合方法。
1. A method of joining an electronic component, wherein a bump formed on a lower surface of the electronic component is joined to a circuit pattern of a substrate, wherein a conductive anaerobic adhesive is interposed between the bump and the circuit pattern. A method for joining electronic components, characterized in that the conductive anaerobic adhesive is cured.
【請求項2】前記硬化は、室温以上であり前記基板のガ
ラス転移温度以下で行われることを特徴とする請求項1
記載の電子部品の接合方法。
2. The curing is performed at room temperature or above and below the glass transition temperature of the substrate.
A method for joining electronic components as described.
【請求項3】前記基板は有機基板であって、前記導電性
嫌気接着剤の硬化温度が前記基板のガラス転移温度より
も小さいことを特徴とする請求項1記載の電子部品の接
合方法。
3. The method for joining electronic components according to claim 1, wherein the substrate is an organic substrate, and a curing temperature of the conductive anaerobic adhesive is lower than a glass transition temperature of the substrate.
【請求項4】前記バンプ及び前記回路パターンは、前記
導電性嫌気接着剤の硬化を促進する触媒となる金属から
構成されていることを特徴とする請求項1記載の電子部
品の接合方法。
4. The method for joining electronic components according to claim 1, wherein the bumps and the circuit patterns are made of a metal serving as a catalyst for promoting the curing of the conductive anaerobic adhesive.
JP07353196A 1996-03-28 1996-03-28 How to join electronic components Expired - Fee Related JP3264173B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07353196A JP3264173B2 (en) 1996-03-28 1996-03-28 How to join electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07353196A JP3264173B2 (en) 1996-03-28 1996-03-28 How to join electronic components

Publications (2)

Publication Number Publication Date
JPH09266227A true JPH09266227A (en) 1997-10-07
JP3264173B2 JP3264173B2 (en) 2002-03-11

Family

ID=13520918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07353196A Expired - Fee Related JP3264173B2 (en) 1996-03-28 1996-03-28 How to join electronic components

Country Status (1)

Country Link
JP (1) JP3264173B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003098681A1 (en) * 2002-05-16 2003-11-27 National University Of Singapore Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
JP2007231966A (en) * 2006-02-27 2007-09-13 Hitachi Powdered Metals Co Ltd Sintered hydrodynamic bearing manufacturing method
CN105405825A (en) * 2015-12-09 2016-03-16 南通富士通微电子股份有限公司 Chip on film package structure
CN105551986A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method
CN105551987A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003098681A1 (en) * 2002-05-16 2003-11-27 National University Of Singapore Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
JP2007231966A (en) * 2006-02-27 2007-09-13 Hitachi Powdered Metals Co Ltd Sintered hydrodynamic bearing manufacturing method
CN105405825A (en) * 2015-12-09 2016-03-16 南通富士通微电子股份有限公司 Chip on film package structure
CN105551986A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method
CN105551987A (en) * 2015-12-09 2016-05-04 南通富士通微电子股份有限公司 COF (Chip on Flex) packaging method

Also Published As

Publication number Publication date
JP3264173B2 (en) 2002-03-11

Similar Documents

Publication Publication Date Title
WO2008032866A1 (en) Electronic components mounting adhesive, manufacturing method of an electronic components mounting adhesive, electronic components mounted structure, and manufacturing method of an electronic components mounted structure
JPH11145336A (en) Method and structure for mounting of electronic component with bump
JPH10223686A (en) Semiconductor mounting method
JP3264173B2 (en) How to join electronic components
US5817542A (en) Method for bonding electronic components
JP2001308146A (en) Apparatus for installing semiconductor chip on chip carrier
JPS601849A (en) Connecting method of electronic part
JPS63151033A (en) Manufacture of semiconductor device
JPH10125734A (en) Semiconductor unit and manufacturing method thereof
JP3261981B2 (en) Bonding method and bonding structure for work with bump
JP2002110715A (en) Manufacturing method of semiconductor device
JP3472342B2 (en) Method of manufacturing semiconductor device package
JP3348830B2 (en) Solder bump bonding apparatus and solder bump bonding method
JPH03209831A (en) Semiconductor device
JP2002016104A (en) Mounting method of semiconductor device and manufacturing method of semiconductor device mounted assembly
JP3255796B2 (en) Semiconductor device mounting method
JP2002170848A (en) Circuit board
JPH065659A (en) Mounting method of semiconductor element
JP2003258030A (en) Electronic component mounting method
JPH10163230A (en) Semiconductor mounting method
JPH05283555A (en) Semiconductor device
JPH08153750A (en) Electronic device assembly, and manufacture thereof
JP2943912B2 (en) Semiconductor device and manufacturing method thereof
JP2780523B2 (en) Semiconductor device mounting method
JP2002289644A (en) Method for joining semiconductor element and joining apparatus

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees