JPH1117050A - Circuit board and manufacture thereof - Google Patents
Circuit board and manufacture thereofInfo
- Publication number
- JPH1117050A JPH1117050A JP9164760A JP16476097A JPH1117050A JP H1117050 A JPH1117050 A JP H1117050A JP 9164760 A JP9164760 A JP 9164760A JP 16476097 A JP16476097 A JP 16476097A JP H1117050 A JPH1117050 A JP H1117050A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- circuit board
- semiconductor element
- substrate
- conductive paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/82385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子を搭載す
るための回路基板及びこの回路基板の製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for mounting a semiconductor device and a method for manufacturing the circuit board.
【０００２】[0002]
【従来の技術】従来、回路基板に半導体素子を搭載する
手段としては、図１４に示すように半導体素子４５の突
起電極４７の先端部に導電性接着剤５０を供給し、回路
基板４９の対応する電極４８上に半導体素子４５を位置
決めして載置し、加熱して導電性接着剤５０を硬化させ
ることにより図１５に示すような接合を得ている。2. Description of the Related Art Conventionally, as a means for mounting a semiconductor element on a circuit board, a conductive adhesive 50 is supplied to the tip of a protruding electrode 47 of a semiconductor element 45 as shown in FIG. The semiconductor element 45 is positioned and mounted on the electrode 48 to be formed, and is heated to cure the conductive adhesive 50, thereby obtaining the bonding as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この接
合方式は、回路基板の電極と半導体素子の突起電極とを
導電性接着剤で接合したものであるため、特に水平方向
の強度が低く、容易に半導体素子が回路基板から剥離す
るなど、取り扱いが困難であるという問題を有してい
た。However, in this joining method, since the electrodes of the circuit board and the projecting electrodes of the semiconductor element are joined with a conductive adhesive, the strength in the horizontal direction is particularly low and the joining method is easy. There is a problem that handling is difficult, for example, the semiconductor element peels off from the circuit board.
【０００４】本発明は、回路基板と半導体素子との接合
強度を高め、高い信頼性を有する接合を得ることを目的
とする。An object of the present invention is to increase the bonding strength between a circuit board and a semiconductor element and obtain a bonding having high reliability.
【０００５】[0005]
【課題を解決するための手段】この課題を解決するため
に本発明は、回路基板上の電極に、半導体素子の突起電
極形状と合致した形状の凹部を設け、回路基板に載置さ
れた半導体素子の突起電極を凹部に嵌合するようにした
ものである。この本発明によれば、回路基板と半導体素
子との接合強度を高め、高い信頼性を有する接合を得る
ことができる。SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a semiconductor device mounted on a circuit board, wherein the electrode on the circuit board is provided with a concave portion having a shape matching the shape of the protruding electrode of the semiconductor element. The projection electrode of the element is fitted in the recess. According to the present invention, it is possible to increase the bonding strength between the circuit board and the semiconductor element and obtain a bonding having high reliability.
【０００６】[0006]
【発明の実施の形態】本発明の請求項１に記載の発明
は、基板上に導体ペーストを供給した後に焼成して電極
を形成する回路基板において、基板上の電極に半導体素
子の突起電極形状と合致した形状の凹部を形成したこと
を特徴とする回路基板であり、基板上に載置された半導
体素子の突起電極はそれぞれ対応する回路基板上の電極
に設けられた凹部に嵌合した状態で実装されるので、水
平方向の応力特に衝撃力に対し、回路基板上の電極の破
壊強度に相当する抗力が得られるという作用を有する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a circuit board in which a conductive paste is supplied onto a substrate and then fired to form an electrode. A circuit board characterized by forming a concave portion having a shape conforming to the above, wherein the protruding electrodes of the semiconductor elements mounted on the substrate are fitted into the concave portions provided on the corresponding electrodes on the circuit board, respectively. Therefore, it has an effect that a resistance corresponding to the breaking strength of the electrode on the circuit board can be obtained against horizontal stress, particularly impact force.
【０００７】請求項２に記載の発明は、基板上の電極に
形成した凹部表面に導電性接着剤層を設けたことを特徴
とする回路基板であり、基板上に載置された半導体素子
の突起電極はそれぞれ対応する回路基板上の電極に設け
られた凹部に嵌合した状態で実装されることにより水平
方向の応力特に衝撃力に対し、回路基板上の電極の破壊
強度に匹敵する抗力を発生させ、さらに、導電性接着剤
層を凹部表面に設け、導電性接着剤による接合面積を拡
大することにより、垂直方向の応力に対しても抗力が得
られるという作用を有する。According to a second aspect of the present invention, there is provided a circuit board wherein a conductive adhesive layer is provided on a surface of a concave portion formed in an electrode on the substrate. Each of the protruding electrodes is mounted in a state of being fitted into a recess provided in the corresponding electrode on the circuit board, thereby providing a resistance to horizontal stress, particularly impact force, equivalent to the breaking strength of the electrode on the circuit board. In addition, by providing a conductive adhesive layer on the surface of the concave portion and enlarging the bonding area by the conductive adhesive, a resistance can be obtained even with respect to a vertical stress.
【０００８】請求項３に記載の発明は、基板上の電極に
形成した凹部上面に接着剤層を設けたことを特徴とする
回路基板であり、基板上に載置された半導体素子の突起
電極はそれぞれ対応する回路基板上の電極に設けられた
凹部に嵌合した状態で実装されることにより水平方向の
応力特に衝撃力に対し、回路基板上の電極の破壊強度に
匹敵する抗力を発生させ、さらに、接着剤層を電極の上
面に設け、半導体素子と回路基板の電極とを接着剤によ
り接合することにより、垂直方向の応力に対しても抗力
が得られるという作用を有する。According to a third aspect of the present invention, there is provided a circuit board, wherein an adhesive layer is provided on an upper surface of a concave portion formed in an electrode on the board, wherein the projecting electrode of a semiconductor element mounted on the board is provided. Are mounted in a state fitted to the recesses provided in the electrodes on the corresponding circuit board, thereby generating a resistance equivalent to the breaking strength of the electrodes on the circuit board against horizontal stress, especially impact force. Further, by providing an adhesive layer on the upper surface of the electrode and joining the semiconductor element and the electrode of the circuit board with an adhesive, a resistance can be obtained even in a vertical stress.
【０００９】請求項４に記載の発明は、基板上に導体ペ
ーストを供給した後に焼成して電極を形成する回路基板
において、基板上の電極に半導体素子の突起電極の体積
よりも小さい凹部を形成したことを特徴とする回路基板
であり、基板上に半導体素子を載置した後に裏面から加
圧することにより、突起電極が回路基板上の電極に強固
に接合されるという作用を有する。According to a fourth aspect of the present invention, in a circuit board in which a conductive paste is supplied onto a substrate and then fired to form an electrode, a concave portion smaller than the volume of the projecting electrode of the semiconductor element is formed in the electrode on the substrate. A circuit board characterized in that the protruding electrodes are firmly joined to the electrodes on the circuit board by pressing the back surface after mounting the semiconductor element on the board.
【００１０】請求項５に記載の発明は、基板上に導体ペ
ーストを供給した後に焼成して電極を形成する回路基板
において、基板上に供給された導体ペーストを半導体の
突起電極で押圧し、導体ペーストの半導体素子が載置さ
れる位置に突起電極形状と合致した形状の凹部を形成
し、焼成することを特徴とする回路基板の製造方法であ
り、基板上に供給された導体ペースト上の半導体素子が
載置される位置に、該半導体素子の突起電極を押圧し、
凹部を形成した後に該導体ペーストを焼成して電極を形
成することにより、載置される半導体素子の突起電極と
回路基板上の電極とが隙間無く接合される電極を形成す
ることができるという作用を有する。According to a fifth aspect of the present invention, there is provided a circuit board in which a conductive paste is supplied onto a substrate and then baked to form an electrode. A method of manufacturing a circuit board, comprising: forming a recess having a shape corresponding to the shape of a protruding electrode at a position where a semiconductor element of a paste is to be mounted; At the position where the element is mounted, pressing the protruding electrode of the semiconductor element,
By forming the electrodes by firing the conductive paste after forming the concave portions, it is possible to form an electrode in which the protruding electrodes of the semiconductor element to be mounted and the electrodes on the circuit board are joined without any gap. Having.
【００１１】請求項６に記載の発明は、導体ペーストを
基板上に供給した後に焼成して電極を形成する回路基板
において、基板上に供給された導体ペーストを所望寸法
の突起を有する金型で押圧し、導体ペーストの半導体素
子が載置される位置に所望寸法の凹部を形成し、焼成す
ることを特徴とする回路基板の製造方法であり、基板上
に供給された導体ペースト上の半導体素子が載置される
位置に、所望の寸法の突起を有する金型を連続して移動
し、押圧して凹部を連続して形成した後に該導体ペース
トを焼成して電極を形成することにより、半導体素子の
突起電極を加圧して強固に接合される電極を形成するこ
とができるという作用を有する。According to a sixth aspect of the present invention, in a circuit board in which electrodes are formed by supplying a conductive paste onto a substrate and then firing the same, the conductive paste supplied on the substrate is formed by a mold having projections of desired dimensions. A method for manufacturing a circuit board, comprising: pressing, forming a recess having a desired size at a position where a semiconductor element of a conductive paste is to be placed, and firing the semiconductor element, wherein the semiconductor element on the conductive paste supplied to the substrate is provided. A mold having projections of a desired size is continuously moved to a position where the semiconductor device is mounted, and pressed to form a concave portion continuously, and then the conductive paste is fired to form an electrode. This has the effect that an electrode that is strongly bonded can be formed by pressing the protruding electrode of the element.
【００１２】請求項７に記載の発明は、半導体素子の突
起電極の体積よりも小さい凹部が形成された電極を有す
る回路基板への半導体素子の実装方法において、前記回
路基板の電極の凹部に半導体素子を位置決め載置した後
に、半導体素子の裏面より加圧し、半導体素子の突起電
極と回路基板の凹部を有する電極とを互いに変形させる
ことにより接合することを特徴とする半導体素子の実装
方法であり、半導体素子の突起電極の体積よりも小さい
凹部が形成された回路基板上の電極に対して、半導体素
子の突起電極を位置決めした後に載置し、さらに半導体
素子を加圧することにより、電極と半導体素子の突起電
極とを互いに変形させて、隙間なく且つ強固に接合する
という作用を有する。According to a seventh aspect of the present invention, there is provided a method of mounting a semiconductor element on a circuit board having an electrode formed with a recess smaller than the volume of the projecting electrode of the semiconductor element. A method of mounting a semiconductor element, comprising: positioning and mounting an element, pressing the semiconductor element from the back surface thereof, and bonding the projecting electrode of the semiconductor element and the electrode having a recess of the circuit board by deforming each other. By positioning the protruding electrode of the semiconductor element with respect to the electrode on the circuit board on which the concave portion smaller than the volume of the protruding electrode of the semiconductor element is formed, and then placing the protruding electrode on the circuit board, and further pressing the semiconductor element, the electrode and the semiconductor It has the effect of deforming the protruding electrodes of the element to each other and joining them tightly without gaps.
【００１３】以下本発明の実施の形態について、図１か
ら図１３を用いて説明する。図１は本発明の請求項１に
記載の回路基板の電極部の構造を示したものであり、図
１において、５は半導体素子１上にボールボンティング
法あるいはメッキ法などにより形成された突起電極３と
回路基板６とを接続するための電極部である。半導体素
子１はこの回路基板６の対応する電極５上に位置決めし
た後に載置される。また、この電極５には半導体素子１
上に形成された突起電極３の凸部に合致して嵌合する凹
部４が予め設けてある。このとき図２に示すように、回
路基板６上の電極５の凹部４の形状は、載置される半導
体素子１上の突起電極３の形状と合致するように形成さ
れているために、載置された半導体素子１の突起電極３
は、それぞれ対応する回路基板６上の電極５に設けられ
た凹部４に収められた状態で嵌合するため、回路基板上
の電極と半導体素子の突起電極との密着により、水平方
向の応力に対する抗力が得られる。この状態で図３に示
すようにエポキシ等の樹脂７により間隙を充填すれば、
垂直方向の衝撃力に対しても大きな抗力を発揮すること
ができる。従って、該基板６に突起電極３を有する半導
体素子１を実装すれば、外部からの応力、特に衝撃力に
対する高い抗力を有し、高い信頼性を有する回路基板と
半導体素子の接合を得ることができる。An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a structure of an electrode portion of a circuit board according to claim 1 of the present invention. In FIG. 1, reference numeral 5 denotes a projection formed on a semiconductor element 1 by a ball bonding method or a plating method. An electrode unit for connecting the electrode 3 and the circuit board 6. The semiconductor element 1 is mounted after being positioned on the corresponding electrode 5 of the circuit board 6. The electrode 5 has the semiconductor element 1
A concave portion 4 is provided in advance so as to match and fit with the convex portion of the projecting electrode 3 formed thereon. At this time, as shown in FIG. 2, the shape of the concave portion 4 of the electrode 5 on the circuit board 6 is formed so as to match the shape of the protruding electrode 3 on the semiconductor element 1 to be mounted. Protruding electrode 3 of placed semiconductor element 1
Are fitted in the recesses 4 provided in the electrodes 5 on the corresponding circuit boards 6, respectively, so that the electrodes on the circuit boards and the protruding electrodes of the semiconductor element are in close contact with each other to prevent horizontal stress. Drag is obtained. In this state, if the gap is filled with a resin 7 such as epoxy as shown in FIG.
A large drag can be exerted against a vertical impact force. Therefore, if the semiconductor element 1 having the protruding electrodes 3 is mounted on the substrate 6, it is possible to obtain a highly reliable circuit board and a semiconductor element having high resistance against external stress, particularly impact force, and high reliability. it can.
【００１４】図４は本発明の請求項２に記載の回路基板
の電極の構造を示したものであり、図４において、１２
は半導体素子８上にボールボンティング法あるいはメッ
キ法などにより形成された突起電極１０と回路基板１３
とを接続するための電極部である。半導体素子８はこの
回路基板１３の対応する電極１２上に位置決めされた後
に載置される。また、この電極部１２には半導体素子８
上に形成された突起電極１０の凸部に合致して嵌合する
凹部１１を予め設けており、さらに、この凹部１１の表
面には導電性接着剤層１４が設けられている。このとき
図５に示すように、回路基板１３上の電極１２の凹部１
４の形状は、載置される半導体素子８上の突起電極１０
の形状と合致するように形成されているために、載置さ
れた半導体素子８の突起電極１０は、それぞれ対応する
回路基板１３上の電極１２に設けられた凹部１１に収め
られた状態で嵌合し、さらに、凹部１１の表面に設けら
れた導電性接着剤１４により、凹部１１と半導体素子８
の突起電極１０の凸部は接着されるので、回路基板上の
電極と半導体素子の突起電極との密着により、外部から
の応力、特に水平方向の応力に対する抗力が得られる。
これにより、高い信頼性を有する回路基板と半導体素子
の接合を得ることができる。FIG. 4 shows the structure of the electrode of the circuit board according to the second aspect of the present invention.
Denotes a bump electrode 10 formed on a semiconductor element 8 by a ball bonding method or a plating method, and a circuit board 13.
And an electrode section for connecting The semiconductor element 8 is mounted after being positioned on the corresponding electrode 12 of the circuit board 13. Also, the semiconductor element 8 is provided on the electrode portion 12.
A concave portion 11 is provided in advance so as to match the convex portion of the projecting electrode 10 formed thereon, and a conductive adhesive layer 14 is provided on the surface of the concave portion 11. At this time, as shown in FIG.
The shape of the projection electrode 10 on the semiconductor element 8 to be mounted is
Is formed so as to match the shape of the semiconductor element 8, and the projection electrodes 10 of the mounted semiconductor elements 8 are fitted in the concave portions 11 provided in the electrodes 12 on the corresponding circuit boards 13. Then, the conductive adhesive 14 provided on the surface of the concave portion 11 causes the concave portion 11 and the semiconductor element 8 to be joined.
Since the protrusions of the protruding electrodes 10 are adhered to each other, a close contact between the electrodes on the circuit board and the protruding electrodes of the semiconductor element provides a resistance to external stress, particularly horizontal stress.
As a result, a highly reliable connection between the circuit board and the semiconductor element can be obtained.
【００１５】図６は本発明の請求項３に記載の回路基板
の電極の構造を示したものであり、図６において、１９
は半導体素子１５上にボールボンティング法あるいはメ
ッキ法などにより形成された突起電極１７と回路基板２
０とを接続するための電極部である。半導体素子１５は
この回路基板２０の対応する電極１９上に位置決めされ
た後に載置される。また、この電極部１９には半導体素
子１５上に形成された突起電極１７の凸部に合致して嵌
合する凹部１８が予め設けられており、さらに、この凹
部１８の上面には接着剤層２１を設けている。このと
き、回路基板２０上の電極１９の凹部１８の形状は、載
置される半導体素子１５上の突起電極１７の形状と合致
するように形成されているために、図７に示したように
載置された半導体素子１５の突起電極１７は、それぞれ
対応する回路基板２０上の電極１９に設けられた凹部１
８に収められた状態で嵌合し、さらに、凹部１８の上面
に設けられた接着剤２１により、凹部１８と半導体素子
１５の電極パッド１６は接着されるので、回路基板２０
上の電極１９と半導体素子１５の突起電極１７との密着
により、外部からの応力、特に水平方向からの応力に対
する抗力が得られる。これにより、高い信頼性を有する
回路基板と半導体素子の接合を得ることができる。FIG. 6 shows the structure of the electrode of the circuit board according to the third aspect of the present invention.
Denotes a protruding electrode 17 formed on the semiconductor element 15 by a ball bonding method or a plating method and the circuit board 2.
This is an electrode section for connecting to 0. The semiconductor element 15 is mounted after being positioned on the corresponding electrode 19 of the circuit board 20. The electrode portion 19 is provided in advance with a concave portion 18 which fits and fits the convex portion of the protruding electrode 17 formed on the semiconductor element 15, and further has an adhesive layer on the upper surface of the concave portion 18. 21 are provided. At this time, since the shape of the concave portion 18 of the electrode 19 on the circuit board 20 is formed so as to match the shape of the projecting electrode 17 on the semiconductor element 15 to be mounted, as shown in FIG. The protruding electrodes 17 of the mounted semiconductor element 15 correspond to the concave portions 1 provided on the electrodes 19 on the corresponding circuit board 20.
The recess 18 and the electrode pad 16 of the semiconductor element 15 are bonded by the adhesive 21 provided on the upper surface of the recess 18.
Due to the close contact between the upper electrode 19 and the protruding electrode 17 of the semiconductor element 15, a resistance against external stress, particularly, stress in the horizontal direction can be obtained. As a result, a highly reliable connection between the circuit board and the semiconductor element can be obtained.
【００１６】図８は本発明の請求項４に記載の回路基板
の電極構造を示したものであり、図８におて、２６は半
導体素子２２上にボールボンティング法あるいはメッキ
法などにより形成された突起電極２４と回路基板２７と
を接続するための電極部である。半導体素子２２はこの
回路基板２７の対応する電極２６上に位置決めされた後
に載置され、その後半導体素子２２の裏面より１個の突
起電極あたり５０〜２００グラムの荷重で加圧される。
また、この電極２６には半導体素子２２上に形成された
突起電極２４の体積よりもその容積が小さい凹部２５が
予め設けてある。このとき図９に示すように、回路基板
２７上の電極２６の凹部２５の容積は、載置された半導
体素子２２上の突起電極２４の体積よりも小さいため
に、半導体素子２２の突起電極２４は、それぞれ対応す
る回路基板２７上の電極２６に設けられた凹部２５に互
いの弾性で変形を伴いながら食い込むような状態で結合
され、水平方向と垂直方向及び回路基板２７上の電極２
６と半導体素子２２の突起電極２４との密着により、水
平方向及び垂直方向の応力に対する抗力が得られる。こ
れにより、高い信頼性を有する回路基板と半導体素子の
接合を得ることができる。このときの突起電極の体積と
回路基板上の電極の凹部の容積の比は１０：９程度で十
分な効果が得られる。FIG. 8 shows an electrode structure of a circuit board according to a fourth aspect of the present invention. In FIG. 8, reference numeral 26 denotes a semiconductor element 22 formed by a ball bonding method or a plating method. This is an electrode portion for connecting the projected electrode 24 and the circuit board 27. The semiconductor element 22 is placed after being positioned on the corresponding electrode 26 of the circuit board 27, and is thereafter pressed from the back surface of the semiconductor element 22 with a load of 50 to 200 grams per one protruding electrode.
The electrode 26 is provided in advance with a recess 25 having a smaller volume than the volume of the protruding electrode 24 formed on the semiconductor element 22. At this time, as shown in FIG. 9, since the volume of the concave portion 25 of the electrode 26 on the circuit board 27 is smaller than the volume of the projecting electrode 24 on the mounted semiconductor element 22, Are connected in such a manner as to bite into the concave portions 25 provided in the electrodes 26 on the corresponding circuit boards 27 while being elastically deformed with each other.
6 and the protruding electrodes 24 of the semiconductor element 22 provide resistance to horizontal and vertical stresses. As a result, a highly reliable connection between the circuit board and the semiconductor element can be obtained. At this time, the ratio of the volume of the protruding electrode to the volume of the concave portion of the electrode on the circuit board is about 10: 9, and a sufficient effect can be obtained.
【００１７】図１０は本発明の請求項５に記載の回路基
板電極の製造方法を示したものであり、回路基板３２上
にスクリーン印刷法などにより導体ペースト３１を供給
した後に、半導体素子２８を所定の位置に載置し押圧す
る。このとき半導体素子２８の電極パッド２９には、ボ
ールボンティング法またはメッキ法などにより突起電極
３０が予め設けられているために、導体ペースト３１上
には、突起電極３０の形状に合致した凹部３３が形成さ
れることになる。この後回路基板３２とともに導体ペー
ストを焼成し、突起電極３０の形状に合致した凹部３３
を有する回路基板を製造することができる。このとき突
起電極１個あたりに与えられる荷重は、突起電極の高さ
５０μｍ、直径８０μｍであれば、通常３０〜８０ｇで
あるが、突起電極の変形が発生しない範囲であれば更に
荷重を加えても良い。尚、この実施例では突起電極３０
の高さと同じ厚みの導体ペーストを供給した場合を示し
たが、突起電極の高さよりも厚く導体ペーストを供給し
ても同様の効果が得られる。 図１１は本発明の請求項
６に記載の回路基板電極の製造方法を示したものであ
り、回路基板３６上にスクリーン印刷法などにより導体
ペースト３５を供給した後に、半導体素子の突起電極が
位置する場所に、突起電極の体積よりも小さい突起３４
を有する金型３５を連続して移動しながら押圧し、凹部
３７を有する電極３５を形成する。このとき金型に与え
られる荷重は、凹部の径が８０μｍ、深さが５０μｍで
あれば、通常３０〜８０ｇであるが、金型の突起が変形
しない範囲であれば更に荷重を加えても良い。この場合
では突起電極の体積よりも小さい金型を用いているが、
所望の大きさが得られれば、その大きさを縮小した突起
電極をボールボンティング法またはメッキ法などにより
半導体素子上に作成し、金型の代用として使用しても同
様の効果が得られる。この後回路基板３６とともに導体
ペースト３５を焼成し、突起電極の体積よりもその容積
が小さい凹部３７を有する回路基板を製造することがで
きる。尚、この実施例では半導体素子の突起電極の高さ
と同じ厚みの導体ペーストを供給した場合を示したが、
突起電極の高さよりも厚く導体ペーストを供給しても同
様の効果が得られる。FIG. 10 shows a method of manufacturing a circuit board electrode according to a fifth embodiment of the present invention. After a conductive paste 31 is supplied onto a circuit board 32 by a screen printing method or the like, the semiconductor element 28 is removed. It is placed at a predetermined position and pressed. At this time, since the protruding electrode 30 is previously provided on the electrode pad 29 of the semiconductor element 28 by a ball bonding method, a plating method, or the like, the concave portion 33 conforming to the shape of the protruding electrode 30 is formed on the conductive paste 31. Is formed. Thereafter, the conductive paste is fired together with the circuit board 32, and the concave portions 33 conforming to the shape of the bump electrodes 30 are formed.
Can be manufactured. At this time, the load applied to one protruding electrode is usually 30 to 80 g if the height of the protruding electrode is 50 μm and the diameter is 80 μm, but if the protruding electrode is not deformed, an additional load is applied. Is also good. In this embodiment, the projection electrode 30 is used.
Although the case where the conductive paste having the same thickness as that of the conductive paste is supplied is shown, the same effect can be obtained by supplying the conductive paste having a thickness larger than the height of the protruding electrode. FIG. 11 shows a method of manufacturing a circuit board electrode according to claim 6 of the present invention. After a conductive paste 35 is supplied onto a circuit board 36 by a screen printing method or the like, the projecting electrodes of the semiconductor element are positioned. Where the projection 34 is smaller than the volume of the projection electrode.
Is pressed while continuously moving the mold 35 having the concave portions 37 to form the electrodes 35 having the concave portions 37. At this time, the load applied to the mold is usually 30 to 80 g if the diameter of the concave portion is 80 μm and the depth is 50 μm, but a further load may be applied as long as the protrusion of the mold is not deformed. . In this case, a mold smaller than the volume of the protruding electrode is used,
If a desired size is obtained, the same effect can be obtained by forming a projecting electrode having a reduced size on a semiconductor element by a ball bonding method or a plating method and using it as a substitute for a mold. Thereafter, the conductive paste 35 is fired together with the circuit board 36, and a circuit board having a concave portion 37 whose volume is smaller than the volume of the protruding electrode can be manufactured. In this embodiment, the case where the conductive paste having the same thickness as the height of the bump electrode of the semiconductor element is supplied is shown.
The same effect can be obtained by supplying a conductive paste thicker than the height of the protruding electrode.
【００１８】図１２は本発明の請求項７に記載の半導体
素子の実装方法を示したものであり、図１２において、
４３は半導体素子３９上にボールボンティング法あるい
はメッキ法などにより形成された突起電極４１と回路基
板４４とを接続するための電極部である。このとき電極
４３には半導体素子３９上に形成された突起電極４１の
体積よりも小さい凹部４２が予め設けてある。この回路
基板４４上に半導体素子３９を位置決めして載置した後
に、あるいは同時に半導体素子の裏面より１個の突起電
極あたり５０〜２００グラムの荷重で加圧を行う。この
とき、回路基板４４上の電極４３の凹部４２の容積は、
載置された半導体素子３９上の突起電極の体積よりも小
さいために、半導体素子３９の突起電極４１はそれぞれ
対応する回路基板４４上の電極４３に設けられた凹部４
２に互いの弾性で変形を伴いながら食い込むような状態
で結合され、回路基板４４上の電極４３と半導体素子３
９の突起電極４１との密着により、水平方向及び垂直方
向の応力に対する抗力が得られる。これにより、高い信
頼性を有する回路基板と半導体素子の接合を得ることが
できる。FIG. 12 shows a method of mounting a semiconductor device according to a seventh aspect of the present invention.
Reference numeral 43 denotes an electrode portion for connecting the protruding electrode 41 formed on the semiconductor element 39 by a ball bonding method or a plating method to the circuit board 44. At this time, the electrode 43 is provided with a concave portion 42 smaller than the volume of the protruding electrode 41 formed on the semiconductor element 39 in advance. After the semiconductor element 39 is positioned and mounted on the circuit board 44, or simultaneously, pressure is applied from the back surface of the semiconductor element with a load of 50 to 200 grams per one protruding electrode. At this time, the volume of the concave portion 42 of the electrode 43 on the circuit board 44 is
Since the volume of the projecting electrodes on the mounted semiconductor element 39 is smaller than the volume of the projecting electrodes, the projecting electrodes 41 of the semiconductor element 39
2 are connected to each other in such a manner that they bite each other while being deformed by elasticity of each other.
Due to the close contact with the projection electrodes 41 of FIG. 9, a resistance to horizontal and vertical stresses is obtained. As a result, a highly reliable connection between the circuit board and the semiconductor element can be obtained.
【００１９】[0019]
【発明の効果】以上のように本発明によれば、回路基板
上の電極部と半導体素子の突起電極とが嵌合する構成と
したことにより、回路基板と半導体素子間の接合強度が
強く信頼性に優れた実装構造が実現できるという有利な
効果が得られる。As described above, according to the present invention, since the electrode portion on the circuit board and the protruding electrode of the semiconductor element are fitted, the bonding strength between the circuit board and the semiconductor element is strong and reliable. The advantageous effect that a mounting structure excellent in performance can be realized is obtained.
【図１】本発明の一実施例の形態による基板の構造を示
す断面図である。FIG. 1 is a cross-sectional view illustrating a structure of a substrate according to an embodiment of the present invention.
【図２】本発明の一実施例の形態による半導体素子の実
装構造を示す断面図である。FIG. 2 is a cross-sectional view illustrating a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図３】本発明の一実施例の形態による半導体素子の実
装構造を示す断面図である。FIG. 3 is a sectional view showing a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図４】本発明の一実施例の形態による基板の構造を示
す断面図である。FIG. 4 is a cross-sectional view illustrating a structure of a substrate according to an embodiment of the present invention.
【図５】本発明の一実施例の形態による半導体素子の実
装構造を示す断面図である。FIG. 5 is a cross-sectional view showing a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図６】本発明の一実施例の形態による基板の構造を示
す断面図である。FIG. 6 is a cross-sectional view illustrating a structure of a substrate according to an embodiment of the present invention.
【図７】本発明の一実施例の形態による半導体素子の実
装構造を示す断面図である。FIG. 7 is a cross-sectional view showing a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図８】本発明の一実施例の形態による基板の構造を示
す断面図である。FIG. 8 is a cross-sectional view illustrating a structure of a substrate according to an embodiment of the present invention.
【図９】本発明の一実施例の形態による半導体素子の実
装構造を示す断面図である。FIG. 9 is a cross-sectional view showing a mounting structure of a semiconductor device according to an embodiment of the present invention.
【図１０】本発明の一実施例による基板の製造工程を示
す断面図である。FIG. 10 is a cross-sectional view illustrating a step of manufacturing a substrate according to an embodiment of the present invention.
【図１１】本発明の一実施例による基板の製造工程を示
す断面図である。FIG. 11 is a cross-sectional view illustrating a process of manufacturing a substrate according to an embodiment of the present invention.
【図１２】本発明の一実施例による半導体素子の実装方
法を示す断面図である。FIG. 12 is a sectional view illustrating a method of mounting a semiconductor device according to an embodiment of the present invention.
【図１３】本発明の一実施例による半導体素子の実装方
法を示す断面図である。FIG. 13 is a cross-sectional view illustrating a method of mounting a semiconductor device according to an embodiment of the present invention.
【図１４】従来の基板へ半導体素子を実装した場合を示
す断面図である。FIG. 14 is a cross-sectional view showing a case where a semiconductor element is mounted on a conventional substrate.
【図１５】従来の基板へ半導体素子を実装した場合を示
す断面図である。FIG. 15 is a cross-sectional view showing a case where a semiconductor element is mounted on a conventional substrate.
１，８，１５，２２，２８，３９，４５ 半導体素子 ３，１０，１７，２４，３０，４１，４７ 突起電極 ５，１２，１９，２６，３２，４３，４８ 電極 ６，１３，２０，２７，３３，４４，４９ 回路基板 1,8,15,22,28,39,45 Semiconductor device 3,10,17,24,30,41,47 Protruding electrode 5,12,19,26,32,43,48 Electrode 6,13,20, 27, 33, 44, 49 circuit board
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 3/34 ５０１ Ｈ０５Ｋ 3/34 ５０１Ｅ ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H05K 3/34 501 H05K 3/34 501E
Claims (7)
成して電極を形成する回路基板において、基板上の電極
に半導体素子の突起電極形状と合致した形状の凹部を形
成したことを特徴とする回路基板。1. A circuit board in which a conductive paste is supplied onto a substrate and then fired to form an electrode, wherein the electrode on the substrate is formed with a concave portion having a shape that matches the shape of the protruding electrode of the semiconductor element. Circuit board.
性接着剤層を設けたことを特徴とする請求項１記載の回
路基板。2. The circuit board according to claim 1, wherein a conductive adhesive layer is provided on the surface of the recess formed in the electrode on the board.
着剤層を設けたことを特徴とする請求項１記載の回路基
板。3. The circuit board according to claim 1, wherein an adhesive layer is provided on an upper surface of the recess formed in the electrode on the board.
成して電極を形成する回路基板において、基板上の電極
に半導体素子の突起電極の体積よりも小さい凹部を形成
したことを特徴とする回路基板。4. A circuit board wherein an electrode is formed by supplying a conductive paste on a substrate and then firing the same to form an electrode, wherein the electrode on the substrate is formed with a concave portion smaller than the volume of the projecting electrode of the semiconductor element. substrate.
成して電極を形成する回路基板において、基板上に供給
された導体ペーストを半導体の突起電極で押圧し、導体
ペーストの半導体素子が載置される位置に突起電極形状
と合致した形状の凹部を形成し、焼成することを特徴と
する回路基板電極の製造方法。5. A circuit board in which a conductive paste is supplied onto a substrate and then fired to form an electrode, wherein the conductive paste supplied on the substrate is pressed by a semiconductor bump electrode, and a semiconductor element of the conductive paste is mounted. A method of manufacturing a circuit board electrode, comprising: forming a concave portion having a shape matching the shape of a protruding electrode at a position to be formed;
成して電極を形成する回路基板において、基板上に供給
された導体ペーストを所望寸法の突起を有する金型で押
圧し、導体ペーストの半導体素子が載置される位置に所
望寸法の凹部を形成し、焼成することを特徴とする回路
基板電極の製造方法。6. A circuit board in which a conductive paste is supplied onto a substrate and then fired to form an electrode, the conductive paste supplied onto the substrate is pressed by a mold having projections of a desired size, and the conductive paste semiconductor is formed. A method for manufacturing a circuit board electrode, comprising: forming a recess having a desired size at a position where an element is to be mounted;
い凹部が形成された電極を有する回路基板への半導体素
子の実装方法において、前記回路基板の電極の凹部に半
導体素子を位置決め載置した後に、半導体素子の裏面よ
り加圧し、半導体素子の突起電極と回路基板の凹部を有
する電極とを互いに変形させることにより接合すること
を特徴とする半導体素子の実装方法。7. A method for mounting a semiconductor element on a circuit board having an electrode formed with a concave portion smaller than the volume of a protruding electrode of the semiconductor element, after positioning and mounting the semiconductor element in the concave portion of the electrode on the circuit board. A method of mounting a semiconductor device, comprising applying pressure from the back surface of a semiconductor device and deforming and joining a protruding electrode of the semiconductor device and an electrode having a concave portion of a circuit board to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9164760A JPH1117050A (en) | 1997-06-20 | 1997-06-20 | Circuit board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9164760A JPH1117050A (en) | 1997-06-20 | 1997-06-20 | Circuit board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1117050A true JPH1117050A (en) | 1999-01-22 |
Family
ID=15799415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9164760A Pending JPH1117050A (en) | 1997-06-20 | 1997-06-20 | Circuit board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1117050A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002222828A (en) * | 2001-01-29 | 2002-08-09 | Kyocera Corp | Substrate for packaging semiconductor element |
| JP2006165546A (en) * | 2004-12-03 | 2006-06-22 | General Electric Co <Ge> | Stacked electronic part for sensor |
| US7312533B2 (en) | 2000-03-31 | 2007-12-25 | Infineon Technologies Ag | Electronic component with flexible contacting pads and method for producing the electronic component |
| US7341894B2 (en) | 2002-03-29 | 2008-03-11 | Seiko Epson Corporation | Semiconductor, electrooptic apparatus and electronic apparatus |
| US7611040B2 (en) | 2005-05-24 | 2009-11-03 | Panasonic Corporation | Method for forming solder bump and method for mounting semiconductor device using a solder powder resin composition |
| JP2010092981A (en) * | 2008-10-06 | 2010-04-22 | Sharp Corp | Solar battery, backside contact solar battery, wiring substrate, and method of manufacturing solar battery |
| JP2018032007A (en) * | 2016-08-26 | 2018-03-01 | エルジー ディスプレイ カンパニー リミテッド | Display device |
| JP2021002563A (en) * | 2019-06-20 | 2021-01-07 | 株式会社デンソー | Sintered sheet, semiconductor device, manufacturing method of sintered sheet, and manufacturing method of semiconductor device |
-
1997
- 1997-06-20 JP JP9164760A patent/JPH1117050A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7312533B2 (en) | 2000-03-31 | 2007-12-25 | Infineon Technologies Ag | Electronic component with flexible contacting pads and method for producing the electronic component |
| JP2002222828A (en) * | 2001-01-29 | 2002-08-09 | Kyocera Corp | Substrate for packaging semiconductor element |
| JP4587573B2 (en) * | 2001-01-29 | 2010-11-24 | 京セラ株式会社 | Semiconductor element mounting body and manufacturing method of semiconductor element mounting body |
| US7341894B2 (en) | 2002-03-29 | 2008-03-11 | Seiko Epson Corporation | Semiconductor, electrooptic apparatus and electronic apparatus |
| JP2006165546A (en) * | 2004-12-03 | 2006-06-22 | General Electric Co <Ge> | Stacked electronic part for sensor |
| US7611040B2 (en) | 2005-05-24 | 2009-11-03 | Panasonic Corporation | Method for forming solder bump and method for mounting semiconductor device using a solder powder resin composition |
| JP2010092981A (en) * | 2008-10-06 | 2010-04-22 | Sharp Corp | Solar battery, backside contact solar battery, wiring substrate, and method of manufacturing solar battery |
| JP2018032007A (en) * | 2016-08-26 | 2018-03-01 | エルジー ディスプレイ カンパニー リミテッド | Display device |
| JP2021002563A (en) * | 2019-06-20 | 2021-01-07 | 株式会社デンソー | Sintered sheet, semiconductor device, manufacturing method of sintered sheet, and manufacturing method of semiconductor device |
| US11557563B2 (en) | 2019-06-20 | 2023-01-17 | Denso Corporation | Sinter sheet, semiconductor device and manufacturing method thereof |
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