JPS61113243A - Mounting process of hybrid integrated circuit - Google Patents
Mounting process of hybrid integrated circuitInfo
- Publication number
- JPS61113243A JPS61113243A JP23481484A JP23481484A JPS61113243A JP S61113243 A JPS61113243 A JP S61113243A JP 23481484 A JP23481484 A JP 23481484A JP 23481484 A JP23481484 A JP 23481484A JP S61113243 A JPS61113243 A JP S61113243A
- Authority
- JP
- Japan
- Prior art keywords
- silver paste
- integrated circuit
- pad
- flowed
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
し産業上の利用分野〕
本発明は、混成集積回路の実装方法に係り、特に、導電
性接着剤を用いて半導体チップを集積回路基板上に接着
せしめるダイボンディング方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for mounting a hybrid integrated circuit, and more particularly to a die bonding method for bonding a semiconductor chip onto an integrated circuit board using a conductive adhesive. .
［従来技術およびその問題点］
薄膜法あるいは厚膜法等によって形成された集積回路基
板上に半導体チップを接着せしめると共に電気的接続を
行うことによって得られる混成集積回路は、その回路設
計や製作技術において、はぼ完成に近いレベルに到達し
てきているといわれている。この分野でも、回路の集積
化が進むにつれて、半導体チップを接着するためのボン
ディングエリアの面積そのもの、基板上の回路パターン
とボンディングエリアとの間隔も小さくなる一方である
。[Prior art and its problems] A hybrid integrated circuit obtained by bonding a semiconductor chip onto an integrated circuit substrate formed by a thin film method or a thick film method and making electrical connections is difficult to obtain due to circuit design and manufacturing technology. It is said that the project has reached a near-perfect level. In this field as well, as the integration of circuits progresses, the area of the bonding area for bonding semiconductor chips as well as the distance between the circuit pattern on the substrate and the bonding area are becoming smaller and smaller.
従来、集積回路基板上に半導体チップを、接着するに際
しては、まず、該集積回路基板１０１上に形成された回
路パターン１０２のダイボンディングエリアＢＰに導電
性の銀ペースト１０３等の接着剤を必要量だけ塗布した
後、その上に正確に位置決めをしつつ半導体チップ１０
４を載置し、乾燥固定する方法がとられている。しかし
ながら、このとき、第２図に示す如くダイボンディング
エリアＢＰから銀ペースト１０３が流れ出し、近接する
回路パターン１０２等の導体パターン上に広がり、ショ
ートが多発するという問題があった。Conventionally, when bonding a semiconductor chip onto an integrated circuit board, first, a necessary amount of adhesive such as conductive silver paste 103 is applied to the die bonding area BP of the circuit pattern 102 formed on the integrated circuit board 101. After coating the semiconductor chip 10 while accurately positioning it on top of it,
4 is mounted and dried and fixed. However, at this time, as shown in FIG. 2, the silver paste 103 flows out from the die bonding area BP and spreads over adjacent conductor patterns such as the circuit pattern 102, resulting in frequent short circuits.
そして、この銀ペースト１０３は、乾燥硬化後は、基板
に対する接着強度が極めて強く、流出部分のみを除去す
るのが非常に困難であった。After drying and hardening, this silver paste 103 had extremely strong adhesion strength to the substrate, making it extremely difficult to remove only the spilled portion.
本発明は、前記実情に鑑みてなされたもので、ボンディ
ングエリアから流出する接着剤によるショートの発生を
防ぎ、信頼性の高い混成集積回路を提供することを目的
とする。The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to prevent the occurrence of short circuits due to the adhesive flowing out from the bonding area and to provide a highly reliable hybrid integrated circuit.
［問題点を解決するための手段］
そこで、本発明では、集積回路基板上のダイボンディン
グエリアに導電性接着剤を塗布し半導体チップを載置し
た後、該導電性接着剤の硬化に先立ち、該集積回路基板
全体を溶剤中に浸積し、流出した導電性接着剤を除去す
る工程付加している。[Means for Solving the Problems] Therefore, in the present invention, after applying a conductive adhesive to the die bonding area on the integrated circuit board and mounting the semiconductor chip, prior to curing of the conductive adhesive, There is an additional step of immersing the entire integrated circuit board in a solvent and removing the conductive adhesive that has flowed out.
［作用］
すなわち、半導体チップを載置し半硬化の状態で、流出
した（はみ出した）導電性接着剤は除去され、この後乾
燥硬化される。従って、余剰分の接着剤が硬化して、除
去困難となることはなくなった。[Function] That is, when the semiconductor chip is placed and in a semi-cured state, the conductive adhesive that has flowed out (protruded) is removed, and then dried and cured. Therefore, the excess adhesive no longer hardens and becomes difficult to remove.
［実施例］
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
まず、厚さ約１．５ｍｍの絶縁性のセラミック基板上に
、通常の厚膜法により、第１図（ａ）に示す如く、ダイ
ボンディングパッドＢＰを含む回路パターン２を形成す
る。First, as shown in FIG. 1(a), a circuit pattern 2 including die bonding pads BP is formed on an insulating ceramic substrate with a thickness of about 1.5 mm by a normal thick film method.
次いで、第１図（ｂ）に示す如く該ダイボンディングパ
ッドＢＰ上に、導電性の銀ペースト３を塗布する。Next, as shown in FIG. 1(b), a conductive silver paste 3 is applied onto the die bonding pad BP.
続いて、第１図（Ｃ）および（ｄ）に示す如く、銀ペー
スト３の塗布されたダイボンディングパッドＢＰ上に、
所望の機能素子を構成する半導体集積回路チップ（以下
ＩＣチップ）４をボンディングする。ボンディングに際
しては、オートダイボンディング装置等を用いて正確に
位置を決めて、ダイボンディングパッドＢＰ上に正しく
固定するようにする。このとき、銀ペースト３がダイボ
ンディングパッドＢＰから流出して隣接する回路パター
ン２にまで達している。Subsequently, as shown in FIGS. 1(C) and (d), on the die bonding pad BP coated with the silver paste 3,
A semiconductor integrated circuit chip (hereinafter referred to as an IC chip) 4 constituting a desired functional element is bonded. During bonding, an automatic die bonding device or the like is used to accurately determine the position and to properly fix the die bonding pad BP. At this time, the silver paste 3 flows out from the die bonding pad BP and reaches the adjacent circuit pattern 2.
この後、１００°Ｃで２０分間、銀ペースト３が半硬化
の状態となるまで、加熱乾燥する。Thereafter, it is heated and dried at 100° C. for 20 minutes until the silver paste 3 becomes semi-hardened.
そして、該基板１をイソプロピルアルコール（ＩＰＡ）
中に浸漬し、超音波洗浄を行ない、第１図くｅ）に示す
如く、ダイボンディングパッドＢＰから流出した余剰分
の銀ペーストを除去する。Then, the substrate 1 is coated with isopropyl alcohol (IPA).
The die bonding pad BP is immersed in the die bonding pad BP and subjected to ultrasonic cleaning to remove the excess silver paste that has flowed out from the die bonding pad BP, as shown in FIG. 1(e).
この後、１８０６Ｃで加熱乾燥し、銀ペーストを完全に
加熱硬化させる。Thereafter, the silver paste is heated and dried at 1806C to completely cure the silver paste.
最後に、このＩＣチップと、回路パタ−ンとの門で必要
に応じてワイヤボンディング法等により電気的接続を行
ない、混成集積回路が完成する。Finally, electrical connections are made between the IC chip and the circuit pattern by wire bonding or the like, if necessary, to complete the hybrid integrated circuit.
このようにして形成された混成集積回路は、流出した銀
ペーストも完全に除去されており、ショートの発生もな
く、極めて信頼性の高いものとなっている。このとき、
超音波洗浄工程において、余剰分の銀ペーストの除去と
同時に、ｔＣチップの下部にある銀ペーストも外側から
れずかに浸触されるが、完全に固着した後は、接着強度
についても問題はなかった。The hybrid integrated circuit thus formed has extremely high reliability, with the spilled silver paste completely removed and no short circuits occurring. At this time,
During the ultrasonic cleaning process, when the excess silver paste is removed, the silver paste at the bottom of the tC chip is also slightly penetrated from the outside, but once it is completely fixed, there is no problem with the adhesive strength. Ta.
なお、実施例においては、流出した導電性ベーストの除
去に、イソプロピルアルコールを用いたが、必ずしも、
これに限定されるものではなく、接着剤として使用する
物質に応じて、該物質に対して溶剤となるような有機溶
剤を適宜選択すればよい。In addition, in the examples, isopropyl alcohol was used to remove the conductive base that leaked out.
The adhesive is not limited thereto, and depending on the substance used as the adhesive, an organic solvent that acts as a solvent for the substance may be appropriately selected.
［発明の効果］
以上、説明してきたように、本発明の混成集積回路の製
造方法によれば、ダイボンディングに際し、半導体チッ
プを載置した後、ポンディングパッドから流出した接着
剤を硬化に先立ち除去する工程を含んでいるため、ショ
ートの発生もなく、信頼性の高い混成集積回路を得るこ
とが可能となる。[Effects of the Invention] As described above, according to the method for manufacturing a hybrid integrated circuit of the present invention, during die bonding, after mounting a semiconductor chip, the adhesive flowing out from the bonding pad is removed before curing. Since the removing step is included, it is possible to obtain a highly reliable hybrid integrated circuit without the occurrence of short circuits.
【図面の簡単な説明】
第１図（ａ）乃至第１図（ｅ）は、本発明実施例の混成
集積回路の製造工程を示す図、第２図は、従来の方法に
よって形成された混成集積回路を示す斜視図である。
１０１・・・基板、１０２・・・回路パターン、ＢＰ・
・・ポンディングパッド、１０３・・・接着剤、１０４
・・・半導体チップ、１・・・セラミック基板、２・・
・回路パターン、３・・・銀ペースト（接着剤）、４・
・・ＴＣチップ。[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to 1(e) are diagrams showing the manufacturing process of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. FIG. 1 is a perspective view showing an integrated circuit. 101... Board, 102... Circuit pattern, BP・
...Ponding pad, 103...Adhesive, 104
...Semiconductor chip, 1...Ceramic substrate, 2...
・Circuit pattern, 3...Silver paste (adhesive), 4.
...TC chip.
Claims (1)
プを接着せしめるに際し、該集積回路パターン上のダイ
ボンディングパッドに導電性の接着剤を塗布し所定の半
導体チップを載置した後、該接着剤の硬化に先立ち、ダ
イボンディングパッドから流出した余剰分の接着剤を除
去する工程を含むことを特徴とする混成集積回路の実装
方法。When bonding a semiconductor chip onto an integrated circuit pattern formed on a substrate, a conductive adhesive is applied to the die bonding pad on the integrated circuit pattern, a predetermined semiconductor chip is mounted, and then the adhesive is applied. A method for mounting a hybrid integrated circuit, the method comprising the step of removing excess adhesive flowing out from a die bonding pad prior to curing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23481484A JPS61113243A (en) | 1984-11-07 | 1984-11-07 | Mounting process of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23481484A JPS61113243A (en) | 1984-11-07 | 1984-11-07 | Mounting process of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61113243A true JPS61113243A (en) | 1986-05-31 |
Family
ID=16976804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23481484A Pending JPS61113243A (en) | 1984-11-07 | 1984-11-07 | Mounting process of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61113243A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5730310A (en) * | 1993-10-01 | 1998-03-24 | Yoshihara; Hiroshi | Lid opening mechanism system |
| JP2010186864A (en) * | 2009-02-12 | 2010-08-26 | Shin-Etsu Chemical Co Ltd | Method of manufacturing solar cell, and solar cell |
| JP2013214546A (en) * | 2012-03-30 | 2013-10-17 | Fujitsu Ten Ltd | Semiconductor device and semiconductor device manufacturing method |
| WO2016157394A1 (en) * | 2015-03-30 | 2016-10-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing same |
-
1984
- 1984-11-07 JP JP23481484A patent/JPS61113243A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5730310A (en) * | 1993-10-01 | 1998-03-24 | Yoshihara; Hiroshi | Lid opening mechanism system |
| JP2010186864A (en) * | 2009-02-12 | 2010-08-26 | Shin-Etsu Chemical Co Ltd | Method of manufacturing solar cell, and solar cell |
| JP2013214546A (en) * | 2012-03-30 | 2013-10-17 | Fujitsu Ten Ltd | Semiconductor device and semiconductor device manufacturing method |
| WO2016157394A1 (en) * | 2015-03-30 | 2016-10-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing same |
| JPWO2016157394A1 (en) * | 2015-03-30 | 2017-06-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US10037932B2 (en) | 2015-03-30 | 2018-07-31 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US10347567B2 (en) | 2015-03-30 | 2019-07-09 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
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