JPH0363813B2 - - Google Patents

Info

Publication number
JPH0363813B2
JPH0363813B2 JP59200109A JP20010984A JPH0363813B2 JP H0363813 B2 JPH0363813 B2 JP H0363813B2 JP 59200109 A JP59200109 A JP 59200109A JP 20010984 A JP20010984 A JP 20010984A JP H0363813 B2 JPH0363813 B2 JP H0363813B2
Authority
JP
Japan
Prior art keywords
chip
wiring pattern
substrate
coating film
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59200109A
Other languages
Japanese (ja)
Other versions
JPS6178132A (en
Inventor
Takeshi Myagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59200109A priority Critical patent/JPS6178132A/en
Publication of JPS6178132A publication Critical patent/JPS6178132A/en
Publication of JPH0363813B2 publication Critical patent/JPH0363813B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24997—Flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/82051—Forming additional members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はICチツプを基板上に搭載し基板上
の配線パターンと接続してなる集積回路装置に係
り、特にICチツプ上の入出力パツドと基板上の
配線パターンとを接続する手段に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an integrated circuit device in which an IC chip is mounted on a substrate and connected to a wiring pattern on the substrate, and particularly relates to an integrated circuit device in which an IC chip is mounted on a substrate and connected to a wiring pattern on the substrate. The present invention relates to a means for connecting the above wiring pattern.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

ICチツプを基板上に実装する場合、ICチツプ
上の入出力パツドと基板上の配線パターンとの接
続には一般にワイヤボンデイング法が使用されて
いる。しかしながらICチツプ内部の集積度が高
まるにつれて、入出力パツドの数も多くなるの
で、ワイヤボンデイング法ではワイヤどうしの接
触という問題が生じてくる。実際、ICチツプ上
の入出力パツドの間隔が100μｍ程度までが、ワ
イヤボンデイング法を適用できる限界とされてい
る。また、今後実用化が進むと見られるGaAs化
合物半導体等を用いた超高速ICになると、ワイ
ヤボンデイング法ではワイヤの特性インピーダン
スと半導体配線および基板配線の特性インピーダ
ンスとの不整合が、高速動作に悪影響を及ぼすこ
とが予想される。 When mounting an IC chip on a board, wire bonding is generally used to connect the input/output pads on the IC chip and the wiring patterns on the board. However, as the degree of integration inside an IC chip increases, the number of input/output pads also increases, so the wire bonding method poses the problem of contact between wires. In fact, it is said that the limit to which the wire bonding method can be applied is when the distance between input and output pads on an IC chip is about 100 μm. In addition, when it comes to ultra-high-speed ICs using GaAs compound semiconductors, which are expected to be put into practical use in the future, the wire bonding method has a negative effect on high-speed operation due to the mismatch between the characteristic impedance of the wire and the characteristic impedance of the semiconductor wiring and substrate wiring. It is expected that

一方、ワイヤを使用せずにICチツプ上の入出
力パツドと基板上の配線パターンとを接続する方
法として、例えばフリツプチツプ法が知られてい
るが、フリツプチツプ法はICチツプの入出力パ
ツド上に金属バンプと呼ばれる特殊な金属端子を
設ける必要があり、ICチツプの集積度が高くな
り入出力パツドのピツチが高密度になると、この
金属バンプ形成工程が技術的に極めて難しく、高
価格化の原因ともなる。 On the other hand, the flip-chip method, for example, is known as a method for connecting the input/output pads on an IC chip and the wiring pattern on the board without using wires. It is necessary to provide special metal terminals called bumps, and as IC chips become more integrated and the pitch of input/output pads becomes denser, the process of forming metal bumps becomes technically extremely difficult and is a cause of high prices. Become.

〔発明の目的〕[Purpose of the invention]

この発明の目的は、ワイヤを使用せず、また
ICチツプ上の入出力パツドに特殊な工程を施す
ことなく、ICチツプ上の入出力パツドと基板上
の配線パターンとが接続された集積回路装置を提
供することにある。 The purpose of this invention is to avoid using wires and
To provide an integrated circuit device in which input/output pads on an IC chip and wiring patterns on a substrate are connected without applying any special process to the input/output pads on the IC chip.

〔発明の概要〕[Summary of the invention]

この発明に係る集積回路装置は、ICチツプの
少なくとも側面部に絶縁性材料をコーテイング
し、該コーテイング膜上にICチツプ上の入出力
パツドと基板上の配線パターンとを接続するため
の配線パターンを形成したことを特徴とする。 An integrated circuit device according to the present invention includes coating an insulating material on at least a side surface of an IC chip, and forming a wiring pattern on the coating film for connecting an input/output pad on the IC chip and a wiring pattern on a substrate. It is characterized by the fact that it has been formed.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、ICチツプの側面上に設け
たコーテイング膜上に形成された配線パターンに
よつてICチツプ上の入出力パツドと基板上の配
線パターンとを接続するため、ワイヤボンデイン
グ法におけるような問題がなく、集積度の極めて
高いICチツプについても容易に基板上に実装す
ることができる。また、コーテイング膜上の配線
パターン形成部分に溝を形成する等により、この
配線パターンの配線抵抗を容易に低減させること
ができ、超高速ICチツプを実装する場合、安定
な高速動作を得ることが可能である。 According to this invention, since the input/output pads on the IC chip and the wiring pattern on the substrate are connected by the wiring pattern formed on the coating film provided on the side surface of the IC chip, it is similar to the wire bonding method. There are no major problems, and even highly integrated IC chips can be easily mounted on the board. In addition, by forming grooves in the wiring pattern forming area on the coating film, the wiring resistance of this wiring pattern can be easily reduced, which makes it possible to obtain stable high-speed operation when mounting ultra-high-speed IC chips. It is possible.

さらに、この発明ではワイヤを使用しない従来
のボンデイング法、例えばフリツプチツプ法等の
ようにICチツプ自体が特殊な端子を有するもの
である必要はなく、しかも入出力パツドが高密度
になつても容易にその配線を行なうことができる
という利点を有する。 Furthermore, with this invention, unlike conventional bonding methods that do not use wires, such as the flip-chip method, it is not necessary for the IC chip itself to have special terminals, and moreover, it is not necessary for the IC chip itself to have special terminals. It has the advantage that the wiring can be done.

〔発明の実施例〕[Embodiments of the invention]

第１図はこの発明の一実施例に係る集積回路装
置の斜視図であり、基板１上にICチツプ２が実
装された状態を示している。 FIG. 1 is a perspective view of an integrated circuit device according to an embodiment of the present invention, showing a state in which an IC chip 2 is mounted on a substrate 1.

第１図において、ICチツプ２は上面に入出力
パツド３を有する。ICチツプ２の側面部には絶
縁性材料、好ましくはポリイミド等の高分子材料
からなるコーテイング膜４が被着形成されてい
る。このコーテイング膜４は、この例では入出力
パツド３に対応した位置に基板１上に垂直に伸び
た溝５を有する。そして、コーテイング膜４の溝
５内に例えばCu、Au等の金属からなる配線パタ
ーン６が形成され、これらの配線パターン６によ
りICチツプ２上の入出力パツド３と基板１上の
配線パターン７とが接続されている。基板１上の
配線パターン７はコーテイング膜４上の配線パタ
ーン６と同様の材料でよい。なお、コーテイング
膜４上の配線パターン５と、ICチツプ２上の入
出力パツド３および基板１上の配線パターン７と
の接続は、導体ペースト（低融点半田でもよい）
８，９によつて行なわれる。基板１上へのICチ
ツプ２の機械的に保持は、通常行なわれているダ
イボンデイング等の方法で行なえばよい。 In FIG. 1, an IC chip 2 has an input/output pad 3 on its top surface. A coating film 4 made of an insulating material, preferably a polymeric material such as polyimide, is formed on the side surface of the IC chip 2. This coating film 4 has a groove 5 extending vertically on the substrate 1 at a position corresponding to the input/output pad 3 in this example. Then, wiring patterns 6 made of metal such as Cu or Au are formed in the grooves 5 of the coating film 4, and these wiring patterns 6 connect the input/output pads 3 on the IC chip 2 and the wiring patterns 7 on the substrate 1. is connected. The wiring pattern 7 on the substrate 1 may be made of the same material as the wiring pattern 6 on the coating film 4. Note that the connection between the wiring pattern 5 on the coating film 4, the input/output pad 3 on the IC chip 2, and the wiring pattern 7 on the substrate 1 is made using conductive paste (low melting point solder may also be used).
8 and 9. The IC chip 2 may be mechanically held onto the substrate 1 by a commonly used method such as die bonding.

ICチツプ２の側面上のコーテイング膜４は、
例えば第２図に示すような方法によつて形成する
ことができる。すなわち、コーテイング膜４に形
成すべき溝５に対応した突条１１を内面に有する
枠状の治具（型）１０の内側にICチツプ２をセ
ツトし、治具１０の内外両面を貫通した注入口１
２よりゲル状となつたポリイミド等の高分子材料
１３を注入し、注入後、加熱して硬化させる。そ
して高分子材料１３の硬化後、治具１０を取外せ
ば高分子材料からなるコーテイング膜４が側面に
形成された、第１図中に示したようなICチツプ
２が得られる。 The coating film 4 on the side surface of the IC chip 2 is
For example, it can be formed by a method as shown in FIG. That is, the IC chip 2 is set inside a frame-shaped jig (mold) 10 that has protrusions 11 on the inner surface that correspond to the grooves 5 to be formed in the coating film 4, and the IC chip 2 is placed inside a frame-shaped jig (mold) 10 that penetrates both the inner and outer surfaces of the jig 10. Entrance 1
Polymer material 13 such as polyimide which has become gel-like from 2 is injected, and after the injection, it is heated and hardened. After the polymer material 13 is cured, the jig 10 is removed to obtain the IC chip 2 as shown in FIG. 1, with the coating film 4 made of the polymer material formed on the side surface.

こうしてICチツプ２の側面上に形成されたコ
ーテイング膜４上に、例えば蒸着その他の薄膜技
術によりCr、Ti等を接着層としてCu、Au等を被
着形成し、さらにドライエツチング等によりパタ
ーニングして配線パターン６を形成した後、基板
１上に搭載し、配線パターン６と入出力パツド３
および基板１上の配線パターン７とを導体ペース
ト８，９により電気的に接続することで、第１図
に示した集積回路装置が得られる。 On the coating film 4 thus formed on the side surface of the IC chip 2, Cu, Au, etc. are deposited using Cr, Ti, etc. as an adhesive layer by vapor deposition or other thin film techniques, and then patterned by dry etching or the like. After forming the wiring pattern 6, it is mounted on the board 1, and the wiring pattern 6 and the input/output pad 3 are connected to each other.
By electrically connecting the wiring pattern 7 on the substrate 1 with conductive pastes 8 and 9, the integrated circuit device shown in FIG. 1 is obtained.

以上のように構成されたこの発明に基く集積回
路装置においては、ICチツプ２が入出力パツド
３が例えば10μｍ程度のピツチで配列形成された
ような非常に集積度の高いものである場合でも、
コーテイング膜４上に形成された配線パターン６
によつて入出力パツド３と基板１上の配線パター
ン７とを短絡、接続不良等を起こすことなく確実
に接続することができる。また、上記実施例では
コーテイング膜４上の配線パターン６が溝５内に
形成されているため、その配線抵抗をワイヤボン
デイング等の場合に比べ大幅に下げることがで
き、また溝５の深さおよび配線パターン６の厚さ
等を調整することにより特性インピーダンスの整
合を得ることができる。従つてICチツプ２が例
えばGaAs化合物半導体を用いた超高速論理ICの
ようなものである場合でも、その高速動作を十分
に保障することが可能である。 In the integrated circuit device according to the present invention constructed as described above, even if the IC chip 2 has a very high degree of integration, with input/output pads 3 arranged at a pitch of, for example, about 10 μm,
Wiring pattern 6 formed on coating film 4
This allows the input/output pad 3 and the wiring pattern 7 on the substrate 1 to be reliably connected without causing short circuits, connection failures, etc. Further, in the above embodiment, since the wiring pattern 6 on the coating film 4 is formed within the groove 5, the wiring resistance can be significantly lowered compared to the case of wire bonding, etc., and the depth of the groove 5 and By adjusting the thickness of the wiring pattern 6, etc., characteristic impedance matching can be obtained. Therefore, even if the IC chip 2 is, for example, an ultrahigh-speed logic IC using a GaAs compound semiconductor, its high-speed operation can be sufficiently guaranteed.

なお、この発明は上記実施例に限定されるもの
ではなく、例えば上記実施例ではコーテイング膜
をICチツプの側面にのみ形成したが、上面にも
形成してもよい。その場合、基板上のICチツプ
のさらに上に別のICチツプを載せた２階建て構
造とし、その上側のICチツプの入出力パツドを
下側のICチツプ上面と側面上に形成した配線パ
ターンを介して基板上の配線パターンと接続する
ことができる。勿論、さらに多層階構造にするこ
とも可能である。 It should be noted that the present invention is not limited to the above embodiments; for example, in the above embodiments, the coating film was formed only on the side surfaces of the IC chip, but it may also be formed on the top surface. In that case, a two-story structure is used in which another IC chip is mounted on top of the IC chip on the board, and a wiring pattern is formed in which the input/output pads of the upper IC chip are formed on the top and side surfaces of the lower IC chip. It can be connected to the wiring pattern on the board through the wire. Of course, it is also possible to have a multilayer structure.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例に係る集積回路装
置の構成を示す斜視図、第２図は同実施例装置に
おけるICチツプ側面上のコーテイング膜の形成
工程を示す図である。 １……基板、２……ICチツプ、３……入出力
パツド、４……コーテイング膜、５……溝、６…
…コーテイング膜上の配線パターン、７……基板
上の配線パターン、８，９……導体ペースト、１
０……コーテイング用治具、１１……突条、１２
……注入口、１３……高分子材料。 FIG. 1 is a perspective view showing the structure of an integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a process of forming a coating film on the side surface of an IC chip in the same embodiment. 1...Substrate, 2...IC chip, 3...I/O pad, 4...Coating film, 5...Groove, 6...
...Wiring pattern on coating film, 7... Wiring pattern on substrate, 8, 9... Conductor paste, 1
0...Coating jig, 11...Protrusion, 12
... Inlet, 13 ... Polymer material.

Claims (1)

【特許請求の範囲】 １ ICチツプを基板上に搭載し、ICチツプ上の
入出力パツドと基板上の配線パターンと接続して
なる集積回路装置において、前記ICチツプの少
なくとも側面部に絶縁性材料をコーテイングし、
該コーテイング膜上に前記ICチツプ上の入出力
パツドと前記基板上の配線パターンとを接続する
ための配線パターンを形成したことを特徴とする
集積回路装置。 ２ コーテイング膜は溝を有し、この溝内にIC
チツプ上の入出力パツドと基板上の配線パターン
とを接続するための配線パターンを形成したこと
を特徴とする特許請求の範囲第１項記載の集積回
路装置。[Claims] 1. An integrated circuit device in which an IC chip is mounted on a substrate and input/output pads on the IC chip are connected to wiring patterns on the substrate, wherein at least a side surface of the IC chip is provided with an insulating material. coated with
An integrated circuit device characterized in that a wiring pattern for connecting input/output pads on the IC chip and wiring patterns on the substrate is formed on the coating film. 2 The coating film has a groove, and an IC is placed in this groove.
2. The integrated circuit device according to claim 1, further comprising a wiring pattern for connecting input/output pads on the chip and wiring patterns on the substrate.
JP59200109A 1984-09-25 1984-09-25 Integrated circuit device Granted JPS6178132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59200109A JPS6178132A (en) 1984-09-25 1984-09-25 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59200109A JPS6178132A (en) 1984-09-25 1984-09-25 Integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6178132A JPS6178132A (en) 1986-04-21
JPH0363813B2 true JPH0363813B2 (en) 1991-10-02

Family

ID=16418975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59200109A Granted JPS6178132A (en) 1984-09-25 1984-09-25 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6178132A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100784388B1 (en) * 2006-11-14 2007-12-11 삼성전자주식회사 Semiconductor package and method for manufacturing the same
US7843046B2 (en) * 2008-02-19 2010-11-30 Vertical Circuits, Inc. Flat leadless packages and stacked leadless package assemblies
US9082438B2 (en) 2008-12-02 2015-07-14 Panasonic Corporation Three-dimensional structure for wiring formation
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
CN103441117A (en) 2009-01-27 2013-12-11 松下电器产业株式会社 Semiconductor device, three-dimensional structure with wiring on the surface, memory card and magnetic head module

Also Published As

Publication number Publication date
JPS6178132A (en) 1986-04-21

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