JPH09232506A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the mounting of LSIs one above the other or on an interconnection board, without damaging semiconductor elements. SOLUTION: A first and second semiconductor chips 1 and 2 are adhered mutually surface to surface through an insulative region 5 and the area occupied by electrodes 3a formed on element regions 6 of both chips is less than that occupied by electrodes 3b formed on other than regions 6. This makes the height of bump electrodes 4a formed on the electrodes 3a of the regions 6 less than that of bump electrodes 4b formed on the electrodes 3b on other regions, resulting in such a structure that at bonding of the electrodes 4a, 4b, the stress is concentrated on the electrodes 4b on other reactors while no stress is concentrated on the electrodes 4a on the regions 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-performance LSI used in electronic equipment and its mounting technology, and more particularly to a semiconductor device connected by using a protruding electrode formed on an electrode of a semiconductor element and a manufacturing method thereof. is there.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become more sophisticated, LSIs are often used, and in order to reduce the size, it is often the case that many chips are integrated into one chip. However, as the circuit scale becomes larger,
There are problems that the development period of the LSI is extended and the cost is increased due to the increase of the chip size.

As one of the solutions, the electrodes provided on the outer peripheral portion of the semiconductor chip are arranged also on the element region,
Either one of these two methods, which has a technique of reducing the cost by reducing the chip area and a technique of stacking different chips, may be used. Cost reduction is achieved.

However, when the electrode on the semiconductor chip is formed on the element region, any one of the wiring, the contact, and the transistor exists under the electrode, and when the protruding electrode is used for bonding, mechanical contact is required. Since various stresses are applied to break the element or change the characteristics and affect the reliability of the semiconductor chip, it is necessary to make electrical connection under a pressure that does not damage the element.

Further, the bump electrodes usually provided on the electrodes of the semiconductor chip for stacking different chips may be electrolytic plating method, vapor deposition method, or thermal transfer method of bump electrodes formed on another substrate. However, any of these methods requires many complicated processes, which leads to an increase in cost and an increase in the cost of lamination. Therefore, in order to solve this problem, a technique for forming a protruding electrode on the electrode by an electroless plating method is being developed. This technique typically uses Ni electroless plating. In this method, first, light etching is performed using sodium hydroxide or phosphoric acid in order to remove the oxide film on Al.
Next, the surface is replaced with Zn for the purpose of preventing re-oxidation on the Al electrode. After this, electroless Ni plating is performed to deposit to a predetermined height to complete the protruding electrode. Substitution Au plating is often performed after Ni plating for the purpose of preventing oxidation of the Ni surface.

According to this method, the protruding electrode can be formed on the Al electrode of the semiconductor chip only by immersing it in the electroless plating solution, so that the cost can be reduced.

[0007]

However, when the electroless plating method of Ni is carried out, height variations occur depending on the area of the electrodes, the surface condition, the electrical condition, and the condition of the plating solution, and the height of the electrodes during the bonding is increased. Stress concentration occurs on the high bump electrode. This stress concentration is particularly remarkable in the case of a material such as Ni that is difficult to deform, and damages the element under the electrode. It has been necessary to form a conductive material that absorbs and spreads the height variation of the protruding electrodes by spreading by wetting due to the diffusion of hardness material or solder.

However, even when a material that absorbs such height variations is formed, if the Ni protruding electrodes are directly contacted and connected to the opposing protruding electrodes, stress is easily applied by the external force after the bonding or after the bonding. There is a problem that concentration occurs and the element is damaged. This problem is the same not only in Ni but also in conductive materials such as Cu and Au.

Therefore, in view of the above problems, an object of the present invention is to provide a semiconductor device which can be mounted on LSIs or on a wiring board without damaging the semiconductor element and a manufacturing method thereof. is there.

[0010]

According to another aspect of the present invention, there is provided a semiconductor device, wherein the surfaces of a first semiconductor chip and a second semiconductor chip are adhered to each other via an insulating resin, and the surface of the first semiconductor chip is affixed to each other. The protruding electrode formed on the upper electrode is electrically connected to the protruding electrode formed on the surface of the second semiconductor chip and corresponding to the electrode of the first semiconductor chip. First semiconductor device,
The area of the electrodes formed on the element regions of the semiconductor chip and the second semiconductor chip is smaller than the area of the electrodes formed on other than the element region.

As described above, the area of the electrodes formed on the element regions of the first semiconductor chip and the second semiconductor chip is made smaller than the area of the electrodes formed other than on the element region, and thus on the element region. The height of the bump electrodes formed on the electrodes of the electrodes is lower than the height of the bump electrodes formed on the electrodes other than the element region, and therefore, when the bump electrodes are joined, stress is applied to the bump electrodes other than the element region. Concentration occurs, and the stress is not concentrated on the protruding electrodes on the element region. Therefore, when mounting an LSI in which electrodes are formed on the element region, the element can be mounted without damaging the element, and thus mounting on a highly reliable laminated LSI or wiring board can be realized.

According to another aspect of the semiconductor device of the present invention, the surfaces of the first semiconductor chip and the second semiconductor chip are adhered to each other via an insulating resin, and the electrodes are located on the surface of the first semiconductor chip. A semiconductor device in which the protruding electrode formed on the second semiconductor chip and the protruding electrode formed on the surface of the second semiconductor chip and corresponding to the electrode of the first semiconductor chip are electrically connected to each other. An electrode formed on the element regions of the first semiconductor chip and the second semiconductor chip is divided into at least two or more regions by an insulating film, and the divided regions are formed on regions other than the element region. It is characterized by having a smaller area.

Thus, the electrodes formed on the element regions of the first semiconductor chip and the second semiconductor chip are divided into at least two or more parts by the insulating film, and the divided regions are formed on the element regions. Since it is smaller than the area of the electrodes formed in other areas, the height of the protruding electrodes formed on the electrodes on the element area is lower than the height of the protruding electrodes formed on electrodes other than the element area. Therefore, at the time of joining the projecting electrodes, stress concentration occurs on the projecting electrodes other than on the element region, and stress concentration does not occur on the projecting electrodes on the element region, and the same effect as in claim 1 can be obtained.

A third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by electroless plating. Thus, since at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by the electroless plating method, the protruding electrodes can be formed simply by immersing the semiconductor chip in the electroless plating solution. It can be manufactured at low cost. Further, as described in claims 1 and 2, since the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than the element region, There is no damage to the element due to height variations of the protruding electrodes due to the state of the electrodes and the plating solution.

A semiconductor device according to a fourth aspect is the semiconductor device according to the first or second aspect, wherein at least one of the first semiconductor chip and the second semiconductor chip is a wiring board. Thus, since at least one of the first semiconductor chip and the second semiconductor chip is the wiring board, mounting on the wiring board can be realized. According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by an electroless plating method, and an electroless plating is formed on an upper portion thereof. A conductive material layer having a hardness lower than that of the bump electrode formed by the method is formed.

As described above, since the conductive material layer having a hardness lower than that of the bump electrode is formed on the bump electrode formed by the electroless plating method, the element can be bonded with a load that does not damage the element. . That is, when the conductive material layer is plastically deformed during connection within a load that does not damage the element, variations in height of the protruding electrodes and warpage of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is The pressure is smaller than the pressure applied to the electrodes other than the above and does not damage the device.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, the conductive material layer is In or In containing Sn, Pb,
It is made of a metal containing at least one of Bi, Ag and Zn. Thus, the conductive material layer I
By using a metal containing at least one of Sn, Pb, Bi, Ag, and Zn for n or In, the conductive material layer is plastically deformed within a load that does not damage the element at the time of connection, and the height of the protruding electrode is increased. It is possible to absorb variations in thickness and warp of the semiconductor chip.

According to a seventh aspect of the present invention, in the fifth aspect, the conductive material layer is a conductive paste made of resin and metal. As described above, by using the conductive material layer as the conductive paste made of resin and metal, the conductive material layer is plastically deformed within a load that does not damage the element at the time of connection, and the height variation of the protruding electrode or the semiconductor chip It can absorb the warp it has.

According to another aspect of the semiconductor device manufacturing method of the present invention, electrodes are provided at corresponding positions on the surfaces of the first semiconductor chip and the second semiconductor chip so that the area on the element region is smaller than the area on the element region. Forming a protruding electrode on the electrodes of the first semiconductor chip and the second semiconductor chip by electroless plating, and insulating on the surface of the first semiconductor chip or the second semiconductor chip. Of applying a conductive resin, the first semiconductor chip and the second semiconductor chip
Of aligning the protruding electrodes of the semiconductor chip, and pressing the back surface of the first semiconductor chip or the second semiconductor chip to cure the insulating resin so that the first semiconductor chip and the second semiconductor chip And the step of electrically connecting the electrodes.

As described above, the electrodes are formed at the corresponding positions on the surfaces of the first semiconductor chip and the second semiconductor chip so that the area of the element region is smaller than that of the area other than the element region. The height of the protruding electrode formed on the upper electrode is lower than that of the protruding electrode formed on the electrodes other than the element region. Therefore, when pressure is applied to the back surface of the first semiconductor chip or the second semiconductor chip to join the protruding electrodes, stress concentration occurs on the protruding electrodes other than on the element region, and stress concentration on the protruding electrodes on the element region. The structure does not occur. Further, since the protruding electrodes are formed by the electroless plating treatment, the protruding electrodes can be formed only by immersing the semiconductor chip in the electroless plating solution, and the manufacturing cost can be reduced.

A method of manufacturing a semiconductor device according to a ninth aspect is
In the eighth aspect, the pressure applied to the electrode on the element region in the step of electrically connecting the electrodes of the first semiconductor chip and the second semiconductor chip is 0.02 g / μm ² or less. As described above, the pressure applied to the electrode on the element region is 0.02 g / μm ² or less, so that the element is not damaged.

According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the metal forming the conductive material layer is formed in the step of forming the protruding electrodes on the electrodes of the first semiconductor chip and the second semiconductor chip. By dipping at least one of the first semiconductor chip and the second semiconductor chip in the melt, a conductive material layer having a hardness lower than that of the protruding electrode is formed on the protruding electrode.

As described above, by immersing at least one of the first semiconductor chip and the second semiconductor chip in the melt of the metal forming the conductive material layer, the hardness above the protruding electrode is higher than that of the protruding electrode. Since the low conductive material layer is formed, the elements can be bonded with a load that does not damage the element. That is, when the conductive material layer is plastically deformed within a load that does not damage the element during connection,
The height variations of the protruding electrodes and the warp of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is smaller than the pressure applied to the electrodes other than on the element region, so that the elements are not damaged. Since the conductive material layer was formed by immersing in the melt of the conductive material as described above,
It is cost effective.

[0024]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. In FIG. 1, 1 and 2 are first and second semiconductor chips, 3a and 3b are Al electrodes, 4a and 4b are protruding electrodes, 5 is an insulating resin, 6 is an element region, 7 is a protective film,
Reference numeral 8 is a conductive material layer. Further, 3a and 4a are element regions 6
3b and 4b are Al electrodes formed on the upper surface and corresponding protruding electrodes, and 3b and 4b are Al formed on areas other than the element region 6.
An electrode and a corresponding bump electrode.

The area of the Al electrode 3a formed on the element region 6 is smaller than the area of the Al electrode 3b formed on other than the element region 6. In this case, the protective film 7 that covers the surfaces of the first and second semiconductor chips 1 and 2
The exposed areas of the Al electrodes 3a and 3b are different. Protrusion electrodes 4a and 4b are formed on these Al electrodes 3a and 3b by electroless plating. Since the Al electrodes 3a and 3b have different areas as described above, the protruding electrode 4a formed on the Al electrode 3a on the element region 6 is the protruding electrode formed on the Al electrode 3b other than on the element region 6. Four
Height is lower than b. In addition, the first semiconductor chip 1 and the second semiconductor chip 2 are attached to each other with the insulating resin 5 interposed therebetween, and the Al electrodes 3 at opposite positions are attached to each other.
a and 3b are electrically connected via the protruding electrodes 4a and 4b.

Next, a method of manufacturing this semiconductor device will be described. The protruding electrodes 4a and 4b are formed on the Al electrodes 3a and 3b by electroless Ni plating. In this case, the Al electrodes 3a and 3b on the semiconductor chips 1 and 2 are formed by the sputtering method, the thickness is 1 μm, and the material is Al-1% S.
i-0.5% Cu was used. For example, the size of the Al electrode 3a is 15 μm square and the size of the Al electrode 3b is 100 μm square. The size of each of the semiconductor chips 1 and 2 is 6
mm and 8 mm, and the protective film 7 is a Si ₃ N ₄ film.

Protruding electrodes 4a, 4 formed by electroless Ni plating
The formation of b is similar to the ordinary electroless plating process of Ni on Al. For example, light etching, Zn substitution treatment, electroless Ni plating is performed to 3 μm, and finally electroless Au plating is performed for the purpose of preventing oxidation of the Ni surface. 0.2 μm is applied.
The Ni plating solution used is an electroless Ni plating solution containing nickel sulfate as a main component. At this time, the Ni protrusion electrode 4
When the areas of the Al electrodes 3a and 3b of a and 4b are different, the heights of the protruding electrodes 4a and 4b are also different, and the larger the area, the higher. This is because when the electrode size becomes smaller, the height grows differently due to the surface tension of the liquid and the circulating property of the liquid.
In this case, the protruding electrode 4b is higher than the protruding electrode 4a.

Therefore, at the time of connection, the Ni protruding electrode 4 is connected.
The protruding electrode 4b that causes stress concentration due to direct contact between a and 4b is formed on the electrode 3b other than on the element region 6, and thus on the electrode 3a on the element region 6 which is easily damaged by a load. The formed protruding electrode 4a has a structure in which stress concentration does not occur at the time of connection. Protruding electrode 4
The fabrication process of a and 4b is basically completed as described above, and the protruding electrodes 4a and 4b facing each other are connected so as to obtain an electrical connection.

In this connection process, all the protruding electrodes 4
It is necessary to deform until the contact between a and 4b is obtained. For example, if the height variation of the Ni protruding electrodes 4a and 4b is about 0.5 μm for the Ni protruding electrodes 4a and 4b on the electrodes 3a and 3b having the same area in the semiconductor chips 1 and 2, the minimum is 0.5 μm. As described above, the Ni protruding electrodes 4a and 4b must be deformed, and a bonding load that damages the element is required.

Therefore, in order to realize the bonding with a load that does not damage the device, a conductive material layer 8 is formed on the upper portions of the protruding electrodes 4a and 4b according to the bonding method. The conductive material layer 8 is plastically deformed within a load that does not damage the element, and the height variations of the protruding electrodes 4a and 4b and the chips 1 and 2 are increased.
It is necessary to absorb the warp of. For example, In or In and Sn, Pb, B may be used as a material that meets these conditions.
An alloy with i, Ag and Zn is used. As a method of forming the conductive material layer 8, a method of selectively forming the conductive material layer 8 on the protruding electrodes 4a and 4b by immersing the conductive material layer 8 in a melt of the conductive material is advantageous in terms of cost. Further, as the conductive material layer 8, a conductive paste made of resin and metal may be used. When the conductive paste is used, the conductive paste can be formed on the protruding electrodes 4a and 4b by an existing method such as transfer or injection.

In this way, the conductive material layer 8 is formed, the height variations of the Ni protruding electrodes 4a and 4b, and further the height variations of the conductive material layer 8 are absorbed to make contact, and then the heat diffusion is performed. The peripheral photo-curable insulating resin 5 is cured to complete the connection. That is, as shown in FIG. 2, the insulating resin 5 is applied to the second semiconductor chip 2, the semiconductor chip 1 and the semiconductor chip 2 are aligned, and the semiconductor chip is pressed by the pressing tool 11 through the insulating resin 5. Pressurize 1. At this time, the pressure applied to the electrode 3a on the element region 6 is set to 0.02 g / μm ² or less. As a result, the protruding electrodes 4a, 4b or the conductive material layer 8 are plastically deformed to bring all the protruding electrodes 4a, 4b or the conductive material layer 8 into contact, and in this state, the surrounding insulating resin 5 is cured to obtain a connection. .

According to this embodiment, the areas of the electrodes 3a formed on the element regions 6 of the first semiconductor chip 1 and the second semiconductor chip 2 are the same as those of the electrodes 3b formed on other than the element regions 6. Since the area is smaller than the area, the height of the bump electrode 4a formed on the electrode 3a on the element region 6 becomes lower than the height of the bump electrode 4b formed on the electrode 3b other than on the element region 6, Therefore, when the protruding electrodes 4a and 4b are joined, stress concentration occurs on the protruding electrodes 4b other than on the element region 6, and stress concentration does not occur on the protruding electrodes 4a on the element region 6. Therefore, in mounting an LSI in which the electrode 3a is formed on the element region 6, the element can be mounted without damaging the element, and thus mounting on a highly reliable laminated LSI or wiring board can be realized.

Further, since the protruding electrodes 4a and 4b of the first semiconductor chip 1 and the second semiconductor chip 2 are formed by the electroless plating method, the semiconductor chips 1 and 2 are immersed in the electroless plating solution. The protruding electrodes 4a and 4b can be formed only by itself, and the manufacturing cost can be reduced. One of the first semiconductor chip 1 and the second semiconductor chip 2 may be formed by electroless plating. In addition, the protruding electrodes 4a, 4b formed by the electroless plating method are provided on the protruding electrodes 4a, 4b.
Since the conductive material layer 8 having a hardness lower than that of 4b is formed, it is possible to perform bonding with a load that does not damage the element. That is, when the conductive material layer 8 is plastically deformed within a load that does not damage the element during connection,
The height variation of a and 4b and the warp of the semiconductor chips 1 and 2 are absorbed, and the pressure applied to the electrode 3a on the element region 6 becomes smaller than the pressure applied to the electrode 3b other than on the element region 6 to damage the element. Never give. In addition, the electrodes 3a, 3 of the first semiconductor chip 1 and the second semiconductor chip 2 are
In the step of electrically connecting b, since the pressure applied to the electrode 3a on the element region 6 is 0.02 g / μm ² or less, the element is not damaged.

When all the electrodes are formed on the element region 6, the semiconductor chip 1,
It is sufficient to form at least three dummy electrodes in 2 in the same manner as in the above embodiment. Further, at least one of the first semiconductor chip 1 and the second semiconductor chip 2 is
In the case of a wiring board, for example, when the second semiconductor chip 2 is a wiring board, the protruding electrodes 4a and 4b are formed on the first semiconductor chip 1 and the conductive material layer 8 is formed on the protruding electrodes 4a and 4b. Alternatively, it can be realized by forming it on a wiring board.

A second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that the electrode 3a on the element region 6 is divided by the protective film 7, and the area of each divided region 10 is larger than the area of the electrode 3b formed on other than the element region 6. Is also small. Since the electrode 3a is divided by the protective film 7, each divided electrode 3
The height of the protruding electrode 4a on a is lower than the height of the protruding electrode 4b of the electrode 3b formed on other than the element region 6, so that stress concentration on the electrode 3a formed on the element region 6 can be prevented at the time of bonding. Not only that, because the current capacity can be secured,
Any type of semiconductor chip can be used. Other composition effects
This is the same as in the first embodiment.

[0036]

According to the semiconductor device of the first aspect of the present invention, the areas of the electrodes formed on the element regions of the first semiconductor chip and the second semiconductor chip are formed outside the element region. Since it is smaller than the area of the electrode, the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than the element region, and therefore At the time of bonding, stress concentration occurs on the protruding electrodes other than on the element region, and stress concentration does not occur on the protruding electrodes on the element region. Therefore, when mounting an LSI in which electrodes are formed on the element region, the element can be mounted without damaging the element, and thus mounting on a highly reliable laminated LSI or wiring board can be realized.

According to the semiconductor device of the second aspect, the first
The electrodes formed on the element regions of the semiconductor chip and the second semiconductor chip are divided into at least two or more parts by the insulating film, so that the divided regions have an area larger than that of the electrodes formed other than on the element regions. Since the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than on the element region, therefore, at the time of joining the protruding electrodes, The stress concentration occurs on the protruding electrodes other than on the element region, so that the stress concentration does not occur on the protruding electrodes on the element region, and the current capacity can be secured. In addition, the same effect as that of the first aspect can be obtained.

In the third aspect, since at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by the electroless plating method, the semiconductor chip can be simply immersed in the electroless plating solution. A protruding electrode can be formed, and it can be manufactured at low cost. Further, as described in claims 1 and 2, since the height of the protruding electrode formed on the electrode on the element region is lower than the height of the protruding electrode formed on the electrode other than the element region, There is no damage to the element due to height variations of the protruding electrodes due to the state of the electrodes and the plating solution. The other effects are similar to those of claim 1 or 2.

In the fourth aspect, at least one of the first semiconductor chip and the second semiconductor chip is a wiring board, so that mounting on the wiring board can be realized. The other effects are similar to those of claim 1 or 2. According to the fifth aspect, since the conductive material layer having a hardness lower than that of the protruding electrode is formed on the protruding electrode formed by the electroless plating method, the element can be bonded with a load that does not damage the element. That is, when the conductive material layer is plastically deformed during connection within a load that does not damage the element, variations in height of the protruding electrodes and warpage of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is The pressure is smaller than the pressure applied to the electrodes other than the above and does not damage the device. The other effects are similar to those of claim 1 or 2.

In a sixth aspect of the present invention, as the conductive material layer of the fifth aspect, In or In containing Sn, Pb, Bi, Ag,
By using a metal containing at least one of Zn, the conductive material layer undergoes plastic deformation within a load that does not damage the element at the time of connection, and absorbs height variation of the protruding electrode and warpage of the semiconductor chip. You can According to a seventh aspect of the present invention, the conductive material layer according to the fifth aspect is a conductive paste made of a resin and a metal, so that the conductive material layer is plastically deformed within a load that does not damage an element at the time of connection, and the height of the protruding electrode is increased. It is possible to absorb variations and warpage of the semiconductor chip.

According to the method of manufacturing a semiconductor device according to the eighth aspect of the present invention, on the surface of the first semiconductor chip and the second semiconductor chip such that the area over the element region is smaller than the area over the element region. Since the electrodes are formed at the corresponding positions, the height of the protruding electrode formed on the electrode on the element region is lower than that of the protruding electrode formed on the electrode other than the element region. Therefore, the first semiconductor chip or the second semiconductor chip
When the back surface of the semiconductor chip is pressed to bond the protruding electrodes, stress concentration occurs on the protruding electrodes other than on the element region, and stress concentration does not occur on the protruding electrodes on the element region. Further, since the protruding electrodes are formed by the electroless plating treatment, the protruding electrodes can be formed only by immersing the semiconductor chip in the electroless plating solution, and the manufacturing cost can be reduced.

In the ninth aspect, since the pressure applied to the electrode on the element region is 0.02 g / μm ² or less in the eighth aspect, the element is not damaged. Claim 10
Then, according to claim 8, at least one of the first semiconductor chip and the second semiconductor chip is dipped in the melt of the metal forming the conductive material layer, so that the hardness is lower than the protruding electrode above the protruding electrode. Since the conductive material layer is formed, the elements can be bonded with a load that does not damage the element. That is, when the conductive material layer is plastically deformed during connection within a load that does not damage the element, variations in height of the protruding electrodes and warpage of the semiconductor chip are absorbed, and the pressure applied to the electrodes on the element region is The pressure is smaller than the pressure applied to the electrodes other than the above and does not damage the device. Further, since the conductive material layer is formed by immersing the conductive material in the melt of the conductive material as described above, it is advantageous in terms of cost.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of the first embodiment.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment.

[Explanation of symbols]

 1 1st semiconductor chip 2 2nd semiconductor chip 4a, 4b Projection electrode 5 Insulating resin 6 Element area 3a Al electrode formed on the element area 3b Al electrode formed on areas other than the element area 7 Protective film 8 Conductivity Material layer

Claims (10)

[Claims] 1. A projecting electrode formed on an electrode located on the surface of the first semiconductor chip, the surfaces of the first semiconductor chip and the second semiconductor chip being adhered to each other via an insulating resin. And a protruding electrode formed on an electrode corresponding to the electrode of the first semiconductor chip and located on the surface of the second semiconductor chip are electrically connected to each other. Semiconductor chip and second
The semiconductor device is characterized in that the area of the electrode formed on the element region of the semiconductor chip is smaller than the area of the electrode formed other than on the element region. 2. A protruding electrode formed on an electrode located on the surface of the first semiconductor chip, the surfaces of the first semiconductor chip and the second semiconductor chip being adhered to each other via an insulating resin. And a protruding electrode formed on an electrode corresponding to the electrode of the first semiconductor chip and located on the surface of the second semiconductor chip are electrically connected to each other. Semiconductor chip and second
The electrode formed on the element region of the semiconductor chip is composed of at least two regions divided by an insulating film, and the divided region has a smaller area than the electrodes formed other than on the element region. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein at least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by electroless plating. 4. The semiconductor device according to claim 1, wherein at least one of the first semiconductor chip and the second semiconductor chip is a wiring board. 5. At least one of the protruding electrodes of the first semiconductor chip and the second semiconductor chip is formed by an electroless plating method, and has a hardness higher than that of the protruding electrodes formed by an electroless plating method on the upper side thereof. The semiconductor device according to claim 1, wherein a low conductive material layer is formed. 6. The conductive material layer is In or Sn in In,
The semiconductor device according to claim 5, which is made of a metal containing at least one of Pb, Bi, Ag, and Zn. 7. The semiconductor device according to claim 5, wherein the conductive material layer is a conductive paste made of resin and metal. 8. A step of forming electrodes at corresponding positions on the surfaces of the first semiconductor chip and the second semiconductor chip so that the area of the element region is smaller than that of the area other than the element region. Forming a protruding electrode on the electrodes of the semiconductor chip and the second semiconductor chip by electroless plating, and applying an insulating resin on the surface of the first semiconductor chip or the second semiconductor chip. By aligning the protruding electrodes of the first semiconductor chip and the second semiconductor chip with each other, and pressing the back surface of the first semiconductor chip or the second semiconductor chip to cure the insulating resin. A method of manufacturing a semiconductor device, comprising a step of electrically connecting electrodes of the first semiconductor chip and the electrodes of the second semiconductor chip. 9. The pressure applied to the electrode on the element region is 0.02 g / μm ² or less in the step of electrically connecting the electrodes of the first semiconductor chip and the second semiconductor chip. Manufacturing method of semiconductor device. 10. In the step of forming protruding electrodes on the electrodes of the first semiconductor chip and the second semiconductor chip, the first semiconductor chip or the second semiconductor is added to the metal melt forming the conductive material layer. 9. The method for manufacturing a semiconductor device according to claim 8, wherein a conductive material layer having a hardness lower than that of the protruding electrode is formed on the protruding electrode by immersing at least one of the chips.