JP3021508B2 - Method of forming conductive protrusions - Google Patents
Method of forming conductive protrusionsInfo
- Publication number
- JP3021508B2 JP3021508B2 JP2033202A JP3320290A JP3021508B2 JP 3021508 B2 JP3021508 B2 JP 3021508B2 JP 2033202 A JP2033202 A JP 2033202A JP 3320290 A JP3320290 A JP 3320290A JP 3021508 B2 JP3021508 B2 JP 3021508B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrodes
- holder
- electrode
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マイクロエレクトロニクス分野における電
気回路部品同士を接続する際の接続材として用いられる
導電突起の形成方法に関し、特にICチップの電極へ導電
突起を精度良く形成できる導電突起の形成方法に関する
ものである。Description: TECHNICAL FIELD The present invention relates to a method for forming a conductive projection used as a connecting material when connecting electric circuit components in the field of microelectronics, and in particular, to a method for forming a conductive projection on an electrode of an IC chip. The present invention relates to a method for forming a conductive protrusion that can form a protrusion with high accuracy.
〔従来の技術〕 半導体製品の実装技術において対応する部品間の接続
方法としては、ワイヤボンディング法,フィルムキャリ
ア法(TAB(Tape Automated Bonding)法),フリップ
チップ法等が知られている。これらの各接続法につい
て、ICチップの電極と基板側のリードとの接続を例にし
て簡単に説明する。[Prior Art] As a connection method between components corresponding to a mounting technology of a semiconductor product, a wire bonding method, a film carrier method (TAB (Tape Automated Bonding) method), a flip chip method and the like are known. Each of these connection methods will be briefly described by taking the connection between the electrode of the IC chip and the lead on the substrate side as an example.
第10図はワイヤボンディング法の実装方式を示す模式
図であり、ICチップ41の各電極42と、プリント配線基板
43の対応する各リード44の接続部とがAuまたはAlからな
るワイヤ45にて、一組ずつ接続されている。このような
方式では、電極42とリード44とを一組ずつ順に接合して
いくので生産能率が低く、また隣合うワイヤ間において
接合時の干渉があるので、最小の接続ピッチには限界が
あり高密度な実装技術には適応できないことがある。FIG. 10 is a schematic diagram showing the mounting method of the wire bonding method, in which each electrode 42 of the IC chip 41 and the printed wiring board
The connection portions of the 43 corresponding leads 44 are connected one by one by wires 45 made of Au or Al. In such a method, the electrode 42 and the lead 44 are joined in order one by one so that the production efficiency is low, and there is interference at the time of joining between adjacent wires, so the minimum connection pitch has a limit. It may not be applicable to high-density mounting technology.
接続ピッチが短い高密度な実装を実現するための接続
方式がフィルムキャリア法である。第11図はフィルムキ
ャリア法の実装方式を示す模式図であって、この方法は
テープキャリア方式による自動ボンディング方法であ
り、予め導電突起47が形成されたICチップ41の各電極42
と各フィルムリード46とを位置決めした後、熱圧着によ
り一括に接続し、その後、各フィルムリード46とプリン
ト配線基板43の各リード44とを位置決めした後、一括に
接続する。また、第12図はフリップチップ法の実装方式
を示す模式図であり、その各電極42に予め導電突起47が
設けられたICチップ41をプリント配線基板43上に位置決
めして搭載させた後、導電突起47を加熱融解させること
によってICチップ41の電極42とプリント配線基板43の対
応するリード44とを接続する。A connection method for realizing high-density mounting with a short connection pitch is a film carrier method. FIG. 11 is a schematic view showing a mounting method of a film carrier method. This method is an automatic bonding method by a tape carrier method, and each electrode 42 of an IC chip 41 on which a conductive projection 47 is formed in advance.
After positioning the film leads 46 and the respective film leads 46, they are connected together by thermocompression bonding. Thereafter, the respective film leads 46 and the respective leads 44 of the printed wiring board 43 are positioned and then connected together. FIG. 12 is a schematic diagram showing the mounting method of the flip chip method, and after positioning and mounting the IC chip 41 provided with the conductive projection 47 in advance on each electrode 42 on the printed wiring board 43, The electrodes 42 of the IC chip 41 are connected to the corresponding leads 44 of the printed wiring board 43 by heating and melting the conductive protrusions 47.
上述した2方法(フィルムキャリア法及びフリップチ
ップ法)にあっては、接続部材としての導電突起が必要
であり、接続作業に先立って導電突起をICチップ41の電
極42に形成しておく必要がある。導電突起の形成方法と
しては、メッキ法を用いて電極42へ直接に導電突起を形
成する方法が公知である。In the above two methods (film carrier method and flip chip method), conductive protrusions are required as connecting members, and it is necessary to form conductive protrusions on the electrodes 42 of the IC chip 41 prior to connection work. is there. As a method of forming the conductive protrusion, a method of forming the conductive protrusion directly on the electrode 42 using a plating method is known.
第13図は、このような従来の導電突起の形成方法の工
程の1つの例を示す断面図であり、第13図に基づき簡単
にその工程を説明する。FIG. 13 is a cross-sectional view showing one example of the steps of such a conventional method for forming a conductive projection, and the steps will be briefly described with reference to FIG.
まず、ICチップ41の電極42及びパッシベーション膜50
上に、Cr層51,Cu層52,Au層53をこの順にスパッタリング
にて蒸着形成し(第13図(a))、導電突起を形成する
以外の領域に、フォトリソグラフィ法によりレジスト54
を形成する(第13図(b))次に、レジスト54の開口部
にメッキ法により金55を充填した後(第13図(c))、
レジスト54を除去する(第13図(d))。最後に、露出
した多層金属膜(Cr層51,Cu層52,Au層53)をエッチング
除去し、窒素雰囲気にて熱処理を行い、多層金属膜及び
金55からなる導電突起47を電極42に形成する(第13図
(e))。First, the electrode 42 of the IC chip 41 and the passivation film 50
On top of this, a Cr layer 51, a Cu layer 52, and an Au layer 53 are formed by vapor deposition in this order by sputtering (FIG. 13 (a)).
(FIG. 13 (b)) Next, after filling the opening of the resist 54 with gold 55 by a plating method (FIG. 13 (c)),
The resist 54 is removed (FIG. 13D). Finally, the exposed multilayer metal film (Cr layer 51, Cu layer 52, Au layer 53) is removed by etching, and heat treatment is performed in a nitrogen atmosphere to form a conductive projection 47 made of the multilayer metal film and gold 55 on the electrode 42. (FIG. 13 (e)).
上述したような従来の導電突起形成方法では、ICチッ
プの電極上に多層金属膜(バリヤメタル)を介して導電
突起を形成するので、複雑な工程,設備が必要であり、
高コストである。また、完成されたICチップに化学処理
を施して導電突起を形成するので、導電突起の形成に伴
ってICチップの歩留りが低下するという難点がある。In the conventional method for forming conductive protrusions as described above, since conductive protrusions are formed on the electrodes of the IC chip via a multilayer metal film (barrier metal), complicated processes and equipment are required.
High cost. In addition, since the completed IC chip is subjected to chemical treatment to form conductive protrusions, there is a problem that the yield of the IC chip is reduced with the formation of the conductive protrusions.
本発明はかかる事情に鑑みてなされたものであり、電
気的接続部材からなる保持体中に複数の導電体を散在さ
せた導電体保持材を使用し、この導電体を導電突起とし
てICチップの電極に転写することにより、ICチップの電
極への導電突起の形成を容易に行えて、基板側のリード
との高密度な接続においても信頼性が高い接続を達成で
きるICチップの電極への導電突起の形成方法を提供する
ことを目的とする。The present invention has been made in view of such circumstances, and uses a conductor holding material in which a plurality of conductors are scattered in a holding body made of an electrical connection member, and uses the conductor as a conductive protrusion to form an IC chip. By transferring to the electrodes, conductive protrusions can be easily formed on the electrodes of the IC chip, and highly reliable connection can be achieved even in high-density connection with the lead on the substrate side. An object of the present invention is to provide a method for forming a projection.
本願に係る第1発明の導電突起の形成方法は、接続用
の導電突起をICチップの電極に形成する方法において、
電気的絶縁材からなるシート状の保持体中に複数の導電
体が、夫々の両端を前記保持体の両面から突出させ、互
いに絶縁状態にして散在させてあり、これらの導電体の
前記保持体の一面からの突出部分を前記保持体中の部分
よりも大きくしてある導電体保持材を用い、前記導電体
の前記一面からの突出端部を前記ICチップの電極に位置
合わせし、位置合わせした各導電体を前記ICチップの電
極に転写して導電突起を形成することを特徴とする。According to a first aspect of the present invention, there is provided a method for forming a conductive projection for connection on an electrode of an IC chip,
A plurality of conductors are scattered in a sheet-shaped holder made of an electrically insulating material, with both ends protruding from both sides of the holder, insulated from each other, and the holders of these conductors are scattered. Using a conductor holding material having a protruding portion from one surface larger than a portion in the holder, aligning the protruding end of the conductor from the one surface with the electrode of the IC chip, and positioning. The conductive members thus formed are transferred to the electrodes of the IC chip to form conductive protrusions.
本願に係る第2発明の導電突起の形成方法は、第1発
明を行った後、前記導電体保持材の保持体を除去するこ
とを特徴とする。A method of forming a conductive projection according to a second invention according to the present invention is characterized in that, after performing the first invention, the holder of the conductor holding material is removed.
本願に係る第3の発明の導電突起の形成方法は、第1
発明において、前記ICチップの電極は複数であり、前記
導電体保持材の前記導電体を前記ICチップの電極に転写
する際に、すべての前記電極に対して一括に転写する方
式、前記電極のうちの複数ずつに対して一括に転写する
方式、または1個の電極に対して個別に順次転写する方
式のうちの何れかの方式を採用することを特徴とする。The method for forming a conductive projection according to the third invention of the present application is the first method.
In the present invention, a plurality of electrodes of the IC chip are provided, and when transferring the conductor of the conductor holding material to the electrodes of the IC chip, a method of collectively transferring the electrodes to all the electrodes, It is characterized by adopting any one of a method of transferring images to a plurality of them at once, and a method of transferring images sequentially to one electrode.
第1発明では、電気的絶縁材からなるシート状の保持
体に互いに絶縁状態として複数の導電体を散在させてあ
る導電体保持材を用い、前記保持体の両面に突出する導
電体の端部の内、保持体中の部分よりも大きくしてある
一面側の突出端部を対象となるICチップの電極に位置合
わせした後、各導電体を夫々が位置合わせされた電極に
転写して導電突起を形成する。そうすると、各電極に導
電突起が容易に形成される。第2発明では、この後必要
に応じて保持体を除去する。そうすると、導電突起のみ
の形成が可能である。ここで、導電体を転写して導電突
起を形成する際に、すべての電極について一括して導電
突起を形成しても良く、また1個の電極について順次個
別に導電突起を形成しても良く、更に電極を複数ずつの
群に分けて各群については一括して導電突起を形成する
こととしても良い。すべての電極について一括して導電
突起を形成する場合には、作業効率に優れ、1個の電極
について個別に導電突起を形成する場合には、接合精度
に優れる。According to a first aspect of the present invention, a plurality of conductors are scattered in a sheet-like holder made of an electrically insulating material in a state in which a plurality of conductors are insulated from each other. After aligning the protruding end on one side, which is larger than the part in the holder, with the electrode of the target IC chip, each conductor is transferred to the electrode to which it is aligned, and the conductor is transferred. Form protrusions. Then, a conductive protrusion is easily formed on each electrode. In the second invention, thereafter, the holder is removed as necessary. Then, only the conductive protrusion can be formed. Here, when forming the conductive protrusions by transferring the conductor, the conductive protrusions may be formed collectively for all the electrodes, or the conductive protrusions may be formed individually for one electrode sequentially. Alternatively, the electrodes may be divided into a plurality of groups, and each group may be collectively formed with conductive protrusions. When the conductive protrusions are formed collectively for all the electrodes, the working efficiency is excellent, and when the conductive protrusions are formed individually for one electrode, the joining accuracy is excellent.
第1図は本発明の導電突起の形成方法に使用する導電
体保持材1の平面図、第2図は第1図のII−II線におけ
る断面図である。導電体保持材1は、例えば金からなる
複数の導電体2を、夫々の導電体2同士が電気的絶縁状
態になるようにポリイミド樹脂からなる保持体3(厚さ
10μm程度)中に備えて構成されている。各導電体2の
両端は、保持体3の両面から夫々突出させてあり、保持
体3の一面側に突出する端部2aは、その径(25μm程
度)が保持体3内に埋設される部分の径(15μm程度)
よりも大きくなっており、所謂出張り形状(突出高さ4
〜8μm程度)をなしている。一方、各導電体2の他方
の端部2bは、保持体3の他面側に僅かに突出しているだ
けであり、その径は保持体3内に埋設される部分の径に
略等しい。なお、導電体2の形成ピッチは後述するICチ
ップの電極のピッチに合せている。FIG. 1 is a plan view of a conductor holding member 1 used in the method for forming a conductive projection of the present invention, and FIG. 2 is a sectional view taken along the line II-II of FIG. The conductor holding material 1 includes a plurality of conductors 2 made of, for example, gold, and a holder 3 (thickness) made of a polyimide resin such that the conductors 2 are electrically insulated from each other.
(About 10 μm). Both ends of each conductor 2 are projected from both sides of the holder 3, and the end 2 a projecting to one side of the holder 3 is a portion whose diameter (about 25 μm) is embedded in the holder 3. Diameter (about 15μm)
So-called projecting shape (projection height 4
程度 8 μm). On the other hand, the other end 2b of each conductor 2 only slightly protrudes toward the other surface of the holder 3, and its diameter is substantially equal to the diameter of a portion embedded in the holder 3. Note that the formation pitch of the conductors 2 matches the pitch of the electrodes of the IC chip described later.
次に、このような構成をなす導電体保持材の製造方法
の一例について、その工程を示す第3図に基づき説明す
る。Next, an example of a method for manufacturing the conductor holding material having such a configuration will be described with reference to FIG.
まず、準備した銅板11上にスピンナにより接着補助剤
を塗布した後、保持体となるネガ型のポリイミド樹脂12
をスピンナにより塗布する(第3図(a))。ここで硬
化に伴う膜厚の減少を考慮して塗布するポリイミド樹脂
12の膜厚は、製造される導電体保持材における保持体の
所望の膜厚よりも厚くする。次いで、所定パターンをな
したフォトマスク(図示せず)を介して光をポリイミド
樹脂12に照射した(露光した)後、現像を行う。本例で
は、露光された部分にはポリイミド樹脂12が残存し、露
光されない部分は現像処理によりポリイミド樹脂12が除
去されて穴13が形成される。その後温度を上げてポリイ
ミド樹脂12の硬化を行う(第3図(b))。次に、この
ような処理がなされた銅板11をエッチング液中に浸漬さ
せてエッチングを行う。穴13の近傍の銅板11の一部がエ
ッチング除去され、穴13に連通する凹部14が銅板11に形
成される(第3図(c))。銅板11を共通電極として金
15の電気メッキを行い、ポリイミド樹脂12の上面より僅
かに金15が突出するまで金メッキを施し、穴13,凹部14
に金15を充填する(第3図(d))。最後に、金属エッ
チングにより銅板11を除去して、第1,2図に示すような
導電体保持材1(上下関係は逆)を製造する。First, after applying an adhesion aid to the prepared copper plate 11 by a spinner, a negative polyimide resin 12 serving as a holding body is applied.
Is applied by a spinner (FIG. 3A). Polyimide resin applied here in consideration of the decrease in film thickness due to curing
The film thickness of 12 is larger than the desired film thickness of the holder in the conductor holding material to be manufactured. Next, after the polyimide resin 12 is irradiated with light (exposed) through a photomask (not shown) having a predetermined pattern, development is performed. In this example, the polyimide resin 12 remains in the exposed portion, and the unexposed portion removes the polyimide resin 12 by a development process to form a hole 13. Thereafter, the temperature is raised to cure the polyimide resin 12 (FIG. 3 (b)). Next, the copper plate 11 thus treated is immersed in an etching solution to perform etching. A portion of the copper plate 11 near the hole 13 is removed by etching, and a concave portion 14 communicating with the hole 13 is formed in the copper plate 11 (FIG. 3C). Use copper plate 11 as common electrode
15 electroplating, gold plating until the gold 15 slightly protrudes from the upper surface of the polyimide resin 12, holes 13, recesses 14
Is filled with gold 15 (FIG. 3 (d)). Finally, the copper plate 11 is removed by metal etching to manufacture the conductor holding material 1 (the up-down relationship is reversed) as shown in FIGS.
本実施例にあっては、製造された導電体保持材1にお
いて、導電体2,保持体3は夫々、金15,ポリイミド樹脂1
2から構成されており、保持体3の一面側に突出する導
電体2の一方の端部2aは、他方の端部2bを含めた保持体
3中の部分よりも大きくされ、出張り形状をなしてい
る。In this embodiment, in the manufactured conductor holding member 1, the conductor 2 and the holder 3 are made of gold 15 and polyimide resin 1 respectively.
2, one end 2a of the conductor 2 protruding to one surface side of the holder 3 is made larger than a portion in the holder 3 including the other end 2b, and has a projecting shape. No.
第4図は、本発明の導電体保持材を製造する別の工程
を示す断面図である。前述の実施例と同様に、銅板11上
にポリイミド樹脂12を塗布した後(第4図(a))、ポ
リイミド樹脂12を所定パターンにて露光,現像して穴13
を形成し、温度を上げてポリイミド樹脂12の硬化を行う
(第4図(b))。このような処理がなされた銅板11上
をエッチング液にて、前述の実施例と同様にエッチング
を行って凹部14を形成するのであるが、この実施例では
前述の実施例に比べてこのエッチング時間を短くする。
そうすると前述の実施例に比べて浅い凹部14が銅板11に
形成される(第4図(c))。その後、銅板11を共通電
極として金15の電気メッキを施し、穴13,凹部14に金15
を充填するのであるが、本実施例ではポリイミド樹脂12
の上より所定高さに金15が突出するまで金メッキを続け
る(第4図(d))。最後に、金属エッチングにより銅
板11を除去して、第1,2図に示すような導電体保持材1
を製造する。FIG. 4 is a cross-sectional view showing another step of manufacturing the conductor holding material of the present invention. After the polyimide resin 12 is applied on the copper plate 11 (FIG. 4 (a)), the polyimide resin 12 is exposed and developed in a predetermined pattern, and the holes 13 are formed.
Is formed, and the temperature is increased to cure the polyimide resin 12 (FIG. 4 (b)). The concave portion 14 is formed by etching the copper plate 11 thus treated with an etching solution in the same manner as in the above-described embodiment, but in this embodiment, the etching time is longer than that in the above-described embodiment. Shorten.
Then, a shallow concave portion 14 is formed in the copper plate 11 as compared with the above-described embodiment (FIG. 4C). Thereafter, electroplating of gold 15 is performed using the copper plate 11 as a common electrode, and gold 15 is
In this embodiment, the polyimide resin 12 is filled.
Gold plating is continued until the gold 15 protrudes to a predetermined height from above (FIG. 4 (d)). Finally, the copper plate 11 is removed by metal etching, and the conductor holding material 1 as shown in FIGS.
To manufacture.
次に、このような導電体保持材を用いる本発明の導電
突起の形成方法について具体的に説明する。Next, a method for forming a conductive projection of the present invention using such a conductor holding material will be specifically described.
第5図はICチップの電極形成面の平面図、第6図は第
5図のVI−VI線における断面図である。図において21は
電極形成面にA1からなる電極22が形成されたICチップで
あり、電極22が形成されていないICチップ21の表面には
パッシベーション膜30が形成されている。このようなIC
チップ21の各電極22に、第1,2図に示すような導電体保
持材1の各導電体2(端部2a)を位置合わせした後、ボ
ンディング治具28を白抜矢符方向に移動させて、熱圧着
法により、導電突起たる導電体2をすべての電極22に対
して一括に転写,接合する(第7図(a))。圧着,転
写された導電突起2(Au)と電極22(Al)とは金属結合
されて、強い接合がなされる。次に、保持体3を機械的
に剥離して、導電突起2のみを電極22に形成する(第7
図(b))。ここで、電極22に接しない側の導電体2の
端部2bの径は、保持体3中の部分の径と略同じであるの
で、この保持体3の除去は容易である。なお、機械的な
剥離(引き剥がし)とは異なり、化学的な溶解処理によ
り保持体3を除去することとしても良い。FIG. 5 is a plan view of the electrode forming surface of the IC chip, and FIG. 6 is a sectional view taken along line VI-VI of FIG. In the figure, reference numeral 21 denotes an IC chip in which an electrode 22 made of A1 is formed on an electrode forming surface, and a passivation film 30 is formed on a surface of the IC chip 21 on which the electrode 22 is not formed. IC like this
After positioning each conductor 2 (end 2a) of the conductor holding material 1 as shown in FIGS. 1 and 2 with each electrode 22 of the chip 21, the bonding jig 28 is moved in the direction of the white arrow. Then, the conductors 2 serving as conductive protrusions are collectively transferred and bonded to all the electrodes 22 by a thermocompression bonding method (FIG. 7A). The conductive projections 2 (Au) and the electrodes 22 (Al), which have been pressed and transferred, are metal-bonded to form a strong bond. Next, the holder 3 is mechanically peeled off, and only the conductive protrusions 2 are formed on the electrodes 22 (the seventh step).
Figure (b). Here, since the diameter of the end 2b of the conductor 2 on the side not in contact with the electrode 22 is substantially the same as the diameter of the part in the holder 3, the holder 3 can be easily removed. Note that, unlike mechanical peeling (peeling), the holder 3 may be removed by a chemical dissolution treatment.
第8図は、導電突起の転写,形成の別の例を示す断面
図であり、この例では、複数個ずつの電極22に対して、
ボンディング治具28を移動させて熱圧着法により導電突
起2を形成している。また第9図は、導電突起の転写,
形成の更に別の例を示す断面図であり、この例では、1
個の電極22に対して、ボンディング治具28を移動させて
個別に導電突起2を形成している。なお、この方式では
熱圧着法に加えて、超音波を併用した熱圧着法によって
も導電突起の形成は可能である。FIG. 8 is a cross-sectional view showing another example of the transfer and formation of the conductive projection.
The conductive protrusions 2 are formed by moving the bonding jig 28 by a thermocompression bonding method. FIG. 9 shows the transfer of conductive protrusions,
It is sectional drawing which shows another example of formation, In this example, 1
The conductive protrusions 2 are individually formed by moving the bonding jig 28 with respect to the individual electrodes 22. In this method, the conductive protrusions can be formed by a thermocompression bonding method using ultrasonic waves in addition to the thermocompression bonding method.
上述したような3方式〔すべての電極に対して一括に
導電突起を形成する方式(第7図:以下一括形成方式と
いう)、複数個ずつの電極に対して一括に導電突起を形
成する方式(第8図:以下部分形成方式という)、1個
ずつの電極に対して個別に導電突起を形成する方式(第
9図:以下個別形成方式という)〕における利点,欠点
について説明する。The above-described three methods (a method in which conductive protrusions are formed on all electrodes at once (FIG. 7: hereinafter referred to as a collective formation method), a method in which conductive protrusions are formed on a plurality of electrodes at once ( The advantages and disadvantages of the method of individually forming conductive projections for each electrode (FIG. 8: hereinafter referred to as a partial formation method) (FIG. 9: hereinafter referred to as an individual formation method) will be described.
一括形成方式では、同時にすべての電極について導電
突起を形成できるので作業時間は短いが、使用する導電
体保持材における各導電体の突出高さにバラツキがある
場合には接合不良が起こり易い。一方、個別形成方式で
は、1個毎に確実に電極に導電突起を形成するので、接
合の信頼性は極めて高いが、作業時間に長時間を要する
という難点がある。また、部分形成方式は、両者の中間
にあたる特性を有している。In the collective formation method, since the conductive protrusions can be formed on all the electrodes at the same time, the operation time is short. However, if the protrusion heights of the respective conductors in the used conductor holding material vary, a joint failure is likely to occur. On the other hand, in the individual formation method, since the conductive protrusions are reliably formed on the electrodes one by one, the reliability of bonding is extremely high, but there is a disadvantage that a long working time is required. In addition, the partial formation method has characteristics that are intermediate between the two.
各形成方式は以上のような特性を夫々有しているの
で、使用する導電体保持材の形状、転写される側のICチ
ップの電極の形状等の条件を鑑みて、これらの3方式か
ら最適な方式を選択して採用すれば良い。例えば、導電
体保持材における導電体の突出高さのバラツキの程度に
より、以下のように3方式を選択すれば良い。Each forming method has the above characteristics, so it is most suitable for these three methods in consideration of the conditions such as the shape of the conductor holding material used and the shape of the electrode of the IC chip to be transferred. What is necessary is just to select and adopt a suitable method. For example, one of the following three methods may be selected according to the degree of variation in the height of protrusion of the conductor in the conductor holding material.
バラツキが小さい場合:一括形成方式 バラツキが中程度の場合:部分形成方式 バラツキが大きい場合:個別形成方式 また上述の実施例では、導電体2を転写した後保持体
3を除去することとしたが、この保持体3を残存させて
おいても良い。保持体3を除去するが、残存させるかに
ついては一長一短がある。絶縁性の樹脂からなる保持体
3を除去する際の長所は、高吸湿性という保持体3の特
性が作製されるICパッケージに及ぼす悪影響を防止でき
る点であり、保持体3を残存する際の長所は、保持体3
は絶縁材であるので隣合う導電体同士の短絡を防止でき
る点である。そして、保持体3を除去するか、残存させ
るかについては、ICチップの電極の形成パターンに合せ
て任意に選択すれば良い。When the variation is small: Batch formation method When the variation is medium: Partial formation method When the variation is large: Individual formation method In the above-described embodiment, the holder 3 is removed after the conductor 2 is transferred. Alternatively, the holder 3 may be left. There is an advantage and disadvantage as to whether the holder 3 is removed or left. An advantage of removing the holding member 3 made of an insulating resin is that the characteristics of the holding member 3 having high moisture absorption can be prevented from adversely affecting the IC package to be manufactured. The advantage is the holder 3
Is a point that a short circuit between adjacent conductors can be prevented because of an insulating material. Whether the holder 3 is removed or left may be arbitrarily selected according to the pattern of forming the electrodes of the IC chip.
以上詳述した如く、本発明の導電突起の形成方法を用
いることにより、容易に低コストにてしかも信頼性が高
く、接続用の導電突起をICチップの電極に形成すること
ができ、高密度な実装においてもICチップの電極と基板
側のリードとの高精度の接続を実現できる。また、従来
法のように完成されたICチップの電極に化学処理を施す
ことがないので、形成処理に伴うICチップの歩留り低下
の虞はない。また、導電体を電極に転写した後に、保持
体を除去する場合には、導電突起のみをICチップの電極
に形成することが可能である。As described in detail above, by using the method for forming conductive protrusions of the present invention, conductive protrusions for connection can be easily formed on electrodes of an IC chip at low cost and with high reliability. High precision connection between the electrodes of the IC chip and the leads on the substrate side can be realized even in a simple mounting. Further, since the chemical treatment is not performed on the electrodes of the completed IC chip unlike the conventional method, there is no possibility that the yield of the IC chip is reduced due to the forming process. When the holder is removed after transferring the conductor to the electrode, only the conductive protrusion can be formed on the electrode of the IC chip.
第1図は本発明の導電突起の形成方法に使用する導電体
保持材の平面図、第2図は第1図のII−II線における断
面図、第3図はこの導電体保持材の製造工程の一例を示
す断面図、第4図はこの導電体保持材の製造工程の別の
例を示す断面図、第5図はICチップの電極形成面の平面
図、第6図は第5図のVI−VI線における断面図、第7図
は本発明の導電突起の形成方法の実施例を示す断面図、
第8図,第9図は本発明の導電突起の形成方法の別の実
施例を示す断面図、第10〜第12図は実装方式を示す模式
図、第13図は従来の導電突起の形成方法を示す断面図で
ある。 1……導電体保持材、2……導電体(導電突起)、2a,2
b……端部、3……保持体、21……ICチップ、22……電
極、28……ボンディング治具FIG. 1 is a plan view of a conductor holding material used in the method for forming a conductive projection of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing an example of the process, FIG. 4 is a cross-sectional view showing another example of the manufacturing process of the conductor holding material, FIG. 5 is a plan view of the electrode forming surface of the IC chip, and FIG. FIG. 7 is a cross-sectional view taken along line VI-VI of FIG. 7, and FIG.
8 and 9 are cross-sectional views showing another embodiment of the method for forming conductive projections according to the present invention, FIGS. 10 to 12 are schematic views showing a mounting method, and FIG. 13 is a conventional method for forming conductive projections. It is sectional drawing which shows a method. 1 ... conductor holding material, 2 ... conductor (conductive protrusion), 2a, 2
b ... end, 3 ... holder, 21 ... IC chip, 22 ... electrode, 28 ... bonding jig
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭64−59944(JP,A) 特開 昭64−22048(JP,A) 特開 平1−243554(JP,A) 特表 昭59−500394(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-59944 (JP, A) JP-A-64-22048 (JP, A) JP-A-1-243554 (JP, A) Table of Japanese Patent Application No. 59-1984 500394 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/60
Claims (3)
する方法において、 電気的絶縁材からなるシート状の保持体中に複数の導電
体が、夫々の両端を前記保持体の両面から突出させ、互
いに絶縁状態にして散在させてあり、これらの導電体の
前記保持体の一面からの突出部分を前記保持体中の部分
よりも大きくしてある導電体保持材を用い、 前記導電体の前記一面からの突出端部を前記ICチップの
電極に位置合わせし、位置合わせした各導電体を前記IC
チップの電極に転写して導電突起を形成することを特徴
とする導電突起の形成方法。1. A method of forming conductive projections for connection on an electrode of an IC chip, wherein a plurality of conductors are provided in a sheet-like holder made of an electrically insulating material, with both ends of the conductors being placed on both sides of the holder. Using a conductor holding material, in which the conductors are scattered in an insulated state from each other, and projecting portions of these conductors from one surface of the holder are made larger than portions in the holder. The protruding end of the one surface is aligned with the electrode of the IC chip, and each aligned conductor is mounted on the IC.
A method for forming a conductive projection, wherein the conductive projection is formed by transferring to a chip electrode.
の電極に転写した後、前記導電体保持材の保持体を除去
する請求項1記載の導電突起の形成方法。2. The method according to claim 1, wherein the conductor of the conductor holding material is transferred to an electrode of the IC chip, and then the holder of the conductor holding material is removed.
電体保持材の前記導電体を前記ICチップの電極に転写す
る際に、すべての前記電極に対して一括に転写する方
式、前記電極のうちの複数ずつに対して一括に転写する
方式、または1個の電極に対して個別に順次転写する方
式のうちの何れかの方式を採用する請求項1記載の導電
突起の形成方法。3. The method according to claim 1, wherein the plurality of electrodes of the IC chip are plural, and when the conductor of the conductor holding material is transferred to the electrodes of the IC chip, the electrodes are collectively transferred to all the electrodes. 2. The method according to claim 1, wherein one of a method of collectively transferring a plurality of electrodes and a method of sequentially transferring a plurality of electrodes individually is adopted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2033202A JP3021508B2 (en) | 1990-02-13 | 1990-02-13 | Method of forming conductive protrusions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2033202A JP3021508B2 (en) | 1990-02-13 | 1990-02-13 | Method of forming conductive protrusions |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03236241A JPH03236241A (en) | 1991-10-22 |
JP3021508B2 true JP3021508B2 (en) | 2000-03-15 |
Family
ID=12379887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2033202A Expired - Lifetime JP3021508B2 (en) | 1990-02-13 | 1990-02-13 | Method of forming conductive protrusions |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3021508B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW336371B (en) * | 1995-07-13 | 1998-07-11 | Motorola Inc | Method for forming bumps on a substrate the invention relates to a method for forming bumps on a substrate |
-
1990
- 1990-02-13 JP JP2033202A patent/JP3021508B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH03236241A (en) | 1991-10-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3285796B2 (en) | Conductive contact pad connection method | |
US5989939A (en) | Process of manufacturing compliant wirebond packages | |
JPH088278B2 (en) | Method for forming semiconductor chip package and chip bonding tape therefor | |
JP2002184904A (en) | Semiconductor device and method for manufacturing the same | |
JPH07201864A (en) | Projection electrode formation method | |
JP2003508898A (en) | Microbeam assembly and internal connection method between integrated circuit and substrate | |
EP0482940B1 (en) | Method of forming an electrical connection for an integrated circuit | |
JP3021508B2 (en) | Method of forming conductive protrusions | |
JPH0357617B2 (en) | ||
JP3268615B2 (en) | Manufacturing method of package parts | |
JPH088293A (en) | Structure for connecting electronic parts and connection method therefor | |
KR0165883B1 (en) | Gold/tin eutectic bonding for tape automated process | |
JP3021509B2 (en) | Method of forming conductive protrusions | |
JP2867547B2 (en) | Method of forming conductive protrusions | |
JP2879159B2 (en) | Method of forming electrical connection member and metal bump | |
JPH09307019A (en) | Manufacture of semiconductor package and semiconductor package | |
JP2508494B2 (en) | Film carrier manufacturing method | |
JPS59201452A (en) | Device sealing for high density tape bonding | |
JP2605999B2 (en) | Semiconductor package manufacturing method | |
JPH05291260A (en) | Forming method for bump | |
JPH02232947A (en) | Semiconductor integrated circuit device and mounting thereof | |
JP2000299399A (en) | Semiconductor device | |
JPH0982752A (en) | Semiconductor device | |
JPS6242549A (en) | Package for electronic part and manufacture thereof | |
JPH04154137A (en) | Manufacture of film carrier tape |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090114 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100114 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100114 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110114 Year of fee payment: 11 |
|
EXPY | Cancellation because of completion of term | ||
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110114 Year of fee payment: 11 |