JPH088293A - Structure for connecting electronic parts and connection method therefor - Google Patents

Structure for connecting electronic parts and connection method therefor

Info

Publication number
JPH088293A
JPH088293A JP6156401A JP15640194A JPH088293A JP H088293 A JPH088293 A JP H088293A JP 6156401 A JP6156401 A JP 6156401A JP 15640194 A JP15640194 A JP 15640194A JP H088293 A JPH088293 A JP H088293A
Authority
JP
Japan
Prior art keywords
substrate
electronic component
connection
semiconductor chip
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6156401A
Other languages
Japanese (ja)
Inventor
Michihiko Yamamoto
充彦 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP6156401A priority Critical patent/JPH088293A/en
Publication of JPH088293A publication Critical patent/JPH088293A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To connect a semiconductor chip with a film substrate by a small number of steps and without thermocompression bonding when they are subject to bonding. CONSTITUTION:A through-hole 17 is made in an insulation film 16 forming on the upper surface side of a semiconductor chip 11,' corresponding to a connection pad 14 and metallic layer 15. A through-hole 22 is also made in a film substrate 21 corresponding to the hole 17. Wiring patterns 24 and 25 are formed on the upper surface of the substrate 21. Then, the lower surface of the substrate 21 is fixed on the upper surface of the film 16 with an adhesive 26, and a conductive resin 27 is provided inside the holes 22 and 17 and adjacent to them, thereby electrically connecting the patterns 24 and 25 and the layer 15 through the resin 27. In this case, the resin 27 is formed by screen printing, resulting in connecting them by a small number of steps and without thermocompression bonding.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は電子部品の接続構造お
よびその接続方法に関し、特に、半導体チップ等からな
る電子部品と基板とを接続した電子部品の接続構造およ
びその接続方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connecting structure for electronic components and a connecting method therefor, and more particularly to a connecting structure for electronic components in which an electronic component such as a semiconductor chip is connected to a substrate and a connecting method therefor.

【0002】[0002]

【従来の技術】例えばTABテープでは、フィルム基板
に半導体チップを搭載(接続)した構造となっている。
図6は従来のこのようなTABテープの一例を示したも
のである。このTABテープはフィルム基板1を備えて
いる。フィルム基板1の所定の個所にはデバイスホール
2が設けられている。フィルム基板1の下面には、デバ
イスホール2内に突出されたフィンガリード(インナリ
ード)3等が設けられている。そして、フィルム基板1
の下面側からデバイスホール2の部分に配置された半導
体チップ4の上面に設けられたバンプ5がフィンガリー
ド3の下面に半田(図示せず)を介して接続されている
ことにより、半導体チップ4がフィルム基板1に搭載さ
れている。なお、半導体チップ4は、チップ本体6上に
形成されたパッシベーション膜7に形成された開口部を
介してチップ本体6上に形成された接続パッド8が露出
され、この露出された接続パッド8上に下地金属層9お
よびバンプ5が形成された構造となっている。この場
合、バンプ5の形成は電解メッキまたは無電解メッキに
より行っている。また、半導体チップ4のバンプ5とフ
ィンガリード3との半田を介しての接続は、熱圧着ヘッ
ドを用いた熱圧着により行っている。
2. Description of the Related Art For example, a TAB tape has a structure in which a semiconductor chip is mounted (connected) on a film substrate.
FIG. 6 shows an example of such a conventional TAB tape. This TAB tape includes a film substrate 1. A device hole 2 is provided at a predetermined position on the film substrate 1. Finger leads (inner leads) 3 and the like protruding into the device holes 2 are provided on the lower surface of the film substrate 1. And the film substrate 1
Since the bumps 5 provided on the upper surface of the semiconductor chip 4 arranged in the device hole 2 from the lower surface side of the are connected to the lower surface of the finger leads 3 via solder (not shown), the semiconductor chip 4 Are mounted on the film substrate 1. In the semiconductor chip 4, the connection pad 8 formed on the chip body 6 is exposed through the opening formed in the passivation film 7 formed on the chip body 6, and the exposed connection pad 8 is exposed. The base metal layer 9 and the bumps 5 are formed in the structure. In this case, the bumps 5 are formed by electrolytic plating or electroless plating. Further, the bump 5 of the semiconductor chip 4 and the finger lead 3 are connected to each other via solder by thermocompression bonding using a thermocompression bonding head.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
このような電子部品の接続構造では、半導体チップ4の
バンプ5の形成を電解メッキまたは無電解メッキにより
行っており、また半導体チップ4のバンプ5とフィンガ
リード3との半田を介しての接続を熱圧着ヘッドを用い
た熱圧着により行っているので、バンプ形成工程と熱圧
着工程とが別々であり、したがって工程数が多く、生産
性が悪いばかりでなく、コスト高になるという問題があ
った。また、熱圧着する際、特に半導体チップ4に比較
的大きな圧力と熱が加わるので、半導体チップ4のダメ
ージが大きく、不良品が発生することがあるという問題
があった。また、このような不良品が発生したり、半導
体チップ4のバンプ5とフィンガリード3との接続に不
良な箇所があったりする場合には、動作試験の結果不良
品と判定されるが、バンプ5とフィンガリード3との半
田を介しての接続が金属的であるので、両者を良好に分
離して別の半導体チップ4と交換することができず、こ
のためフィンガリード3等を備えたフィルム基板1が良
品であっても、そのまま廃棄することとなり、無駄であ
るという問題があった。さらに、半導体チップ4の多ピ
ン化を図る場合、デバイスホール2内に突出されたフィ
ンガリード3の配置位置に制約を受ける関係から、フィ
ンガリード3を細くせざるを得ないが、細くするとフィ
ンガリード3がデバイスホール2内に突出しているため
強度的に弱くなり、この結果フィンガリード3が曲がっ
たり切断したりしやすくなり、取り扱いにかなりの注意
を要することになるという問題があった。この発明の目
的は、少ない工程数でかつ熱圧着によらないで接続する
ことのできる電子部品の接続構造およびその接続方法を
提供することにある。また、この発明の他の目的は、多
ピン化に無理なく対応することのできる電子部品の接続
構造およびその接続方法を提供することにある。
However, in the conventional connection structure for such electronic parts, the bumps 5 of the semiconductor chip 4 are formed by electrolytic plating or electroless plating, and the bumps 5 of the semiconductor chip 4 are formed. Since the connection between the lead and the finger lead 3 via solder is performed by thermocompression bonding using a thermocompression bonding head, the bump forming process and the thermocompression bonding process are separate, so that the number of processes is large and the productivity is poor. Not only that, but there was also the problem of high costs. In addition, since relatively large pressure and heat are applied especially to the semiconductor chip 4 during thermocompression bonding, there is a problem that the semiconductor chip 4 is greatly damaged and a defective product may occur. Further, when such a defective product is generated or there is a defective portion in the connection between the bump 5 of the semiconductor chip 4 and the finger lead 3, it is determined as a defective product as a result of the operation test. Since the connection between the lead wire 5 and the finger lead 3 via the solder is metallic, it is not possible to satisfactorily separate the two and to replace it with another semiconductor chip 4, and therefore the film provided with the finger lead 3 and the like. Even if the substrate 1 is a good product, it is discarded as it is, which is a problem. Further, when the number of pins of the semiconductor chip 4 is increased, the finger leads 3 have to be thinned because of the restriction of the arrangement position of the finger leads 3 protruding in the device hole 2, but if they are thinned, the finger leads 3 will have to be thinned. Since 3 protrudes into the device hole 2, the strength is weakened, and as a result, the finger lead 3 is easily bent or cut, and there is a problem in that it requires considerable care in handling. An object of the present invention is to provide a connection structure of an electronic component and a connection method thereof, which can be connected by a small number of steps and without thermocompression bonding. Another object of the present invention is to provide a connection structure of an electronic component and a connection method thereof that can cope with the increase in the number of pins without difficulty.

【0004】[0004]

【課題を解決するための手段】請求項1記載の発明に係
る電子部品の接続構造は、一の面に複数の接続電極を有
する電子部品と、一の面に配線パターンを有するととも
に、前記電子部品の接続電極とそれぞれ対応する部分に
貫通孔を有する基板と、前記基板の貫通孔内およびその
近傍にそれぞれ設けられた導電部材とからなり、前記電
子部品を前記基板の一の面に対して反対側の面に固着す
るとともに、前記導電部材を介して前記電子部品の接続
電極と前記基板の配線パターンとを導電接続したもので
ある。請求項3記載の発明に係る電子部品の接続構造
は、一の面に複数の第1の接続電極が設けられ、その上
に層間絶縁膜が設けられ、その上であって前記第1の接
続電極の配置位置とは少なくとも一部で異なる位置に第
2の接続電極が相対応する前記第1の接続端子とそれぞ
れ接続されて設けられた電子部品と、一の面に配線パタ
ーンを有するとともに、前記電子部品の第2の接続電極
とそれぞれ対応する部分に貫通孔を有する基板と、前記
基板の貫通孔内およびその近傍にそれぞれ設けられた導
電部材とからなり、前記電子部品を前記基板の一の面に
対して反対側の面に固着されているとともに、前記導電
部材を介して前記電子部品の第2の接続電極と前記基板
の配線パターンとを導電接続したものである。請求項5
記載の発明に係る電子部品の接続方法は、請求項1〜4
のいずれかに記載の電子部品の接続構造の接続に際し、
前記電子部品と前記基板とを固着した後、前記基板の貫
通孔内およびその近傍に前記導電部材をスクリーン印刷
により塗布して設けるようにしたものである。
According to a first aspect of the present invention, there is provided a connection structure for an electronic component, wherein the electronic component has a plurality of connection electrodes on one surface and a wiring pattern on the one surface. A substrate having through holes in portions corresponding to the connection electrodes of the components, and a conductive member provided in the through holes of the substrate and in the vicinity thereof, respectively, and the electronic component with respect to one surface of the substrate. In addition to being fixed to the surface on the opposite side, the connection electrode of the electronic component and the wiring pattern of the substrate are conductively connected via the conductive member. According to a third aspect of the present invention, there is provided an electronic component connecting structure, wherein a plurality of first connecting electrodes are provided on one surface, an interlayer insulating film is provided on the first connecting electrodes, and the first connecting electrodes are provided on the interlayer insulating film. An electronic component provided with a second connection electrode connected to the corresponding first connection terminal at a position different from at least part of the position where the electrode is arranged, and a wiring pattern on one surface, The electronic component is composed of a substrate having a through hole in a portion corresponding to the second connection electrode of the electronic component, and a conductive member provided in and near the through hole of the substrate. The second connection electrode of the electronic component and the wiring pattern of the substrate are conductively connected to each other through the conductive member while being fixed to the surface opposite to the surface of the above. Claim 5
A method of connecting electronic components according to the invention described in any one of claims 1 to 4.
When connecting the electronic component connection structure according to any one of
After the electronic component and the substrate are fixed to each other, the conductive member is applied to the inside of the through hole of the substrate and its vicinity by screen printing.

【0005】[0005]

【作用】請求項1記載の発明によれば、半導体チップ等
からなる電子部品の接続電極とフィルム基板等からなる
基板の配線パターンとを、基板の貫通孔内およびその近
傍に設けた導電部材を介して導電接続しているので、例
えば請求項5記載の発明のように、基板の貫通孔内およ
びその近傍に導電部材をスクリーン印刷により塗布して
設けると、この設けられた導電部材を介して電子部品の
接続電極と基板の配線パターンとを導電接続することが
でき、したがって少ない工程数でかつ熱圧着によらない
で接続することができる。また、請求項3記載の発明に
よれば、半導体チップ等からなる電子部品の構造が、一
の面に設けられた第1の接続電極の配置位置とは少なく
とも一部で異なる位置に第2の接続電極を相対応する第
1の接続端子とそれぞれ接続させて設けた構造であるの
で、第2の接続電極の配置位置を比較的自由に選定する
ことができ、ひいては多ピン化しても基板の配線パター
ンの配置位置にあまり制約を受けず、したがって多ピン
化に無理なく対応することができる。
According to the first aspect of the present invention, a conductive member is provided in which a connecting electrode of an electronic component such as a semiconductor chip and a wiring pattern of a substrate such as a film substrate are provided in the through hole of the substrate and in the vicinity thereof. Since the conductive connection is made through the conductive member, for example, when a conductive member is applied by screen printing in and around the through hole of the substrate as in the invention of claim 5, the conductive member is provided through the provided conductive member. The connection electrode of the electronic component and the wiring pattern of the substrate can be conductively connected, and therefore can be connected in a small number of steps and without thermocompression bonding. According to the third aspect of the invention, the structure of the electronic component including the semiconductor chip and the like is arranged at a position different from at least a part of the position of the first connection electrode provided on the one surface in the second structure. Since the structure is such that the connection electrodes are connected to the corresponding first connection terminals respectively, the arrangement position of the second connection electrodes can be selected relatively freely, and even if the number of pins is increased, the board The arrangement position of the wiring pattern is not so restricted, so that it is possible to cope with the increase in the number of pins without difficulty.

【0006】[0006]

【実施例】図1はこの発明の一実施例における電子部品
の接続構造の要部を示したものである。この電子部品の
接続構造では、半導体チップ11とフィルム基板21と
を接続した構造となっている。このうち半導体チップ1
1は、チップ本体12上に形成されたパッシベーション
膜13に形成された開口部を介してチップ本体12上に
形成された接続パッド14が露出され、この露出された
接続パッド14上に金属層15が形成され、金属層15
およびその周囲を除くパッシベーション膜13上に表面
が平坦な絶縁膜16が形成された構造となっている。し
たがって、金属層15およびその周囲に対応する部分に
おける絶縁膜16には貫通孔17が形成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an essential part of a connection structure for electronic parts in an embodiment of the present invention. The connection structure of this electronic component has a structure in which the semiconductor chip 11 and the film substrate 21 are connected. Of these, semiconductor chip 1
1 shows that the connection pad 14 formed on the chip body 12 is exposed through the opening formed in the passivation film 13 formed on the chip body 12, and the metal layer 15 is formed on the exposed connection pad 14. And the metal layer 15 is formed.
The insulating film 16 having a flat surface is formed on the passivation film 13 except for the above and surroundings. Therefore, the through hole 17 is formed in the insulating film 16 in the portion corresponding to the metal layer 15 and its periphery.

【0007】フィルム基板21の半導体チップ11の貫
通孔17に対応する部分には貫通孔22が形成されてい
る。フィルム基板21の上面には接着剤23を介して配
線パターンが形成されている。この場合の配線パターン
は、フィルム基板21の上面周囲に形成された接続用の
配線パターン24と、フィルム基板21の上面中央部に
形成された動作試験用の配線パターン25とからなって
いる。そして、フィルム基板21の下面は、その貫通孔
22が半導体チップ11の貫通孔17とそれぞれ対応す
るように位置合わせされた状態で、半導体チップ11の
絶縁膜16の上面に接着剤26を介して固着されてい
る。また、フィルム基板21および半導体チップ11の
貫通孔22、17内およびその近傍にはそれぞれ導電部
材27が設けられ、この導電部材27を介してフィルム
基板21の配線パターン24、25と半導体チップ11
の金属層15とが導電接続されている。
A through hole 22 is formed in a portion of the film substrate 21 corresponding to the through hole 17 of the semiconductor chip 11. A wiring pattern is formed on the upper surface of the film substrate 21 via an adhesive 23. The wiring pattern in this case is composed of a wiring pattern 24 for connection formed around the upper surface of the film substrate 21 and a wiring pattern 25 for operation test formed in the central portion of the upper surface of the film substrate 21. Then, the lower surface of the film substrate 21 is bonded to the upper surface of the insulating film 16 of the semiconductor chip 11 with an adhesive 26 with the through holes 22 aligned with the through holes 17 of the semiconductor chip 11, respectively. It is fixed. Conductive members 27 are provided in the through holes 22 and 17 of the film substrate 21 and the semiconductor chip 11 and in the vicinity thereof, respectively, and the wiring patterns 24 and 25 of the film substrate 21 and the semiconductor chips 11 are provided via the conductive members 27.
Is electrically conductively connected to the metal layer 15.

【0008】次に、半導体チップ11の製造方法につい
て図2(A)〜(E)を順に参照しながら説明する。ま
ず、図2(A)に示すように、チップ本体12上に形成
されたパッシベーション膜13に形成された開口部を介
してチップ本体12上に形成された接続パッド14が露
出され、この露出された接続パッド14上に金属層15
が形成されたものを用意する。この場合の金属層15
は、詳細には図示していないが、図6に示す従来の半導
体チップ4の下地金属層9と同じであって、Alからな
る接続パッド14上に形成されたTi−W合金からなる
下側金属層上にAuからなる上側金属層が形成された構
造となっている。このうち下側金属層は接続パッド14
と上側金属層との密着性を良くするためのものであり、
上側金属層は表面酸化防止のためのものである。
Next, a method of manufacturing the semiconductor chip 11 will be described with reference to FIGS. 2 (A) to 2 (E) in order. First, as shown in FIG. 2A, the connection pad 14 formed on the chip body 12 is exposed through the opening formed in the passivation film 13 formed on the chip body 12, and this exposed portion is exposed. A metal layer 15 on the connection pad 14
Prepare the one in which is formed. Metal layer 15 in this case
Although not shown in detail, the lower side is the same as the base metal layer 9 of the conventional semiconductor chip 4 shown in FIG. 6 and is made of a Ti—W alloy formed on the connection pad 14 made of Al. The structure is such that an upper metal layer made of Au is formed on the metal layer. Of these, the lower metal layer is the connection pad 14
Is to improve the adhesion between the upper metal layer and
The upper metal layer is for preventing surface oxidation.

【0009】次に、図2(B)に示すように、上面全体
にポリイミドからなる絶縁膜16をスピンコート法等の
方法によりその表面が平坦となるように塗布する。この
場合の絶縁膜16の膜厚は5〜10μm程度となるよう
にする。次に、プリベークした後、図2(C)に示すよ
うに、絶縁膜16の上面にネガ型のフォトレジスト層1
8を塗布して形成する。次に、金属層15およびその周
囲に対応する部分に遮光パターンを有するフォトマスク
19を用いて露光する。次に、図2(D)に示すよう
に、現像すると、フォトレジストパターン18aが形成
されるとともに、このときの現像液により絶縁膜16が
フォトレジストパターン18aをマスクとしてエッチン
グされ、金属層15およびその周囲に対応する部分にお
ける絶縁膜16に貫通孔17が形成される。この後、フ
ォトレジストパターン18aを剥離すると、図2(E)
に示すように、金属層15およびその周囲を除くパッシ
ベーション膜13上に表面が平坦な絶縁膜16が形成さ
れたものが得られる。
Next, as shown in FIG. 2B, an insulating film 16 made of polyimide is applied to the entire upper surface by a method such as spin coating so that the surface becomes flat. In this case, the film thickness of the insulating film 16 is about 5 to 10 μm. Next, after prebaking, as shown in FIG. 2C, the negative photoresist layer 1 is formed on the upper surface of the insulating film 16.
8 is applied and formed. Next, exposure is performed using a photomask 19 having a light-shielding pattern on the metal layer 15 and the portion around the metal layer 15. Next, as shown in FIG. 2D, when development is performed, a photoresist pattern 18a is formed, and the insulating film 16 is etched by the developing solution at this time using the photoresist pattern 18a as a mask, and the metal layer 15 and A through hole 17 is formed in the insulating film 16 in the portion corresponding to the periphery thereof. After that, when the photoresist pattern 18a is peeled off, FIG.
As shown in FIG. 7, the insulating film 16 having a flat surface is formed on the passivation film 13 excluding the metal layer 15 and its periphery.

【0010】次に、フィルム基板21の製造方法につい
て図3(A)〜(D)を順に参照しながら説明する。ま
ず、図3(A)に示すように、ポリイミドやPET等か
らなるフィルム基板21の上面に接着剤23を介して配
線パターン24、25形成用の銅箔等からなる金属箔3
1をラミネートする。次に、金属箔31の上面にポジ型
のフォトレジスト層32を塗布して形成する。次に、所
定の遮光パターンを有するフォトマスク33を用いて露
光し、次いで現像すると、図3(B)に示すように、所
定のフォトレジストパターン32aが形成される。次
に、図3(C)に示すように、フォトレジストパターン
32aをマスクとしてエッチングを行うと、所定の配線
パターン24、25が形成される。この後、フォトレジ
ストパターン32aを剥離する。
Next, a method of manufacturing the film substrate 21 will be described with reference to FIGS. 3 (A) to 3 (D) in order. First, as shown in FIG. 3 (A), a metal foil 3 made of copper foil or the like for forming wiring patterns 24, 25 on an upper surface of a film substrate 21 made of polyimide, PET or the like via an adhesive 23.
Laminate 1. Next, a positive photoresist layer 32 is applied and formed on the upper surface of the metal foil 31. Next, by exposing using a photomask 33 having a predetermined light-shielding pattern and then developing, a predetermined photoresist pattern 32a is formed as shown in FIG. 3 (B). Next, as shown in FIG. 3C, etching is performed using the photoresist pattern 32a as a mask to form predetermined wiring patterns 24 and 25. Then, the photoresist pattern 32a is peeled off.

【0011】次に、図3(D)に示すように、フィルム
基板21の所定の複数個所に、つまり図2(E)に示す
半導体チップ11の貫通孔17とそれぞれ対応する部分
に、貫通孔22を形成する。この場合、貫通孔22の形
成方法には、両面にフォトレジストパターンを形成して
ウェットエッチングにより形成する方法があるが、微細
な貫通孔22を形成するには、レーザを用いた形成方法
の方が望ましい。このときの形成方法は、フィルム基板
21における貫通孔22の形成箇所にレーザを照射し、
照射された部分を除去する方法である。また、レーザを
用いた形成方法には、YAGレーザ等を用いた熱分解に
よる形成方法と、エキシマレーザ等を用いた分子結合切
断による形成方法とがあるが、後者の方が加工形状に優
れているので望ましい。かくして、フィルム基板21の
製造が終了する。
Next, as shown in FIG. 3 (D), through holes are formed in a predetermined plurality of locations on the film substrate 21, that is, at portions corresponding to the through holes 17 of the semiconductor chip 11 shown in FIG. 2 (E). 22 is formed. In this case, as a method of forming the through holes 22, there is a method of forming a photoresist pattern on both surfaces and performing wet etching, but for forming the fine through holes 22, a forming method using a laser is more preferable. Is desirable. The forming method at this time is to irradiate a laser on the formation position of the through hole 22 in the film substrate 21,
This is a method of removing the irradiated portion. Further, as a forming method using a laser, there are a forming method by thermal decomposition using a YAG laser or the like and a forming method by cutting a molecular bond using an excimer laser or the like, but the latter is superior in a processed shape. Is desirable. Thus, the manufacturing of the film substrate 21 is completed.

【0012】次に、半導体チップ11とフィルム基板2
1との接続方法を図4(A)〜(C)を順に参照しなが
ら説明する。まず、図4(A)に示すように、フィルム
基板21の下面の所定の個所に熱硬化性樹脂または熱可
塑性樹脂からなる接着剤26をスクリーン印刷等の方法
により塗布して形成する。次に、図4(B)に示すよう
に、半導体チップ11とフィルム基板21との相対応す
る貫通孔17、22の位置合わせを行った状態で、半導
体チップ11の絶縁膜16の表面とフィルム基板21の
下面とを接着剤26を介して接着して固着する。この場
合、絶縁膜16の表面が平坦となっているので、半導体
チップ11とフィルム基板21との固着性を良くするこ
とができる。また、絶縁膜16は、このほかに、半導体
チップ11の表面を保護する役目も備えている。
Next, the semiconductor chip 11 and the film substrate 2
A method of connecting to 1 will be described with reference to FIGS. 4 (A) to 4 (C) in order. First, as shown in FIG. 4A, an adhesive 26 made of a thermosetting resin or a thermoplastic resin is applied to a predetermined portion on the lower surface of the film substrate 21 by a method such as screen printing to form the adhesive 26. Next, as shown in FIG. 4B, with the through holes 17 and 22 corresponding to the semiconductor chip 11 and the film substrate 21 aligned, the surface of the insulating film 16 of the semiconductor chip 11 and the film are aligned. The lower surface of the substrate 21 is adhered and fixed via the adhesive 26. In this case, since the surface of the insulating film 16 is flat, the adhesiveness between the semiconductor chip 11 and the film substrate 21 can be improved. In addition, the insulating film 16 also has a role of protecting the surface of the semiconductor chip 11.

【0013】次に、図4(C)に示すように、フィルム
基板21の配線パターン24、25上にスクリーンマス
ク41を位置合わせして配置する。この場合のスクリー
ンマスク41のパターンは、互いに位置合わせされた貫
通孔22、17に対応する部分に印刷材通過許容部を有
するパターンとなっている。次に、スキージ42で銀ペ
ーストやカーボンペースト等からなる導電性樹脂(導電
部材)27をこすり出し、図1に示すように、互いに位
置合わせされた貫通孔22、17内およびその近傍にそ
れぞれ導電性樹脂27を印刷して設ける。次に、熱処理
を行って導電性樹脂27を硬化させると、この硬化され
た導電性樹脂27を介して半導体チップ11の金属層1
5とフィルム基板21の配線パターン24、25とが導
電接続されることになる。かくして、半導体チップ11
とフィルム基板21とが接続される。
Next, as shown in FIG. 4C, the screen mask 41 is aligned and arranged on the wiring patterns 24 and 25 of the film substrate 21. In this case, the pattern of the screen mask 41 is a pattern having a printing material passage permitting portion at portions corresponding to the through holes 22 and 17 aligned with each other. Next, a conductive resin (conductive member) 27 made of silver paste, carbon paste, or the like is rubbed out with a squeegee 42, and as shown in FIG. The resin 27 is provided by printing. Next, when heat treatment is performed to cure the conductive resin 27, the metal layer 1 of the semiconductor chip 11 is interposed via the cured conductive resin 27.
5 and the wiring patterns 24 and 25 of the film substrate 21 are conductively connected. Thus, the semiconductor chip 11
And the film substrate 21 are connected.

【0014】このようにして得られた電子部品の接続構
造では、フィルム基板21および半導体チップ11の貫
通孔22、17内およびその近傍に導電性樹脂27をス
クリーン印刷により塗布して設けるだけで、この設けら
れた導電性樹脂27を介して半導体チップ11の接続パ
ッド14およびその上の金属層15からなる接続電極と
フィルム基板21の配線パターン24、25とを導電接
続することができる。したがって、従来のようにバンプ
形成工程と熱圧着工程とが別々である場合と比較して、
少ない工程数で接続することができ、生産性が向上し、
コストダウンを図ることができる。また、熱圧着によら
ないで接続することができるので、半導体チップ11の
ダメージが小さく、接続工程で不良品が発生しにくいよ
うにすることができる。また、熱圧着の場合には、かな
りの高温(230〜310℃程度)に加熱するので、フ
ィルム基板21の材料として耐熱性の低いものを使用す
ることができないが、この実施例の場合、耐熱性の低い
ものでも使用することができる。また、図6に示すTA
Bテープの場合には、熱圧着ヘッドの熱圧着面の平面度
等を考慮すると、半導体チップ4の大型化に容易に対応
することができないが、この実施例の場合、導電性樹脂
27をスクリーン印刷により形成すればよいので、半導
体チップ11の大型化にも容易に対応することができ
る。さらに、図6に示すTABテープの場合には、一般
に、信頼性の向上を図るために、半導体チップ4および
フィンガリード3の部分を封止樹脂で封止しているの
で、工程数が増えるが、この実施例の場合、そのような
必要はない。
In the electronic component connection structure thus obtained, the conductive resin 27 is applied by screen printing to the insides of the through holes 22 and 17 of the film substrate 21 and the semiconductor chip 11 and their vicinity. Through the conductive resin 27 thus provided, the connection electrodes composed of the connection pads 14 of the semiconductor chip 11 and the metal layer 15 thereon can be conductively connected to the wiring patterns 24 and 25 of the film substrate 21. Therefore, compared with the conventional case where the bump forming process and the thermocompression bonding process are separate,
You can connect with a small number of processes, productivity is improved,
Cost can be reduced. In addition, since the connection can be made without using thermocompression bonding, the semiconductor chip 11 is less damaged, and defective products are less likely to occur in the connection process. Further, in the case of thermocompression bonding, since the film substrate 21 is heated to a considerably high temperature (about 230 to 310 ° C.), a material having low heat resistance cannot be used. It can be used even if it has low properties. Also, the TA shown in FIG.
In the case of the B tape, in consideration of the flatness of the thermocompression bonding surface of the thermocompression bonding head, it is not possible to easily cope with an increase in the size of the semiconductor chip 4, but in the case of this embodiment, the conductive resin 27 is used as a screen. Since it may be formed by printing, it is possible to easily cope with an increase in the size of the semiconductor chip 11. Further, in the case of the TAB tape shown in FIG. 6, generally, in order to improve reliability, the semiconductor chip 4 and the finger leads 3 are sealed with a sealing resin, so that the number of steps is increased. In the case of this embodiment, there is no such need.

【0015】次に、完成後の動作試験の結果半導体チッ
プ11が不良品と判定され、あるいは導電性樹脂27を
介した導電接続が不良と判定され、別の半導体チップ1
1と交換する場合について説明する。まず、動作試験を
行う場合には、図示していないが、試験装置と電気的に
接続するためのプローブをフィルム基板21の試験用の
配線パターン25に接触させると、接続用の配線パター
ン24の表面に傷が付かないようにすることができる。
次に、半導体チップ11の交換を行う場合には、導電性
樹脂27が銀ペーストやカーボンペースト等からなって
いるので、イソプロピレンアルコールやアセトン等の有
機溶剤を用いると、導電性樹脂27を溶かすことができ
る。また、接着剤26として熱可塑性樹脂を用いると、
熱処理により接着剤26を軟化させることができる。し
たがって、不良品の半導体チップ11をフィルム基板2
1から容易に分離することができる。次に、必要に応じ
て、上記と同じ有機溶剤を用いてフィルム基板21を洗
浄し、フィルム基板21上に残った導電性樹脂27を完
全に除去する。次に、別の半導体チップ11を上記の場
合と同様の接続工程を経てフィルム基板21に接続する
と、一般に良品であるフィルム基板21を容易に再利用
することができる。
Next, as a result of the operation test after completion, the semiconductor chip 11 is determined to be defective, or the conductive connection via the conductive resin 27 is determined to be defective, and another semiconductor chip 1 is determined.
The case of exchanging with 1 will be described. First, in the case of performing an operation test, although not shown, a probe for electrically connecting to a test device is brought into contact with the test wiring pattern 25 of the film substrate 21, and the wiring pattern 24 for connection is The surface can be protected from scratches.
Next, when the semiconductor chip 11 is replaced, the conductive resin 27 is made of silver paste, carbon paste, or the like. Therefore, if an organic solvent such as isopropylene alcohol or acetone is used, the conductive resin 27 is dissolved. be able to. Further, if a thermoplastic resin is used as the adhesive 26,
The heat treatment can soften the adhesive 26. Therefore, the defective semiconductor chip 11 is replaced by the film substrate 2.
It can be easily separated from 1. Next, if necessary, the film substrate 21 is washed with the same organic solvent as described above to completely remove the conductive resin 27 remaining on the film substrate 21. Next, another semiconductor chip 11 is connected to the film substrate 21 through the same connection process as in the above case, so that the generally good film substrate 21 can be easily reused.

【0016】次に、図5はこの発明の他の実施例におけ
る電子部品の接続構造の要部を示したものである。この
図において、図1と同一名称部分には同一の符号を付
し、その説明を適宜省略する。この実施例の半導体チッ
プ11は、第1の接続パッド14およびパッシベーショ
ン膜13の上面全体に第1の層間絶縁膜51が形成さ
れ、第1の層間絶縁膜51の上面に中継用の配線パター
ン52が第1の層間絶縁膜51に形成された開口部を介
して接続パッド14に接続されて形成され、中継用の配
線パターン52および第1の層間絶縁膜51の上面全体
に第2の層間絶縁膜53が形成され、第2の層間絶縁膜
53の上面に第2の接続パッド54が第2の層間絶縁膜
53に形成された開口部を介して中継用の配線パターン
52に接続されて形成された構造となっている。この場
合、第1の接続パッド14は平面方形状のチップ本体1
2の上面の4辺に沿って配置され、第2の接続パッド5
4は第1の接続パッド14の配置位置とは少なくとも一
部で異なる位置に配置されている。一方、フィルム基板
21の半導体チップ11の第2の接続パッド54および
その近傍に対応する部分には貫通孔22が形成されてい
る。
Next, FIG. 5 shows an essential part of a connecting structure for electronic parts in another embodiment of the present invention. In this figure, the same reference numerals are given to the same names as those in FIG. 1, and the description thereof will be omitted as appropriate. In the semiconductor chip 11 of this embodiment, a first interlayer insulating film 51 is formed on the entire upper surfaces of the first connection pad 14 and the passivation film 13, and a wiring pattern 52 for relaying is formed on the upper surface of the first interlayer insulating film 51. Is formed by being connected to the connection pad 14 through the opening formed in the first interlayer insulating film 51, and the second interlayer insulating film is formed on the entire upper surfaces of the relay wiring pattern 52 and the first interlayer insulating film 51. The film 53 is formed, and the second connection pad 54 is formed on the upper surface of the second interlayer insulating film 53 by being connected to the relay wiring pattern 52 through the opening formed in the second interlayer insulating film 53. It has a structured structure. In this case, the first connection pad 14 is the planar chip body 1
The second connection pad 5 arranged along the four sides of the upper surface of
4 is arranged at a position different from at least the position where the first connection pad 14 is arranged. On the other hand, the through hole 22 is formed in the portion of the film substrate 21 corresponding to the second connection pad 54 of the semiconductor chip 11 and its vicinity.

【0017】そして、フィルム基板21の下面と半導体
チップ11の第2の層間絶縁膜53の上面とは接着剤2
6を介して接着されて固着され、フィルム基板21の貫
通孔22内およびその近傍に設けられた導電性樹脂27
を介してフィルム基板21の接続用の配線パターン24
と半導体チップ11の第2の接続パッド54とが導電接
続されている。このようにした場合には、半導体チップ
11の構造が、チップ本体12の上面に設けられた第1
の接続パッド14の配置位置とは少なくとも一部で異な
る位置に第2の接続パッド54を相対応する第1の接続
パッド14とそれぞれ接続させて設けた構造であるの
で、第2の接続パッド54の配置位置を比較的自由に選
定することができ、ひいては多ピン化してもフィルム基
板21の配線パターン24の配置位置にあまり制約を受
けず、したがって多ピン化に無理なく対応することがで
きる。
The lower surface of the film substrate 21 and the upper surface of the second interlayer insulating film 53 of the semiconductor chip 11 are bonded to each other by the adhesive 2
Conductive resin 27 provided inside and in the vicinity of the through hole 22 of the film substrate 21 by being adhered and fixed via 6
Wiring pattern 24 for connection of the film substrate 21 via
And the second connection pad 54 of the semiconductor chip 11 are conductively connected. In this case, the structure of the semiconductor chip 11 is the same as that of the first chip provided on the upper surface of the chip body 12.
Since the second connection pad 54 is connected to the corresponding first connection pad 14 at a position different from at least the position where the connection pad 14 is arranged, the second connection pad 54 Can be relatively freely selected, and even if the number of pins is increased, the position of the wiring pattern 24 on the film substrate 21 is not restricted so much, and thus the number of pins can be coped with without difficulty.

【0018】[0018]

【発明の効果】以上説明したように、この発明によれ
ば、基板の貫通孔内およびその近傍に導電部材を例えば
スクリーン印刷により塗布して設けると、この設けられ
た導電部材を介して電子部品の接続電極と基板の配線パ
ターンとを導電接続することができるので、少ない工程
数で接続することができ、生産性が向上し、コストダウ
ンを図ることができる。また、熱圧着によらないで接続
することができるので、電子部品のダメージが小さく、
接続工程で不良品が発生しにくいようにすることができ
る。さらに、導電性樹脂からなる導電部材による導電接
続である場合には、完成後に電子部品と基板とを容易に
分離することができ、したがって完成後に電子部品の交
換を行う場合、容易に交換することができる。また、請
求項3記載の発明によれば、半導体チップ等からなる電
子部品の構造が、一の面に設けられた第1の接続電極の
配置位置とは少なくとも一部で異なる位置に第2の接続
電極を相対応する第1の接続端子とそれぞれ接続させて
設けた構造であるので、第2の接続電極の配置位置を比
較的自由に選定することができ、ひいては多ピン化して
も基板の配線パターンの配置位置にあまり制約を受け
ず、したがって多ピン化に無理なく対応することができ
る。
As described above, according to the present invention, when a conductive member is applied in the through hole of the substrate and in the vicinity thereof by screen printing, for example, an electronic component is provided through the provided conductive member. Since the connection electrode and the wiring pattern of the substrate can be conductively connected, the connection can be performed in a small number of steps, the productivity can be improved, and the cost can be reduced. Also, since the connection can be made without using thermocompression bonding, the damage to electronic parts is small,
It is possible to prevent defective products from occurring in the connection process. Further, when the conductive connection is made by the conductive member made of a conductive resin, the electronic component and the substrate can be easily separated after completion, and therefore, when the electronic component is replaced after completion, the electronic component can be easily replaced. You can According to the third aspect of the invention, the structure of the electronic component including the semiconductor chip and the like is arranged at a position different from at least a part of the position of the first connection electrode provided on the one surface in the second structure. Since the structure is such that the connection electrodes are connected to the corresponding first connection terminals respectively, the arrangement position of the second connection electrodes can be selected relatively freely, and even if the number of pins is increased, the board The arrangement position of the wiring pattern is not so restricted, so that it is possible to cope with the increase in the number of pins without difficulty.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例における電子部品の接続構
造の要部を示す断面図。
FIG. 1 is a cross-sectional view showing a main part of a connection structure for electronic components according to an embodiment of the present invention.

【図2】(A)〜(E)はそれぞれ半導体チップの各製
造工程を示す断面図。
2A to 2E are cross-sectional views showing respective manufacturing steps of a semiconductor chip.

【図3】(A)〜(D)はそれぞれフィルム基板の各製
造工程を示す断面図。
3A to 3D are cross-sectional views showing respective manufacturing steps of the film substrate.

【図4】(A)〜(C)はそれぞれ半導体チップとフィ
ルム基板との各接続工程を示す断面図。
4A to 4C are cross-sectional views showing respective connecting steps of the semiconductor chip and the film substrate.

【図5】この発明の他の実施例における電子部品の接続
構造の要部を示す断面図。
FIG. 5 is a sectional view showing an essential part of a connection structure for an electronic component according to another embodiment of the present invention.

【図6】従来の電子部品の接続構造の一例として示すT
ABテープの断面図。
FIG. 6 shows T as an example of a conventional connection structure for electronic components.
Sectional drawing of AB tape.

【符号の説明】[Explanation of symbols]

11 半導体チップ 14 接続パッド 15 金属層 16 絶縁膜 17 貫通孔 21 フィルム基板 22 貫通孔 24、25 配線パターン 26 接着剤 27 導電性樹脂(導電部材) 11 Semiconductor Chip 14 Connection Pad 15 Metal Layer 16 Insulating Film 17 Through Hole 21 Film Substrate 22 Through Hole 24, 25 Wiring Pattern 26 Adhesive 27 Conductive Resin (Conductive Member)

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 一の面に複数の接続電極を有する電子部
品と、 一の面に配線パターンを有するとともに、前記電子部品
の接続電極とそれぞれ対応する部分に貫通孔を有する基
板と、 前記基板の貫通孔内およびその近傍にそれぞれ設けられ
た導電部材とからなり、 前記電子部品が前記基板の一の面に対して反対側の面に
固着されているとともに、前記導電部材を介して前記電
子部品の接続電極と前記基板の配線パターンとが導電接
続されていることを特徴とする電子部品の接続構造。
1. An electronic component having a plurality of connection electrodes on one surface, a substrate having a wiring pattern on the one surface, and a through hole at a portion corresponding to each of the connection electrodes of the electronic component, And a conductive member provided inside and in the vicinity of the through hole of the electronic component, and the electronic component is fixed to a surface opposite to the one surface of the substrate, and the electronic component is provided through the conductive member. A connection structure for an electronic component, wherein a connection electrode of the component and a wiring pattern of the substrate are conductively connected.
【請求項2】 前記電子部品の接続電極を除く一の面に
表面が平坦な絶縁膜を設け、この絶縁膜の表面に前記基
板を固着したことを特徴とする請求項1記載の電子部品
の接続構造。
2. The electronic component according to claim 1, wherein an insulating film having a flat surface is provided on one surface of the electronic component excluding the connection electrode, and the substrate is fixed to the surface of the insulating film. Connection structure.
【請求項3】 一の面に複数の第1の接続電極が設けら
れ、その上に層間絶縁膜が設けられ、その上であって前
記第1の接続電極の配置位置とは少なくとも一部で異な
る位置に第2の接続電極が相対応する前記第1の接続端
子とそれぞれ接続されて設けられた電子部品と、 一の面に配線パターンを有するとともに、前記電子部品
の第2の接続電極とそれぞれ対応する部分に貫通孔を有
する基板と、 前記基板の貫通孔内およびその近傍にそれぞれ設けられ
た導電部材とからなり、 前記電子部品が前記基板の一の面に対して反対側の面に
固着されているとともに、前記導電部材を介して前記電
子部品の第2の接続電極と前記基板の配線パターンとが
導電接続されていることを特徴とする電子部品の接続構
造。
3. A plurality of first connection electrodes are provided on one surface, an interlayer insulating film is provided on the first connection electrodes, and at least a part of the position is the arrangement position of the first connection electrodes. An electronic component having second connection electrodes connected to different corresponding first connection terminals at different positions, and a second connection electrode of the electronic component having a wiring pattern on one surface. A substrate having through holes in corresponding portions, and a conductive member provided in the through holes of the substrate and in the vicinity thereof, respectively, the electronic component on the surface opposite to one surface of the substrate. A connection structure for an electronic component, wherein the second connection electrode of the electronic component and the wiring pattern of the substrate are conductively connected to each other via the conductive member.
【請求項4】 前記電子部品は半導体チップからなり、
前記基板はフィルム基板からなることを特徴とする請求
項1〜3のいずれかに記載の電子部品の接続構造。
4. The electronic component comprises a semiconductor chip,
The connection structure for electronic components according to claim 1, wherein the substrate is a film substrate.
【請求項5】 請求項1〜4のいずれかに記載の電子部
品の接続構造の接続に際し、前記電子部品と前記基板と
を固着した後、前記基板の貫通孔内およびその近傍に前
記導電部材をスクリーン印刷により塗布して設けること
を特徴とする電子部品の接続方法。
5. When connecting the electronic component connection structure according to claim 1, after the electronic component and the substrate are fixed, the conductive member is provided in the through hole of the substrate and in the vicinity thereof. A method for connecting electronic components, wherein the method is applied by screen printing.
JP6156401A 1994-06-16 1994-06-16 Structure for connecting electronic parts and connection method therefor Pending JPH088293A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6156401A JPH088293A (en) 1994-06-16 1994-06-16 Structure for connecting electronic parts and connection method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6156401A JPH088293A (en) 1994-06-16 1994-06-16 Structure for connecting electronic parts and connection method therefor

Publications (1)

Publication Number Publication Date
JPH088293A true JPH088293A (en) 1996-01-12

Family

ID=15626938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6156401A Pending JPH088293A (en) 1994-06-16 1994-06-16 Structure for connecting electronic parts and connection method therefor

Country Status (1)

Country Link
JP (1) JPH088293A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037665A (en) * 1997-03-03 2000-03-14 Nec Corporation Mounting assembly of integrated circuit device and method for production thereof
EP1094518A1 (en) * 1999-09-30 2001-04-25 Ming-Tung Shen Semiconductor device comprising a lead frame and method for fabricating the same
WO2001071773A2 (en) * 2000-03-23 2001-09-27 Infineon Technologies Ag Method and device for connecting at least one chip to a rewiring arrangement
US6414382B1 (en) 1997-01-23 2002-07-02 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device and method of manufacturing the same, mounted board, and electronic instrument
JP2002231762A (en) * 2001-02-01 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip and ic chip mounting body
WO2005117096A1 (en) * 2004-05-31 2005-12-08 Sharp Takaya Electronics Industry Co., Ltd. Circuit module manufacturing method and circuit module manufactured by the method
DE102010016517B4 (en) * 2009-04-30 2015-03-05 Infineon Technologies Ag Semiconductor device
CN110349931A (en) * 2018-04-08 2019-10-18 华为技术有限公司 Encapsulating structure, electronic device and packaging method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6414382B1 (en) 1997-01-23 2002-07-02 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device and method of manufacturing the same, mounted board, and electronic instrument
US6037665A (en) * 1997-03-03 2000-03-14 Nec Corporation Mounting assembly of integrated circuit device and method for production thereof
US6297141B1 (en) 1997-03-03 2001-10-02 Nec Corporation Mounting assembly of integrated circuit device and method for production thereof
EP1094518A1 (en) * 1999-09-30 2001-04-25 Ming-Tung Shen Semiconductor device comprising a lead frame and method for fabricating the same
WO2001071773A2 (en) * 2000-03-23 2001-09-27 Infineon Technologies Ag Method and device for connecting at least one chip to a rewiring arrangement
WO2001071773A3 (en) * 2000-03-23 2002-04-11 Infineon Technologies Ag Method and device for connecting at least one chip to a rewiring arrangement
US7036216B2 (en) 2000-03-23 2006-05-02 Infineon Technologies Ag Method and apparatus for connecting at least one chip to an external wiring configuration
JP2002231762A (en) * 2001-02-01 2002-08-16 Toppan Forms Co Ltd Mounting method for ic chip and ic chip mounting body
WO2005117096A1 (en) * 2004-05-31 2005-12-08 Sharp Takaya Electronics Industry Co., Ltd. Circuit module manufacturing method and circuit module manufactured by the method
DE102010016517B4 (en) * 2009-04-30 2015-03-05 Infineon Technologies Ag Semiconductor device
CN110349931A (en) * 2018-04-08 2019-10-18 华为技术有限公司 Encapsulating structure, electronic device and packaging method

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