JP2003332491A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a cost and improve a reliability and electric characteristics of a semiconductor device wherein external terminal sections are arranged like a lattice on a plane. <P>SOLUTION: The semiconductor device comprises a semiconductor chip 61; a lead 62 which comprises a lead section 66 electrically connected to the semiconductor chip 61 and extended in the outward direction of the semiconductor chip 61, and an external connection terminal section 67 integrally connected to the lead section 66 and extended downwards nearly in the vertical direction with respect to the lead section 66; sealing resin 63 which seals the semiconductor chip 61 and the lead section 66, with a bottom face of the semiconductor chip 61 and a bottom face of the lead section 66 being exposed; and an insulation member 65 which covers at least the bottom face of the semiconductor chip 61 and the bottom face of the lead section 66, and through which the external connection terminal sections 67 is extended. The external connection terminal section 67 comprises a columnar terminal section 68 which is partially embedded in the insulation member 65 and projects from a bottom face of the insulation member 65, and a terminal end 69 which has a multilayer structure with an inner layer and an outer layer being formed of different metals. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having external terminals arranged in a lattice on a plane.

In recent years, electronic devices have become smaller, thinner, and faster,
As the need for higher functionality increases, semiconductor devices, which are one of the main components, are also required to have smaller size, higher density, and higher functionality. Therefore, the external shape of the semiconductor device is QFP (Quad Flat Package) or QTP (Quad Tape-carr).
ier Package) to BGA (Ball Grid Array), TAB
(Tape Automated Bonding) The technology is shifting to mini or micro (μ) BGA using connection technology.

Therefore, it is desired to improve the reliability and electrical characteristics of the semiconductor device due to its small size.

[0004]

2. Description of the Related Art FIG. 33 is a block diagram of a conventional semiconductor device of a μBGA package. 33A is a cross-sectional view and FIG. 33B is a plan view.

A semiconductor device 1 shown in FIGS. 33A and 33B.
In No. 1, a predetermined number of pads 13 are formed on the semiconductor chip 12, and an elastic adhesive 14 is formed on a portion other than the pads 13 of the semiconductor chip 12. A frame portion 16 made of metal or the like for protection or heat dissipation is attached to the peripheral side surface of the semiconductor chip 12 by an adhesive agent 15a, and an adhesive agent 15b is also formed on the frame portion 16.

On the other hand, a copper foil pattern 18 is attached on a resin film 17 such as polyimide (PI). The pattern 18 is composed of an external pad 18a and a lead 18b extending from the external pad 18a and TC ( Tape Car
rier) is configured. In addition, holes 19 are formed in the resin film 17 at portions corresponding to the external pads 18, and gold or solder ball electrodes 20 that are in contact with the external pads 18a are formed in the holes 19 in a grid array. For example,
The pitch of the ball electrodes 20 is arranged at 0.5 mm. The ball electrode 20 serves as an external terminal.

This resin film 17 is the above-mentioned adhesive 1
It is mounted on 4, 15b. Then, the leads 18 b extending from the pattern 18 and the pads 1 of the semiconductor chip 12 are formed.
3 is connected by fusion or the like, and this portion is sealed with a resin 15c such as epoxy.

As described above, the semiconductor device 11 is formed in the μBGA package structure including the ball electrode 20 having a size close to the chip size.

The plane size of the semiconductor device 11 is determined by the size of the semiconductor chip 12, the number of terminals, and the terminal pitch.

That is, when the area determined by the number of terminals and the terminal pitch does not exceed the area of the semiconductor chip 12, the pads 13 formed on the semiconductor chip 12 are arranged outside the lattice-arranged external terminals. Therefore, the plane size of the semiconductor device 11 is determined.

When the area determined by the number of terminals and the terminal pitch exceeds the area of the semiconductor chip 12, the pad 13 is not necessarily located outside the external terminals, but the area of the external ends arranged in a lattice arrangement causes the semiconductor device. 11 plane sizes are determined.

[0012]

However, the semiconductor device 11 as described above has a problem that the semiconductor chip 12 and the external terminal are connected by the TAB technique, and therefore the products are not uniform and have no versatility. .

Further, to concentrate all the external terminals on the semiconductor chip 12, for example, when the pitch of the pads 13 is 80 μm or less and the number of terminals is 324 or more, the pitch of the external terminals is 0.4 mm or less. It is necessary and difficult to implement. On the other hand, if the external terminal pitch is 0.5 mm or more, it is necessary to increase the size of the semiconductor chip 12, which causes a problem of increasing the total cost.

Further, since the plating process is performed in the formation of the external terminals (bump electrodes 20), there is a problem that the cost is increased. In addition, there is a problem in that a part of the semiconductor chip 12 is exposed and reliability is lowered.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of reducing cost and improving reliability and electrical characteristics.

[0016]

In order to solve the above problems, the present invention is characterized by taking the following means.

According to a first aspect of the present invention, a semiconductor chip, a lead portion electrically connected to the semiconductor chip and extending in an outer direction of the semiconductor chip, and a lead portion integrally connected to the lead portion are provided. A lead body composed of an external connection terminal portion extending downward at substantially right angles to the lead portion, and the semiconductor chip and the lead portion sealed with the lower surface of the semiconductor chip and the lower surface of the lead portion exposed. A sealing resin for stopping, and an insulating member which covers at least the lower surface of the semiconductor chip and the lower surface of the lead portion and is arranged in a state where the external connection terminal portion is penetrated are provided, and the external connection A terminal has a columnar terminal portion partially embedded in the insulating member and protruding from a lower surface of the insulating member, and a plurality of laminated structures, and an inner layer and an outer layer thereof are different from each other. It is characterized in being constituted by a terminal end configured by.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the external connection terminal portion forming the lead body is formed on the columnar terminal portion and the lower end portion of the columnar terminal portion. And a terminal end portion, and the lead portion and the terminal end portion are made of a material having a resist action with respect to the material of the columnar terminal portion.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the lead portion is made of a nickel (Ni) layer, an aluminum (Al) layer, or a titanium (Ti) layer and a gold layer above the lead layer. (Au) layer, silver (Ag) layer, or palladium (Pd) layer is formed, and the columnar terminal portion is formed of copper (Cu), and At the terminal end portion, a gold (Au) layer, a silver (Ag) layer, or a palladium (Pd) layer is formed below a nickel (Ni) layer, an aluminum (Al) layer, or a titanium (Ti) layer. It is characterized by being configured.

According to a fourth aspect of the invention, in the semiconductor device according to any one of the first to third aspects, a second insulating member is interposed between the semiconductor chip and the insulating member. It is characterized by.

According to a fifth aspect of the invention, in the semiconductor device according to the fourth aspect, the external connection terminal portion is the inner peripheral portion of the semiconductor chip, or both the inner peripheral portion and the outer peripheral portion of the semiconductor chip. It is characterized in that it is arranged in.

Each of the above means operates as follows.

According to the first aspect of the present invention, the lead body is composed of a lead portion extending outward of the semiconductor chip and an external connection terminal portion extending downward substantially at right angles to the lead portion. There is. Therefore, the arrangement position of the external connection terminal portion is determined by the extension length of the lead portion, but the extension length of the lead portion can be set with a degree of freedom. Therefore, the arrangement position of the external connection terminal portion can be set without being restricted by the size of the semiconductor chip, and the versatility is improved. Further, since the lead portion and the external connection terminal portion are integrally formed, it is not necessary to form a via hole or lay out a wiring to electrically connect the lead portion and the external connection terminal portion, The cost of the semiconductor device can be reduced.

Further, in the inventions according to claims 2 and 3, the external connection terminal portion constituting the lead body is constituted by the columnar terminal portion and the terminal end portion, and the material of the lead portion and the terminal end portion is made of the columnar terminal portion. The columnar terminal portion can be formed using the lead portion and the terminal end portion as the resist by forming the material having the resist action with respect to the material. Therefore, the columnar terminal portions can be formed easily and inexpensively as compared with the configuration in which the resist material is separately provided for forming the columnar terminal portions.

According to the invention of claim 4, the second insulating member is interposed between the semiconductor chip and the insulating member, so that the external connection terminal portion or the semiconductor chip is provided below the second insulating member. It becomes possible to arrange a cooling member.

According to the invention of claim 5, the external connection terminal portion is arranged at the inner peripheral portion of the semiconductor chip, or at both the inner peripheral portion and the outer peripheral portion of the semiconductor chip. It becomes possible to arrange in a high density.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of the first embodiment of the present invention. FIG. 1A is an overall perspective view from the separation surface, and FIG. 1B is a sectional view thereof.

A semiconductor device 21 shown in FIGS. 1A and 1B.
1A, the package 22 includes a resin region 23 formed of a molding resin and a terminal region 24. The terminal region 24 is composed of a pattern portion 25 formed of a flexible PWB (print wiring board) and an external terminal portion 26.

The external terminal portion 26 is formed of a metal conductor such as copper, has a frame-shaped terminal portion 27 formed on the outer side in a plane, and is insulated by a resin 23a in the inner region of the frame-shaped terminal portion 27. A predetermined number (for example, 324) of columnar terminal portions 28 are arranged in a grid pattern. The frame-shaped terminal portion 27 serves as a base for wire bonding, which will be described later, and
Noise resistance can be improved by providing a function as a power source pattern or a ground pattern.

In FIG. 1B, the pattern portion 25 is
An insulating film or a base layer 31 of a metal frame and a pattern layer 32 formed of a copper foil or the like are formed with an epoxy insulating layer 33 interposed, for example, and a semiconductor chip 41 is silver paste or the like in the central portion of the base layer 31. It is mounted by the adhesive 42. In the pattern layer 32, a terminal connecting portion 32a and a wire connecting portion 32b corresponding to the columnar terminal portion 28 are formed, respectively.

Openings 34 are formed in the base layer 31 around the outer periphery of the semiconductor chip 41 to show the wire connection portions of the pattern layer 32, and the pads and wires 43 formed on the outer peripheral side of the semiconductor chip 41. Are electrically connected to each other (described in FIG. 2).

Then, the pattern layer 32 of the pattern portion 25
And the external terminal portion 26 (frame-shaped terminal portion 27) of the terminal region 24 are fixed to each other with an epoxy adhesive or an insulating layer 35 of an insulating film interposed therebetween. At this time, the terminal connecting portion 32 a of the pattern layer 32 and the columnar terminal portion 28 of the external terminal portion 26 are in a contact state and electrically connected by the plating 36. The exposed external terminal portion 2
The surfaces of the frame-shaped terminal portion 27 and the columnar terminal portion 28 of No. 6 are subjected to a predetermined plating treatment (described later). Here, FIG. 2 shows an explanatory view of the partial cutting of FIG. 2A is a partially cutaway perspective view, and FIG. 2A is an enlarged view of a wire bonding portion.

In FIG. 2A, as described in FIG. 1, the semiconductor chip 41 is formed in the central portion of the base layer 31.
Is mounted, and is electrically connected to the wire connecting portion 32b of the pattern layer 32, which is exposed from the opening 34, and the wire 43 in the periphery thereof.

As shown in FIG. 2B, the semiconductor chip 4
Pads 41a are formed on the upper surface of the base layer 1 in two rows at the same position with respect to the opening 34 of the base layer 31. In addition, the wire connecting portion 32 of the pattern layer 32 that is exposed from the opening 34
The ends of b are sized and arranged in a staggered pattern for wire bonding.

Then, the pad 41a near the opening 34
And the wire connecting portion 32b near the semiconductor chip 41 are electrically connected by the wire 43a. Further, the pad 41a farther from the opening 34 and the wire connecting portion 32b farther from the semiconductor chip 41 are connected to the wire 43a by the wire 43b.
The electrical connection is made by a shape loop having a height higher than that of the loop. As a result, contact between the wires 43a and 43b is prevented, and the wiring density can be improved.

Next, FIG. 3 shows a manufacturing process diagram for forming the pattern portion shown in FIG. 3A shows the case where the base of the pattern portion 25 is an insulating film (PI), and FIG. 3B shows the case where it is a metal frame (copper-based or tin-nickel-based).

In FIG. 3A, first, a polyimide (PI) film to be the base layer 31 is prepared (step (S) 1), and an opening 34 for representing the wire connecting portion 32b is punched by a press. (S
2).

Subsequently, for example, an epoxy-based insulating adhesive (which becomes the insulating layer 33) is applied onto the PI film (S3), and a copper foil which becomes the pattern layer 32 is attached (S).
4). After that, a predetermined resist is applied to the copper foil-attached surface (S5), exposure for forming a predetermined pattern is performed (S6), and after the exposure, etching that is chemical polishing of the exposed surface (one side) is performed (S7). ), And then the resist is stripped (S
8).

As a result, the wire connection portion 32b of the pattern layer 32 is exposed from the opening 34 of the base layer 31, and the plating process (gold, silver or palladium) for wire bonding is performed there. (S
9).

On the other hand, in FIG. 3B, the base layer 31
In the case of forming the metal frame with a metal frame, first, a copper-based or iron-nickel-based metal frame is prepared (S11), and the opening 34 for representing the wire connection portion 32b is formed by pressing or etching (S12). ). Here, when the base is a copper base, SnNi plating is performed on the base (S13a).

After the opening 34 is formed or after the copper-based base is plated, an epoxy-based insulating adhesive that becomes the insulating layer 33 is applied (S13), and the copper foil that becomes the pattern layer 32 is attached. It is worn (S14). Then, a resist corresponding to a predetermined pattern is applied to the copper foil sticking surface (S15), and exposure for pattern formation is performed (S16).

After the exposure, the exposed surface (one surface) is etched (S17), and the resist which is not etched is removed (S18). Then, the base layer 31
The plating process (gold, silver, or palladium) for wire bonding is performed on the wire connecting portion 32b of the pattern layer 32, which is exposed from the opening 34 of S1 (S1).
9).

Next, FIG. 4 shows a manufacturing process drawing of the external terminal portion of FIG. FIG. 4 shows a case where the external terminal portion is formed by etching. In FIG. 4, first, for example, a copper plate is prepared (S21), a resist is applied on the connection surface with the pattern portion 25 in a pattern for forming the frame-shaped terminal portion 27 and the columnar terminal portion 28 (S22), and the pattern portion is formed. A resist is applied to the entire back surface of the connection surface (S2
3).

Then, double-sided etching is performed (S2
4) After the etching, the resist on both sides is stripped (S2
5). In this case, the pattern-surface connecting surface is so-called half-etched so that the frame-shaped terminal portion 27 and the columnar terminal portion 28 are thinly connected.

Here, FIG. 5 shows a manufacturing explanatory view of post-processing of the external terminal portion of FIG. 6 is a manufacturing explanatory view of another shape of the external terminal portion of FIG.

In FIG. 5A, the external terminal portion 26 formed according to FIG. 4 has a columnar terminal portion 28 on the connection surface of the pattern portion.
Projections 28a are formed, and the opposite surface has a planar shape that is not etched.

The external terminal portion 26 of the press 51 constituted by the punch 51a and the die 51b has a flat punch 51a as its pattern connecting surface, and a projection 28 on the opposite surface.
It is positioned so as to be on the side of the die 51b on which the protrusion 51b1 corresponding to the valley portion is formed.

Then, as shown in FIG. 5B, the columnar terminal portion 28 is formed by the stamping of the press 51 so that the columnar terminal portion 28 is also projected on the opposite surface. A thin portion 29 is interposed between the adjacent columnar terminal portions 28, and the columnar terminal portions 28 are connected by the thin portion 29.

Further, in FIG. 6A, a copper plate 26a is prepared instead of the external terminal portion 26 having the protrusion 28a as shown in FIG. 5A, and the protrusions 51a ₁ and 51b _{2 are also provided.}
Are located between the punch 51a and the die 51b formed to face each other.

Then, the columnar terminal portions 28 are formed on both surfaces of the external terminal portion 26 by the stamping of the press 51, as shown in FIG. 6B. In this case, either surface may be the connection surface of the pattern portion. Further, the stamping of the press 51 allows the thin portion 29
Are also formed collectively.

7 to 9 are manufacturing explanatory views of other shapes of the external terminal portion of FIG.

In FIG. 7A, two metal conductor plates (for example, copper alloy) are used, and the metal conductor plate 26 has a predetermined number of recesses 26b ₃ formed by half etching.
b ₁ and 26 b ₂ are formed.

As shown in FIG. 7B, these are attached to the surface of the metal conductor plate 26b _{1 where} the recess 26b ₃ is not formed,
The surfaces of the metal conductor plate 26b _{2 on which} the recesses 26b ₃ are formed are superposed and joined by ultrasonic waves or the like to form the external terminal portion 26.
Is formed.

[0055] The external terminal portion 26, by etching after sealed with resin to expose the surface of the recess 26b ₃ are not formed, FIG. 11 (B) frame-like terminal portion 27 and as shown in the later The columnar terminal portion 28 is formed in a thin connection state.

Further, the above-mentioned FIG. 7A shown in FIG.
As shown in FIG. 8 (B), the _two metal conductor plates 26b ₁ and 26b ₂ formed in step ₂ are joined together by ultrasonic waves or the like to form the external terminal portion 26 of the external terminal portion 26. The columnar terminal portion 28 is projected on both sides and in the frame-shaped terminal portion 27 in a state of being connected to each other via a thin portion 29.
In this case also, any surface may be used as the pattern portion connection surface, as in FIG.

Subsequently, FIG. 9A shows the frame-shaped terminal portion 2 later.
7. An annular metal wire frame 27a (thickness equal to the thickness of the columnar terminal portion 27) 27a made of a material such as solder or tin, and a metal sphere (diameter is the columnar terminal portion) such as solder and tin to be the columnar terminal portion 28. 28a is prepared, and a groove (corresponding to the metal wire frame 27a) 26c ₁ and a concave portion (corresponding to the metal ball 28a) are formed inside the groove 26c ₁ by half etching on a metal conductor plate of copper alloy, for example. Metal plate 2 with 26c2 formed
6c is prepared.

As shown in FIG. 9B, the groove 26
c ₁ a metal wire frame 27a is fitted in, it is obtained by fusion bonding by heating with a metal ball 28a is fitted in the recess 26c _2. That is, the frame-shaped terminal portion 27 of the metal wire frame 27a and the columnar terminal portion 28 of the metal ball 28a are formed in a thin connection state.

The external terminal portion 26 will be described later by exposing the surface on which the metal wire frame 27a and the metal sphere 28a are not attached and sealing the resin, and then etching to completely remove the metal conductor plate 26c. A frame-shaped terminal portion 27 and a columnar terminal portion 28 as shown in FIG. 11 (B) are formed.

Next, FIG. 10 shows a manufacturing process diagram of the chip bonding of the first embodiment. In FIG. 10, the pattern portion 25 and the external terminal portion 26 formed as described above are abutted with the terminal connection portion 32a and the corresponding columnar terminal portion 28 to form an insulating layer 35 (for example, an epoxy adhesive). A curable resin) or an insulating film is attached (S31).

Subsequently, the external terminal portion 26 is plated with copper to form a plating 36 to electrically connect the terminal connecting portion 32a and the columnar terminal portion 28 (S).
32).

Thereafter, the semiconductor chip 41 is mounted on the pattern portion 25 via the adhesive 42 (S33), and the pad 41a of the semiconductor chip 41 and the wire connecting portion 32b represented by the opening 34 are bonded by the wires 43a and 43b. (S34, see FIG. 2B).

The frame-shaped terminal portion 27 of the external terminal portion 26
Then, the columnar terminal portion 28 is exposed and the semiconductor chip 41 side is subjected to resin molding or resin potting to form the resin region 24 with the resin 23a (S35). This state is shown in FIG.

Therefore, FIG. 11 shows a manufacturing explanatory view of the final step of the first embodiment. FIG. 11A is formed in the step shown in FIG. 7, and in this state, the frame-shaped terminal portion 27 and the columnar terminal portion 28 in the external terminal portion 26 are in a conductive state.

Therefore, as shown in FIG. 11B, the exposed surface of the external terminal portion 26 is etched to the surface of the resin 23a, and the thin portion 29 is removed to remove the frame-shaped terminal portion 27 and the columnar terminal portion. 28 and are separated. Then, the separated frame-shaped terminal portion 27 and columnar terminal portion 28 are soldered, gold, silver,
It is a plating treatment such as tin or palladium that can be mounted on a substrate.

When the pattern portion 25 and the external terminal portion 26 are continuously formed, they are separated into individual semiconductor devices 21 _A at the end of various processes such as packaging, etching, plating, etc. in the continuous state. It is what is done.

In this way, the terminal region 24 is arranged on the bottom surface side of the semiconductor chip 41 and the external terminal portion is arranged on the bottom portion thereof, and the electric connection between the terminal region 24 and the semiconductor chip 41 is made by wire instead of the TAB technique. Since they are connected, the package can be generalized without being restricted by the size of the semiconductor chip 41 and the layout of the pads 41a.

Further, the external terminals of the lattice array (columnar terminal portion 2
The formation of 8) can be performed inexpensively and surely because the terminals are formed by the additional processing after the resin region 23 is formed by conducting all the terminals in the external terminal portion 26 in an unfinished state, and the semiconductor chip 41 can be protected. Resin can be applied.

Further, the external terminal portion 26 is provided with a frame-shaped terminal portion 27, which serves as a base for wire bonding and also serves as a terminal for a power source or a ground, so that the power source or the ground is collectively an apparent terminal. The number can be reduced and the noise resistance can be improved.

Next, FIG. 12 shows an external view of another package shape of the first embodiment. The semiconductor device 21B shown in FIG. 12 (A) is obtained by forming the frame-shaped terminal portions 27a ₁ through 27a ₄ divided into a four example periphery of the external terminal portions 26, other configurations are the same as FIG. 1 .

In this way, the frame-shaped terminal portions 27a _{1 to} 27a ₄
Is divided into a plurality of parts (an appropriate number is set according to the role), so that the power supply and the ground can be provided with the respective roles, and a necessary necessary signal system role can be provided.

Further, the semiconductor device 21 shown in FIG.
_C is the one in which the frame-shaped terminal portion 27 of FIG. 1 is composed of a first frame-shaped terminal portion 27a formed on the outer periphery and a second frame-shaped terminal portion 27b formed annularly in the columnar terminal portion 28. Other configurations are the same as those in FIG. This also makes it possible to play a role of a power source, a ground, etc., and to improve noise resistance.

Further, the semiconductor device 21 shown in FIG.
D further includes the second frame-shaped terminal portion 27b of FIG.
One in which was formed a second frame-shaped terminal portions 27a ₁ through 27a ₄ which is divided, it is possible to improve the similarly noise resistance, improved power, the freedom of the layout of sharing ground such Is something that can be done. Incidentally, FIG.
The shape may be a combination of (A) and FIG. 12 (C).

Next, FIG. 13 shows a block diagram of a second embodiment of the present invention. 13A is an external view and FIG. 13B is a cross-sectional view. A semiconductor device 2 shown in FIGS. 13A and 13B.
1E differs from the semiconductor device 21 _A shown in FIG. 1 in that the pattern portion 25 has a different structure and is connected to the external terminal portion 26 by vapor deposition. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIGS. 13A and 13B, the semiconductor device 21 _E is similar to FIG. 1 in that the package 22 is composed of the resin region 23 and the terminal region 24. The resin region 23 is the resin 23 that similarly protects the semiconductor chip 41.
a.

The terminal area 24 is composed of a pattern portion 25A and an external terminal portion 26, and the external terminal portion 26 is composed of a frame-shaped terminal portion 27 on the outer periphery and columnar terminal portions 28 arranged in a lattice pattern inside thereof. To be done. Frame-shaped terminal portion 27 and columnar terminal portion 28
Is insulated by the first insulating layer 51a, and the second insulating layer 51b is formed on the first insulating layer 51a by exposing the frame-shaped terminal portion 27 and the columnar terminal portion 28.

Further, a patterned pattern layer 52 is formed on the second insulating layer 51b above the frame-shaped terminal portion 27 and on the exposed surface of the columnar terminal portion 28 by vapor deposition of aluminum or the like. At this time, the wire connection portion 52a as shown in FIG. 2B is formed on the pattern layer 52 above the frame-shaped terminal portion 27. The connecting portion of the pattern layer 52 with the surface of the columnar terminal portion 28 becomes the terminal connecting portion in the first embodiment.

A third insulating layer 53, which is an upper insulating layer, is formed on the pattern layer 52, and the wire connecting portion 52 is formed.
The opening 53a is formed in the portion a. Third insulating layer 53
The semiconductor chip 41 is mounted on the upper surface by the adhesive 42. As shown in FIG. 2B, two rows of front and rear pads 41 a are formed on the semiconductor chip 41.
(43a, 43b) avoids contact at different heights and is electrically connected to the wire connecting portion 52a of the pattern layer 52. Further, among the pads 41 a, the pads 41 a for power supply or ground, the frame-shaped terminal portion 27, and the wires 43 are electrically connected.

In order to protect this semiconductor chip 41,
The resin region 23 is formed on the third insulating layer 53 by being sealed with the resin 23a. The manufacturing of the external terminal portion 26 in such a semiconductor device 21 _E is similar to that shown in FIGS.

Therefore, FIG. 14 shows a manufacturing explanatory view of the formation of the pattern layer of the second embodiment. In the external terminal portion 26 formed by FIGS. 4 to 6, the frame-shaped terminal portion 27 and the columnar terminal portion 28 are electrically connected to each other as shown in FIG. Portion 27 and columnar terminal portion 2
Powdered glass or glass paste, or epoxy resin is filled as the first insulating layer 51a in the recessed portion between 8.

Then, as shown in FIG. 14B, the columnar terminal portion 28 is exposed and the same glass or resin as the first insulating layer 51a is formed to form a second insulating layer 51b.

Here, FIGS. 14A and 14B show the case where the first and second insulating layers 51a and 51b are sequentially deposited, but the columnar terminal portion 28 is formed by melting glass on the entire surface.
The surface of the substrate is exposed to form the first insulating layer 51a, and CVD is performed.
Secondly, the surface of the columnar terminal portion 28 is exposed by the (chemical vapor deposition) method and is covered with SiOn (silicon oxide).
Insulating layer 51b may be used. Similarly, the entire surface is filled with resin to form the first insulating layer 51a, and the columnar terminal portion 28 is formed.
After exposing the surface of the above, the second insulating layer 51b may be formed by coating the portion other than the exposed surface with resin by printing or the like.

Then, as shown in FIG. 14C, the second
Of the insulating layer 51b and the columnar terminal portion 28 is formed on the exposed surface using a mask having a predetermined pattern, for example, aluminum is vapor-deposited, and then a wire-connectable metal such as gold or palladium is plated to form the pattern layer 52. To do. In this case, a pattern may be formed by photoetching after aluminum is vapor-deposited on the entire surface, and the above-described plating treatment may be performed.

Then, as shown in FIG. 14D, a third opening 53a is formed in the inner area of the frame-shaped terminal portion 27.
Forming an insulating film as the insulating layer 53 of
It is formed by forming a SiOn layer by D or applying a resin paste by print printing.

Next, FIG. 15 shows a sectional view of the final step of the second embodiment. FIG. 15A shows FIG.
The semiconductor chip 41 is mounted on the pattern portion 25 formed in (D) with an adhesive (for example, silver paste) 42, and as shown in FIGS.
3a, 43b) and the pad 41a and the wire connecting portion 52
Electrical connection is made with a. After that, the semiconductor chip 41 is sealed with the resin 23a above the terminal region 24 to form the resin region 23.

Then, as shown in FIG. 15B, the bottom surface of the external terminal portion 26 is etched, and the thin portion 29 is removed to separate the frame-shaped terminal portion 27 and the columnar terminal portion 28. Then, in order to make the surface mountable on a substrate, a plating process is performed with solder, gold, silver, tin, palladium or the like.

The pattern portion 25A and the external terminal portion 26
Are formed in a continuous state, they are separated into individual semiconductor devices 21 _E at the end of various processes such as packaging, etching, and plating in the continuous state.

The external terminal portion 26 is shown in FIG.
As shown in (C), it is divided at the outer periphery, or is formed annularly or appropriately in the columnar terminal portion 28 together with the outer periphery so as to have a role of a power source, a ground, etc., and improve noise resistance. It is also possible.

Further, when the thin portion 29 is removed by etching, as shown in FIG. 16A, the shape of the columnar terminal portion 28 is preliminarily determined such that the cross-sectional area above the thin portion 29 is smaller than the cross-sectional area below the thin portion 29. By forming it to be small, it is possible to make the cross-sectional areas of the upper portion and the lower portion of the columnar terminal portion 28 substantially equal as shown in FIG. 16B when the thin portion 29 is removed by etching. Therefore, the shape of the columnar terminal portion 28 can be improved.

Next, a semiconductor device 60 which is a third embodiment of the present invention will be described. FIG. 17 is a sectional view of a semiconductor device 60 which is a third embodiment of the present invention. The semiconductor device 60 generally includes a semiconductor chip 61, lead bodies 62,
It is composed of a sealing resin (package) 63, a solder resist (insulating member) 64, and the like.

The semiconductor chip 61 is electrically connected to the lead body 62 by the wire 65 in this embodiment. The lead body 62 is composed of a lead portion 66 extending outward of the semiconductor chip 61 and an external connection terminal portion 67 extending downward at a right angle to the lead portion 66. The external connection terminal portion 67 has an integral structure.

The lead portion 66 is made of nickel (N
i), aluminum (Al), titanium (Ti) or the like, gold (Au), silver (Ag),
Alternatively, the outer layer 66b made of palladium (Pd) or the like is formed.

The external connection terminal portion 67 is composed of a columnar terminal portion 68 having a columnar shape and a terminal end portion 69 formed at the lower end portion of the columnar terminal portion 68.
The columnar terminal portion 68 is made of copper (Cu), and the terminal end portion 69 is made of nickel (Ni), aluminum (A).
l), or gold (Au), silver (Ag), or palladium (P) under the inner layer 69a made of titanium (Ti) or the like.
The outer layer 69b made of d) or the like is formed.

As will be described later, the columnar terminal portion 68 is formed into a predetermined shape by an alkaline etchant (etching solution), but the lead portion 66 and the terminal end portion 69 arranged with the columnar terminal portion 68 interposed therebetween are formed. A material that does not dissolve in the alkaline etchant is selected. Therefore, when the columnar terminal portion 68 is formed by the etching process, the lead portion 66 and the terminal end portion 69 can be used as a resist.

The sealing resin 63 is, for example, an epoxy resin, and the semiconductor chip 61, the lead portion 66, and the semiconductor chip 61 are exposed with the lower surface of the semiconductor chip 61 and the lower surface of the lead portion 66 exposed.
The wire 65 is sealed. The sealing resin 63 is formed by resin molding using a molding die, for example.

The solder resist 64 is made of an electrically insulating material (for example, insulating resin) and is provided so as to cover at least the lower surface of the semiconductor chip 61 and the lower surface of the lead portion 66. Further, since the external connection terminal portion 67 is configured to extend downward as described above, the external connection terminal portion 67 penetrates the solder resist 64 and extends downward.

Further, in a portion of the external connection terminal portion 67 which extends through the solder resist 64 and extends downward, an Au film or a solder film (hereinafter referred to as an exterior film 7) is formed by, for example, electroless plating.
0) is formed. As described above, since the solder resist 64 made of an electrically insulating material is provided on the lower surface of the semiconductor chip 61 and the lower surface of the lead portion 66, the external connection terminal portion 6 is formed by electroless plating the exterior film 70.
7 does not cause the exterior film 70 to adhere to the semiconductor chip 61 and the lead portion 66.

In the semiconductor device 60 having the above-described structure, the lead body 62 extends to the outside of the semiconductor chip 61 as described above, and the lead body 66 extends downward at substantially right angles to the lead portion 66. And an external connection terminal portion 67 that operates. Therefore, the arrangement position of the external connection terminal portion 67 is determined by the extension length of the lead portion 66, but the extension length of the lead portion 66 can be set with a degree of freedom. Therefore, the arrangement position of the external connection terminal portion 67 can be set without being restricted by the size of the semiconductor chip 61, and the versatility can be improved.

Further, the lead portion 66 and the external connection terminal portion 67
Since the and are integrally formed, it is not necessary to form a via hole or route a wiring to electrically connect the lead portion 66 and the external connection terminal portion 67,
Therefore, the cost of the semiconductor device 60 can be reduced.

Subsequently, the semiconductor device 60 having the above structure
The manufacturing method of will be described with reference to FIGS. Note that the portions corresponding to the configuration of the semiconductor device 60 shown in FIG.

The semiconductor device 60 is manufactured by performing the lead frame forming step, the semiconductor chip mounting step, the sealing resin disposing step, the substrate removing step, the insulating member disposing step, and the exterior step. Hereinafter, each step will be described in detail.

In the lead frame forming step, the columnar terminal portion 6
The lead portion 66 and the terminal end portion 69 are formed on the substrate 71 to be 8 to form the lead frame 72.
This corresponds to the processing shown in 8 (A) to 8 (F). To form the lead frame 72, first, the substrate 71 is prepared as shown in FIG. The substrate 71 is, for example, a copper plate having a thickness of 100 μm. As shown in FIG. 18B, photoresist materials 73 and 74 are applied to the upper surface and the lower surface of the substrate 71 with a predetermined film thickness.

Subsequently, the photoresist materials 73 and 74
As shown in FIG.
As shown in (C), the photoresist material 7 in the portion corresponding to the formation position of the lead portion 66 and the formation position of the terminal end portion 69.
3, 74 are removed to form openings 75, 76. next,
The lead portion 6 is formed in the openings 75 and 76 by plating.
6 and the terminal end 69 are formed.

Specifically, first, Ni plating (Al or Ti may be used) is performed until the thickness becomes about 5 μm, and the inner layer 66a,
69a is formed, and then Au plating (Ag, Pd) is formed on the inner layers 66a, 69a to a thickness of about 0.1 μm.
But it's okay). FIG. 18D shows the openings 75 and 76.
A state in which the lead portion 66 and the terminal end portion 69 are formed is shown.

When the lead portion 66 and the terminal end portion 69 are formed at predetermined positions on both surfaces of the substrate 71 as described above, FIG.
As shown in (E), the photoresist materials 73 and 74 are removed, and only the lead portion 66 and the terminal end portion 69 are removed from the substrate 7.
1 is arranged. In addition, the substrate 71 in this state
29, a plurality of semiconductor devices 60 (two are shown in FIG. 29) are provided on one substrate 71, as shown in FIG.
Corresponding to the lead portion 66 and the terminal end portion 69 are formed.

Subsequently, the substrate 71 on which the lead portions 66 and the terminal end portions 69 corresponding to the plurality of semiconductor devices 60 are formed as described above is divided into regions of one semiconductor device 60. In the example shown in FIG. 29, the substrate 71 is divided at the position indicated by the alternate long and short dash line in the figure. As a result, the substrate 71 corresponding to one semiconductor device 60 (this one semiconductor device 6
A substrate 71 corresponding to 0 is called a lead frame 72).

As described above, in the lead frame forming step, the lead portions 66 and the terminal end portions 69 corresponding to a plurality of semiconductor devices are formed on one substrate 71, and thereafter, one region of the semiconductor device 60 for each one is formed. By dividing the substrate 71 into two and forming the lead frame 72, it is possible to obtain a large number of lead frames 72 from one substrate 71, and the lead frame 72 can be formed efficiently and accurately.

The process of dividing one substrate 71 into a plurality of lead frames 72 as described above is performed by using a pressing process. At this time, a positioning guide hole 77 and an inter-element throttle (not shown) are used. ) Is also formed collectively.
As a result, the lead frame forming step can be simplified as compared with a configuration in which the positioning guide hole 77 and the inter-element throttle are separately formed (for example, by etching). The lead frame 72 formed as described above is shown in FIG.

When the lead frame 72 is formed by performing the above lead frame forming step, the semiconductor chip mounting step is subsequently performed. This semiconductor chip mounting step is a step of mounting the semiconductor chip 61 at a predetermined position on the upper surface of the substrate of the lead frame 72 and performing a process of electrically connecting the semiconductor chip 61 and the lead portion 66. (G).

In the semiconductor chip mounting step, first, a soluble insulating material 78 made of a material (for example, polyvinyl alcohol) which is soluble in an alkaline etchant described later is applied to a predetermined position of the lead frame 72 where the semiconductor chip 61 is mounted. Then, the semiconductor chip 61 is fixed to the upper surface of the lead frame 72 using the soluble insulating material 78 as an adhesive. Then, a wire 65 such as a gold wire is formed between the semiconductor chip 61 and the lead portion 66 using a wire bonding method.
To arrange. At this time, in the lead portion 66, the outer layer 66b made of Au or the like is formed on the inner layer 66a made of Ni or the like, and the wire 65 is connected to the outer layer 66b made of the same material as the wire. And the lead portion 66 can be satisfactorily connected.

When the semiconductor chip mounting step is carried out as described above, the semiconductor chip 61 is mounted on the lead frame 72, and the wires 65 are arranged, then the sealing resin mounting step is carried out. The semiconductor chip 6 is used in the sealing resin disposing process.
This is a step of sealing the 1 and the lead portion 66 with the sealing resin 63, and is shown in FIG. In this embodiment, a method of molding the sealing resin 63 using a molding die is used. Thereby, the semiconductor chip 61
Also, the portion of the lead portion 66 other than the bottom surface and the wire 65 are sealed and protected in the sealing resin 63. As the material of the sealing resin 63, for example, epoxy resin is selected.

When the sealing resin disposing step is performed and the sealing resin 63 is dispositioned as described above, the substrate removing step is subsequently performed. The board removing step is a step of removing the board 71 and the soluble insulating material 78 while leaving the terminal position 69 disposed.

In this substrate removing step, the semiconductor device assembly 80 shown in FIG. 19H is immersed in an etching bath filled with an alkaline etchant (etching solution),
The substrate 71 made of Cu is removed by etching. At the time of this etching process, as described above, the lead portion 66 and the terminal end portion 69 are selected from materials that do not dissolve in the alkaline etchant (specific materials are as described above). Therefore, when the columnar terminal portion 68 is formed by the etching process, the lead portion 66 and the terminal end portion 69 are formed.
Can be used as a resist.

Therefore, the substrate 71 is dissolved and removed by the alkaline etchant except for the portion sandwiched between the lead portion 66 and the terminal end portion 69 by the above etching process. FIG. 19I shows a state where the substrate removing step is completed. As shown in the figure, the portion sandwiched between the lead portion 66 and the terminal end portion 69 of the substrate 71 remains even after the etching process is performed, so that the columnar portion is formed between the lead portion 66 and the terminal end portion 69. The terminal portion 68 is formed.

As a result, the lead portion 66 extending outward is formed, and the external connection terminal portion 67 is formed by the columnar terminal portion 68 and the terminal end portion 69 and extends downward at right angles to the lead portion 66. The lead body 62 is formed. Further, since the soluble insulating material 78 is also removed by the etching process as described above, the bottom surfaces of the semiconductor chip 61 and the lead portions 66 (excluding the positions where the external connection terminal portions 67 are formed) are formed in the state where the substrate removing step is completed. It is exposed from the sealing resin 63.

When the substrate removing step is performed and the substrate 71 other than the predetermined portion is removed as described above, the insulating member disposing step is subsequently performed. In this insulating member disposing step, the lower surface of the semiconductor chip 61 and the lower surface of the lead portion 66 exposed by performing the above-described substrate removing step are covered with a solder resist 64 (insulating member) except for external connection terminal portions. And is shown in FIG.

In this insulating member disposing step, a liquid insulating member 81 having a low viscosity is used as the solder resist 64, and after this liquid insulating member 81 is potted using a potting nozzle 82 as shown in FIG. 19 (J). The solder resist 64 is formed by coating or applying a predetermined film thickness using a spinner or the like.

As described above, in the insulating member disposing step, the liquid insulating member 81 having low viscosity is used as the base material of the solder resist 64, and the method of potting or applying the liquid insulating member 81 is used to dispose the insulating member. The installation process can be simplified. This is because the external connection terminal portion 67 is configured to extend downward (that is, project) from the lead portion 66 at a right angle downward.

Assuming that the external connection terminal portion 67 is LGA (Land
Assuming that the semiconductor device has a flat structure (small projection amount) like a Grid Array) structure, the external connection terminal portion is covered with the liquid insulating member by the method of simply potting or applying the liquid insulating member. It will be buried in the solder resist and will not function as a connection terminal. Therefore, when a liquid insulating member is used in this LGA structure, a treatment such as masking is required so that the insulating member does not adhere to the external connection terminal portion.

On the other hand, in the structure in which the external connection terminal portion 67 extends downward at a right angle from the lead portion 66 as in this embodiment, the external connection terminal portion 67 is liquid-insulated even if the liquid insulating member 81 is potted or applied. Since the member 81 (solder resist 64) penetrates and protrudes, the above-described masking or other processing is not necessary. Therefore, the step of disposing the insulating member can be simplified. FIG. 20K shows a state where the solder resist 64 is formed.

When the insulating member disposing step is performed and the solder resist 64 is formed as described above, the exterior step is subsequently performed. This exterior process uses solder resist 64
This is a step of forming the exterior film 70 on the surface of the external connection terminal portion 67 protruding from. Specifically, the external connection terminal portion 67
The exterior film 70 is formed by plating Au or solder by electroless plating, for example, on the portion that penetrates the solder resist 64 and extends downward. At this time, as described above, since the solder resist 64 made of an electrically insulating material is provided on the lower surface of the semiconductor chip 61 and the lower surface of the lead portion 66, the exterior film 70 is formed on the external connection terminal portion 67 by electroless plating. Even if formed, the exterior film 70 does not adhere to the semiconductor chip 61 and the lead portion 66.

By carrying out the steps described above, semiconductor device 60 shown in FIG. 17 is manufactured.
In the manufacturing method described above, the lead frame 72 is formed in advance in the lead frame forming step, and the semiconductor device 60 is manufactured using the lead frame 72 as a base material.
The semiconductor device 60 can be manufactured efficiently and highly accurately.

In the semiconductor chip mounting step, the semiconductor chip 61 is mounted on the lead frame 72 at a predetermined position using the soluble insulating material 78, and the soluble insulating material 78 is removed in the substrate removing step.
The lower surface of No. 1 is exposed. Therefore, the lower surface of the semiconductor chip 61 comes into contact with the solder resist 64, and the heat dissipation characteristics can be improved.

Further, since the exterior step of forming the exterior film 70 on the surface of the external connection terminal portion 67 is performed after the insulation member disposing step, the lead portion 66 and the semiconductor chip 61 are formed.
It is possible to reliably prevent the exterior film 70 from adhering to and short-circuiting between the adjacent lead portions and between the semiconductor chip 61 and the lead portion 66 due to the exterior film 70.

Next, a semiconductor device 90 which is a fourth embodiment of the present invention will be described. FIG. 21 is a sectional view of a semiconductor device 90 which is a fourth embodiment of the present invention. Note that FIG.
In FIG. 17, the same components as those of the semiconductor device 60 according to the third embodiment shown in FIG. 17 are designated by the same reference numerals and the description thereof will be omitted.

In the semiconductor device 90 according to the present embodiment, the soluble insulating member 78 is used to mount the semiconductor chip 61 on the lead frame 72 in the semiconductor device 60 according to the third embodiment, whereas the insoluble insulating material is used. The first feature is that the semiconductor chip 61 is mounted on the lead frame 72 by using 91. Therefore, even if the substrate 71 is etched with an alkaline etchant, the insoluble insulating material 91 does not dissolve, and as shown in the figure, the insoluble insulating material 91 remains below the semiconductor chip 61. There is.

Further, the semiconductor device 90 according to the present embodiment is
As described above, the external connection terminal portion 92 (hereinafter, this external connection terminal portion 92 is referred to as the inner peripheral terminal portion 92) is also formed under the insoluble insulating material 91 disposed under the semiconductor chip 61. It is characterized by 2. Therefore, in the semiconductor device 90 according to the present embodiment, the external connection terminal portion 67 is arranged on the outer peripheral portion of the semiconductor chip 61, and the inner peripheral terminal portion 92 is arranged on the inner peripheral portion of the semiconductor chip 61. It will be composed. That is, the terminal portions 67 and 92 are arranged on both the inner peripheral portion and the outer peripheral portion of the semiconductor chip 61.

As described above, the insoluble insulating material 91 remains under the semiconductor chip 61,
The lower portion of the insoluble insulating material 91 (that is, the semiconductor chip 6
It is possible to dispose the inner peripheral terminal portion 92 on the lower part of the position 1. In the semiconductor device 90 of the embodiment shown in FIG. 21, the inner peripheral terminal portion 92 is used as a heat radiating member for radiating the heat generated in the semiconductor chip 61.

With this structure, the heat generated in the semiconductor chip 61 is radiated through the inner peripheral terminal portion 92. In particular, the inner peripheral terminal portion 92 has the same configuration as the external connection terminal portion 67, and a terminal end portion formed of a Ni film, an Au film, or the like is formed below the columnar terminal portion 68 formed of Cu having good heat dissipation. Since 69 is provided, the heat generated in the semiconductor chip 61 can be efficiently dissipated.
In addition, since the lead portion is connected to the inner peripheral terminal portion 92, it is possible to use the inner peripheral terminal portion 92 as a signal terminal or a power supply terminal. This can be realized, and the density of the semiconductor device 90 can be increased.

Subsequently, the semiconductor device 90 configured as described above is used.
The manufacturing method will be described with reference to FIGS. 22 and 23. Note that the portions corresponding to the configuration of the semiconductor device 90 shown in FIG. Further, points different from the method of manufacturing the semiconductor device 60 described with reference to FIGS. 18 to 20 will be mainly described, and description of the same processing will be omitted.

The semiconductor device 90 is also manufactured by performing the lead frame forming step, the semiconductor chip mounting step, the sealing resin disposing step, the substrate removing step, the insulating member disposing step, and the exterior step.

22A to 22F show a lead frame forming step. 22 is different from the manufacturing method described above in the lead frame forming step according to the present embodiment.
In (C), when the openings are formed by performing double-sided exposure and development on the photoresist materials 73 and 74, the openings 75 and 76 are formed at the formation position of the lead portion 66 and the formation position of the terminal end portion 69. In addition to the
The point is that the opening 93 is also formed at the formation position of 2.

The opening 93 formed at the position where the inner peripheral terminal portion 92 is formed is plated with Ni (Al or Ti may be used) like the opening 76 formed at the position where the terminal end portion 69 is formed. Then, Au plating (or Ag or Pd may be used) is performed on the upper portion of the inner layer 69a to form the inner peripheral terminal portion 92. That is, the formation of the terminal end portion 69 for the inner peripheral terminal portion 92 is performed simultaneously with the formation of the terminal end portion 69 for the external connection terminal 67. FIG. 22D shows a state in which the lead portion 66 and the terminal end portion 69 are formed.

When the lead portion 66 and the terminal end portion 69 are formed at predetermined positions on both surfaces of the substrate 71 as described above, FIG.
The photoresist materials 73 and 74 are removed as shown in (E), and then the substrate 71 is divided into regions of one semiconductor device 90, whereby the lead frame 94 shown in FIG. Is formed.

As described above, in the lead frame forming step, the formation of the terminal end portion 69 for the inner peripheral terminal portion 92 and the formation of the terminal end portion 69 for the external connection terminal 67 are performed at the same time. Even if the portion 92 is provided, the lead frame forming process does not become complicated.

When the lead frame 94 is formed by performing the above lead frame forming step, the semiconductor chip mounting step is subsequently performed. In this semiconductor chip mounting process, the semiconductor chip 6 of the lead frame 94 is
1 is mounted on a predetermined position, and is made of Cu which is a material of the substrate 71.
Insoluble insulating material 9 made of a material that does not dissolve in an alkaline etchant that dissolves
1 is applied and the insoluble insulating material 91 is used as an adhesive to fix the semiconductor chip 61 to the upper surface of the lead frame 72. FIG. 22G shows a state where the semiconductor chip mounting process is completed.

When the semiconductor chip mounting step is performed as described above, the sealing resin disposing step is performed and the sealing resin 63 is disposed as shown in FIG. 23 (H). When the sealing resin disposing process is completed, the substrate removing process is subsequently performed.

In this substrate removing step, the semiconductor device assembly 95 shown in FIG. 23H is immersed in an etching bath filled with an alkaline etchant (etching solution),
The substrate 71 made of Cu is removed by etching. During the etching process, as described above, the lead portion 66 and the terminal end portion 69 are made of a material which is not dissolved in the alkaline etchant. Therefore, when the columnar terminal portion 68 is formed by the etching process, the lead portion 66 and the terminal end portion 69 can be used as a resist.

Therefore, the substrate 71 is dissolved and removed by the alkaline etchant except the portion sandwiched between the lead portion 66 and the terminal end portion 69 by the above etching process. FIG. 23I shows a state where the substrate removing step is completed. As shown in the figure, the portion sandwiched between the lead portion 66 and the terminal end portion 69 of the substrate 71 remains even after the etching process is performed, so that the columnar portion is formed between the lead portion 66 and the terminal end portion 69. The terminal portion 68 is formed.

In addition, as described above, the insoluble insulating material 91
Is formed of a material that is not dissolved by an alkaline etchant that dissolves the substrate 71, and thus is not removed even if the above etching process is performed and remains below the semiconductor chip 61.

As a result, the lead portion 66 extends outward, and the external connection terminal portion 67 is formed of the columnar terminal portion 68 and the terminal end portion 69 and extends downward at right angles to the lead portion 66. The lead body 62 is formed, and the inner peripheral terminal portion 92 is formed under the insoluble insulating material 91 (that is, the inner peripheral portion of the semiconductor chip 61). Since the inner peripheral terminal portion 92 and the semiconductor chip 61 are electrically insulated by the insoluble insulating material 91, the inner peripheral terminal portion 92 does not short-circuit with the semiconductor chip 61.

Also in this embodiment, the semiconductor chip 61 and the lead portion 6 are also in the state where the substrate removing process is completed.
The bottom surface of 6 (excluding the position where the external connection terminal portion 67 is formed) is exposed from the sealing resin 63.

When the substrate removing step is carried out as described above and the board 71 other than the predetermined portion is removed, the insulating member disposing step is carried out, and the lower surface of the semiconductor chip 61 and the leads are carried out as shown in FIG. 23 (J). The solder resist 64 is disposed on the lower surface of the portion 66. When the solder resist 64 is provided, the exterior process is subsequently performed to form the exterior film 70 on the surface of the external connection terminal portion 67 protruding from the solder resist 64, and the semiconductor device 90 shown in FIG. 21 is manufactured. .

By carrying out the steps described above, the semiconductor device 90 shown in FIG. 21 is manufactured.
According to the manufacturing method described above, similarly to the manufacturing method described with reference to FIGS. 18 to 20, the lead frame 94 is formed in advance in the lead frame forming step, and the semiconductor device 60 is manufactured using the lead frame 94 as a base material. Therefore, the semiconductor device 60 can be manufactured efficiently and highly accurately.

In addition, since the exterior step of forming the exterior film 70 on the surface of the external connection terminal portion 67 is performed after the insulation member disposing step, the lead portion 66 and the semiconductor chip 61 are formed.
It is possible to reliably prevent the exterior film 70 from adhering to and short-circuiting between the adjacent lead portions and between the semiconductor chip 61 and the lead portion 66 due to the exterior film 70.

In addition to this, in the manufacturing method according to the present embodiment, the semiconductor chip 61 is mounted at a predetermined position of the lead frame 94 using the insoluble insulating material 91 in the semiconductor chip mounting step, and the semiconductor chip 61 is not removed in the substrate removing step. Since the soluble insulating material 91 remains without being removed by etching,
The lower portion of the insoluble insulating material 91 (that is, the semiconductor chip 6
It is possible to dispose the inner peripheral terminal portion 92 (heat dissipating member) or the external connection terminal portion for dissipating the heat generated in the semiconductor chip in the lower part (1).

Next, a semiconductor device 100 which is a fifth embodiment of the present invention will be described. FIG. 24 shows the fifth embodiment of the present invention.
It is a sectional view of semiconductor device 90 which is an example. Incidentally, FIG.
4, the same components as those of the semiconductor device 60 according to the third embodiment shown in FIG. 17 are designated by the same reference numerals and the description thereof will be omitted.

In the semiconductor device 90 according to the present embodiment, the wires 65 are used to connect the semiconductor chip 61 and the lead portion 66 in the semiconductor device 60 according to the third embodiment, whereas the semiconductor chip 61 and the leads are used. It is characterized in that the bumps 101 are used to connect the portions 66 and flip-chip bonding is performed.

As described above, the flip chip bonding method is used to directly connect the semiconductor chip 61 and the lead portion 66 to each other by the bump 101, so that the electrical characteristics (eg, impedance characteristics) of the connection portion can be obtained.
Can be improved, and the density can be increased as compared with the wire bonding method, so that the number of pins can be increased. Next, a method of manufacturing the semiconductor device 100 having the above structure will be described with reference to FIGS. 25 and 26. The parts corresponding to the configuration of the semiconductor device 100 shown in FIG. 24 will be described with the same reference numerals. Also,
Differences from the method of manufacturing the semiconductor device 60 described with reference to FIGS. 18 to 20 will be mainly described, and description of the same processing will be omitted.

Also in the semiconductor device 100 according to this embodiment, the lead frame forming step, the semiconductor chip mounting step, the sealing resin disposing step, the substrate removing step, the insulating member disposing step, and the exterior step are performed. Manufactured by.

FIGS. 25A to 25F show the lead frame forming step. The difference from the manufacturing method described above in the lead frame forming process according to the present embodiment is shown in FIG.
In (C), when the openings are formed by performing double-sided exposure and development on the photoresist materials 73 and 74, the openings 102 corresponding to the formation positions of the lead portions 66 are extended to the lower part of the semiconductor chip 61. It is a point that was formed so as to be long.

In the opening 102, similarly to the opening 76 formed at the position where the terminal end portion 69 is formed, Ni plating (Al,
Ti may be used) to form the inner layer 69a, and then Au plating (Ag or Pd may be used) on the upper portion of the inner layer 69a.
Then, the inner peripheral terminal portion 92 is formed.

When the lead portion 66 and the terminal end portion 69 are formed at predetermined positions on both surfaces of the substrate 71 as described above, FIG.
As shown in FIG. 25E, the photoresist materials 73 and 74 are removed, and subsequently, the substrate 71 is divided into regions of one semiconductor device 90, whereby the lead frame 72 shown in FIG. Is formed.

As described above, in the lead frame forming step, the length and shape of the lead portion 66 can be arbitrarily set, and therefore, the flip chip bonding method can be easily applied.

When the lead frame 72 is formed by performing the above lead frame forming step, the semiconductor chip mounting step is subsequently performed. In this semiconductor chip mounting step, the bumps 101 (solder bumps, gold bumps, etc.) are formed in advance at predetermined positions on the electrode pads of the semiconductor chip 61 or the lead portions 66, and the semiconductor chip 6 is formed.
The semiconductor chip 61 is bonded to the lead portion 66 by heat-treating 1 with the lead portion 66 facing down. By using this flip chip bonding method, electrical characteristics and high density can be achieved as described above. FIG. 25G shows a state where the semiconductor chip mounting process is completed.

Although not shown in the embodiments shown in FIGS. 25 and 26, a soluble insulating material or an insoluble insulating material is applied to the lower portion of the semiconductor chip 61 as in the manufacturing method according to each of the above-described embodiments. It may be configured to. The effect of the structure in which the soluble insulating material or the insoluble insulating material is applied is as described above.

When the semiconductor chip mounting step is performed as described above, the sealing resin disposing step is performed, and the sealing resin 63 is disposed as shown in FIG. When the sealing resin disposing process is completed, the substrate removing process is subsequently performed.

In this substrate removing step, the semiconductor device assembly 103 shown in FIG. 26H is immersed in an etching bath filled with an alkaline etchant (etching solution), and the substrate 71 formed of Cu is etched. Remove. By this etching process, the substrate 71 is dissolved and removed by the alkaline etchant except for the portion sandwiched between the lead portion 66 and the terminal end portion 69. FIG. 26
(I) shows a state where the substrate removing step is completed.

When the substrate removing step is performed and the substrate 71 other than the predetermined portion is removed as described above, the insulating member disposing step is performed, and the lower surface of the semiconductor chip 61 and the leads are performed as shown in FIG. The solder resist 64 is disposed on the lower surface of the portion 66. When the solder resist 64 is provided, an exterior process is subsequently performed to form an exterior film 70 on the surface of the external connection terminal portion 67 protruding from the solder resist 64, and the semiconductor device 90 shown in FIG. 24 is manufactured. .

Next, a modified example of the lead frame forming step among the above semiconductor device manufacturing steps will be described with reference to FIGS. 27 and 28.

FIG. 27 shows a first lead frame forming step.
Shows a modified example of. In the lead frame forming step described above, the photoresist materials 73 and 74 are provided to form the lead portion 66 and the terminal end portion 69, and the predetermined openings 75 and 76 are formed in the photoresist material 73 and 74, thereby forming the lead portion 66 and the terminal. A method of forming the end portion 69 at a predetermined position with a predetermined shape has been performed.

On the other hand, the present modification is characterized in that a metal mask is used in place of the photoresist materials 73 and 74. Specifically, as shown in FIG. 27A, the metal mask 105 for the upper surface in which the opening 107 is previously formed at the position where the lead portion 66 is formed, and the terminal end portion 69.
A lower surface metal mask 106 having an opening 108 formed at the formation position is prepared.

Then, as shown in FIG. 27 (B),
Top metal mask 105 and bottom metal mask 106
Are mounted on the substrate 71. At this time, the metal mask 1 for the upper surface
05 and the lower surface metal mask 106 are accurately positioned and then mounted on the substrate 71.

As described above, each metal mask 105, 10
When 6 is mounted on the substrate 71, the substrate 71 is set in the vapor deposition device (or the sputtering device), and the openings 107,
First, Ni, Al, or Ti is formed into a film in 108 by an evaporation method to form inner layers 66a and 69a, and then Au, Ag, or Pd is formed on the inner layers 66a and 69a.
Is formed by a vapor deposition method to form outer layers 66b and 69b.

As a result, as shown in FIG. 27C, the openings 107, 1 of the metal masks 105, 106 are formed.
The lead portion 66 and the terminal end portion 69 are formed in the 08.
After that, the metal masks 105 and 106 are attached to the substrate 7
By removing from 1, the lead portion 66 and the terminal end portion 69 are formed at predetermined positions on the substrate 71, as shown in FIG.

According to the first modification described above, the lead portion 66 and the terminal end portion 69 can be formed by using the vapor deposition method (or the sputtering method). Further, since the openings 107 and 108 are formed in the metal masks 105 and 106 in advance, the processes such as exposure and development which are performed when the photoresist materials 73 and 74 are used are unnecessary, and the lead frame forming process can be simplified. Can be planned.

FIG. 28 shows a second lead frame forming step.
Shows a modified example of. In each of the lead frame forming steps described above, in order to form the lead portion 66 and the terminal end portion 69, first, the photoresist materials 73 and 74 are arranged on the substrate 71, and after the predetermined openings 75 and 76 are formed therein, The method of forming the inner layers 66a and 69a and the outer layers 66b and 69b to be the lead portion 66 and the terminal end portion 69 has been performed.

On the other hand, in this modified example, first, the inner layer film 110 and the outer layer film 111 to be the lead portion 66 and the terminal end portion 69 are formed on the substrate 71 over the entire surface of the substrate, and then the photoresist materials 112 and 113 are disposed. It is characterized by having a configuration.

Specifically, the substrate 7 shown in FIG. 28 (A)
First, as shown in FIG. 28B, the inner layer film 110 and the outer layer film 1 are formed over the entire upper surface and lower surface of the substrate 71.
11 is formed. The inner layer film 110 and the outer layer film 111 may be formed by a plating method or a vapor deposition method (sputtering method).

Then, photoresist materials 112 and 113 are formed on the substrate 71 on which the inner layer film 110 and the outer layer film 111 are formed.
Is provided, and the photoresist materials 112 and 113 are exposed and developed, so that the photoresist materials 112 and 113 are left only at the formation positions of the lead portions 66 and the terminal end portions 69. FIG. 28C shows a state in which the above processing is completed.

Subsequently, the inner layer film 110 and the outer layer film 111 are etched by using an etchant (etching solution) that dissolves both the inner layer film 110 and the outer layer film 111. At this time, since the inner layer film 110 and the outer layer film 111 in the portion covered with the photoresist materials 112 and 113 are not etched, the lead portion 66 and the terminal end portion are provided at predetermined positions of the substrate 71 as shown in FIG. 69 is formed.

After that, the photoresist material 112 remaining on the lead portion 66 and the terminal end portion 69,
By removing 113, only the lead portion 66 and the terminal end portion 69 are formed at predetermined positions of the substrate 71, as shown in FIG. 28 (E).

Also according to the second modification described above, the lead portion 66 and the terminal end portion 69 can be formed by using the vapor deposition method (or the sputtering method). Further, since the steps relating to the photoresist materials 112 and 113 are the same as the steps relating to the above-mentioned manufacturing methods, the manufacturing steps do not become complicated even if the second modification is adopted.

Next, a modified example of the encapsulating resin disposing step of the above-described semiconductor device manufacturing steps will be described.

FIG. 30 shows a modification of the sealing resin disposing process. In the sealing resin disposing step described above, the sealing resin 6
A molding method using a molding die has been used to form 3. However, in this molding method, the mold cost is high for manufacturing the mold, and the product cost of the semiconductor device is increased accordingly. Therefore, the present modification is characterized in that the sealing resin 116 is formed by a potting method without using a molding die.

In this modification, first, in the lead frame forming step, the resin stopper 115 is integrally formed on the boundary of the predetermined region where the sealing resin 116 is provided on the substrate 71. The resin stopper 115 is a protrusion protruding above the substrate 71 and is formed by, for example, press working or cutting.

Subsequently, by performing the same lead frame forming step and semiconductor chip mounting step as described above, the semiconductor chip 61, the wires 65, the lead portions 66, The terminal end portion 69 and the like are provided. In the example shown in FIG. 30, the semiconductor chip 61
A fusible insulating member 78 is disposed below the.

In the encapsulating resin disposing process carried out subsequently,
As shown in FIG. 30C, the sealing resin 116 is formed by potting. At this time, as described above, in the lead frame forming step, the resin stopper 11 is attached to the substrate 71
5 is formed, it is possible to prevent the resin from leaking to the outside of the resin stopper 115 even if the sealing resin 116 is potted in the sealing resin disposing step.

This makes it possible to form the sealing resin 116 using the potting method. Further, unlike the molding process, the formation of the sealing resin 116 by the potting method does not require a mold, so that the sealing resin disposing process can be simplified and the product cost can be reduced.

When the sealing resin 116 is formed by the potting method as described above, the substrate removing step is subsequently performed. In the substrate removing step, the substrate 71 is etched to remove the substrate 71 except the portion sandwiched between the lead portion 66 and the terminal end portion 69, and the external connection terminal is removed as shown in FIG. The part 67 is formed. On this occasion,
As described above, since the resin stopper 115 is formed integrally with the substrate 71, the resin stopper 115 is removed by etching in the substrate removing step.

Subsequently, an insulating member disposing step is performed to form a salt resist 64, and an external packaging step is performed to form an external packaging film 70 on the surface of the external connection terminal portion 67, as shown in FIG. The semiconductor device 120 shown in E) is formed. In this semiconductor device 120, the resin stopper 115 is removed by the etching process in the substrate removing step, so that the resin stopper 115 does not remain in the completed state. Therefore, it is possible to prevent the resin stopper 115 from becoming an obstacle and prevent the resin stopper 115 from increasing the size of the semiconductor device 120.

Next, a modified example of the substrate removing step of the above-described semiconductor device manufacturing steps will be described.

FIG. 31 shows a modification of the substrate removing process. In the above-described substrate removing step, the plate-shaped terminal end portion 69 having no notch or the like is used as a resist for etching the substrate 71 to form the columnar terminal portion 68. For this reason, when the substrate 71 is over-etched in the etching process, as shown in FIG. 31C, the terminal end portion 69 extends laterally from the columnar terminal portion 68 and remains in a brim shape, resulting in a lead shape. It will be defective.

Therefore, in this embodiment, in order to prevent the terminal end portion 69 from remaining in a brim shape after the etching process, the terminal end portion 69 is dissolved before the substrate 71 is dissolved with an etching solution.
It is characterized in that a notch 125 corresponding to the cross-sectional shape of the external connection terminal 67 (columnar terminal 68) is formed.

FIG. 31 (A) shows an enlarged view of the terminal end portion 69 in which the cutout portion 125 is formed. As shown in the figure, the notch 125 is formed so as to penetrate the terminal end 69, and the position of the notch 125 is the shape of the columnar terminal 68 to be formed by etching (indicated by a broken line in the figure).
Has been selected to correspond to.

This notch 125 is formed by forming the photoresist 7 at the position where the notch 125 is formed in the step shown in FIG. 18C in the lead frame forming step described above.
It can be easily formed by leaving 4. Alternatively, a method of forming the notch 125 in the terminal end 69 using a laser processing device or the like may be used after the lead frame forming step shown in FIGS. 18A to 18F is performed.

When the substrate 71 having the terminal end portion 69 having the cutout portion 125 is subjected to the etching treatment, in a state where the etching of the substrate 71 does not proceed to the cutout portion 125 formed in the terminal end portion 69, Terminal end 69
An outer peripheral portion (hereinafter, referred to as an outer peripheral portion 69-1) of the notch portion 125 is kept fixed to the substrate 71.

However, when the etching of the substrate 71 proceeds to the cutout portion 125 formed in the terminal end portion 69, as shown in FIG. 31B, the cutout portion 12 of the terminal end portion 69 is formed.
The outer peripheral portion 69-1 located on the outer periphery of 5 is detached from the substrate 71 and the terminal end portion 69.

Therefore, according to this modification, the terminal end portion 69 can be prevented from extending from the columnar terminal portion 68 in a brim shape after the etching process, and a good lead shape can be realized.

Next, a modified example of the exterior process in the above-described semiconductor device manufacturing process will be described.

FIG. 32 shows a modification of the exterior process. In the packaging process described above, electrolytic plating is used to dispose the packaging film 70 on the surface of the external connection terminal portion 67.
On the other hand, the present modification is characterized in that the dimple plate 130 is used to form the exterior film 70. Hereinafter, a specific process of the exterior process according to this modification will be described.

To form the exterior film 70, first, the dimple plate 130 having the dimple portion 131 formed at a position corresponding to the external connection terminal portion 67 is prepared. The dimple plate 130 is made of, for example, ceramic or metal, and the dimple portion 131 is a hemispherical recess.

Subsequently, the dimple portion 131 formed on the dimple plate 130 having the above structure is filled with the solder paste 132. The solder paste 132 is filled in the dimple portion 131 by using a squeegee or the like using the thick film printing technique. Further, since the dimple portions 131 are formed to have the same shape, each dimple portion 13 is formed.
The amount of the solder paste 132 filled in 1 is also equal.
In FIG. 32A, the solder paste 1 is applied to the dimple portion 131.
The state where 32 is filled is shown.

Subsequently, the external connection terminal portion 67 is inserted into the dimple portion 131 filled with the solder paste 132, as shown in FIG. 32 (B). Then, while maintaining the state in which the external connection terminal portion 67 is inserted into the dimple portion 131, the semiconductor device assembly 133 is placed in the reflow furnace together with the dimple plate 130 to perform a heat treatment. As a result, as shown in FIG. 32C, the solder to be the exterior film 70 can be formed on the surface of the external connection terminal portion 67.

As described above, in the exterior process, the dimple portion 131 of the dimple plate 130 is filled with the solder paste 132, the external connection terminal portion 67 is inserted, and the external connection terminal portion 67 is inserted into the dimple portion 131. By performing the heat treatment in this state and forming the solder to be the exterior film 70 on the surface of the external connection terminal portion 67, the exterior process can be simplified.

That is, in the conventional packaging process using the dimple plate, after filling the dimple portion of the dimple plate with the solder paste, the first heat treatment is performed to form the solder ball in the dimple portion, and then the second heat treatment. It has been practiced to dispose the solder balls formed by performing the processing on the external connection terminal portion.

On the other hand, in the exterior process according to this modification,
Heat treatment is performed with the external connection terminal portion 67 inserted in the dimple portion 131 filled with the solder paste 132, and solder is disposed on the external connection terminal portion 67, so that the number of times of heat treatment is reduced. Therefore, the exterior process can be simplified.

[0198]

As described above, according to the present invention, the following various effects can be realized.

According to the first aspect of the invention, the lead body is composed of the lead portion extending outward of the semiconductor chip and the external connection terminal portion extending downward at a right angle to the lead portion. Therefore, the arrangement position of the external connection terminal portion is determined by the extension length of the lead portion, but the extension length of the lead portion can be set with a degree of freedom.
Therefore, the arrangement position of the external connection terminal portion can be set without being restricted by the size of the semiconductor chip, and the versatility is improved. Further, since the lead portion and the external connection terminal portion are integrally formed, it is not necessary to form a via hole or lay out a wiring to electrically connect the lead portion and the external connection terminal portion, The cost of the semiconductor device can be reduced.

Further, in the inventions according to claims 2 and 3, since it is possible to form the columnar terminal portion by using the lead portion and the terminal end portion as resist, a resist material is separately provided for forming the columnar terminal portion. The columnar terminal portion can be formed easily and inexpensively as compared with the configuration in which it is provided.

Further, according to the invention of claim 4, the second insulating member is interposed between the semiconductor chip and the insulating member, so that the external connection terminal portion or the semiconductor chip is provided below the second insulating member. It becomes possible to arrange a cooling member.

According to the invention of claim 5, the external connection terminal portion is provided at the inner peripheral portion of the semiconductor chip, or at both the inner peripheral portion and the outer peripheral portion of the semiconductor chip. It becomes possible to arrange in a high density.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a partial cutout of FIG.

FIG. 3 is a manufacturing process diagram for forming the pattern portion of FIG. 1.

FIG. 4 is a manufacturing process diagram of the external terminal portion of FIG.

5 is a post-process manufacturing explanatory diagram of the external terminal portion of FIG. 4. FIG.

6 is a manufacturing explanatory view (1) of another shape of the external terminal portion of FIG. 4. FIG.

FIG. 7 is a manufacturing explanatory view (2) of another shape of the external terminal portion of FIG. 4.

FIG. 8 is a manufacturing explanatory view (3) of another shape of the external terminal portion of FIG. 4.

9 is a manufacturing explanatory view (4) of another shape of the external terminal portion of FIG. 4. FIG.

FIG. 10 is a manufacturing explanatory diagram of the chip bonding of the first embodiment.

FIG. 11 is a manufacturing explanatory diagram of the final step of the first embodiment.

FIG. 12 is an external view of another package shape according to the first embodiment.

FIG. 13 is a configuration diagram of a second embodiment of the present invention.

FIG. 14 is a manufacturing explanatory diagram of formation of a pattern portion according to the second embodiment.

FIG. 15 is a sectional view of a final step of the second embodiment.

FIG. 16 is a diagram for explaining another method of forming the columnar terminal portion.

FIG. 17 is a configuration diagram of a third embodiment of the present invention.

FIG. 18 is a diagram for explaining the manufacturing method of the semiconductor device according to the third example of the present invention (No. 1).

FIG. 19 is a drawing for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention) (2).

FIG. 20 is a view for explaining the manufacturing method of the semiconductor device according to the third example of the present invention (No. 3).

FIG. 21 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 22 is a diagram for explaining the manufacturing method of the semiconductor device according to the fourth example of the present invention (No. 1).

FIG. 23 is a view for explaining the manufacturing method of the semiconductor device according to the fourth example of the present invention (No. 2).

FIG. 24 is a configuration diagram of a fifth embodiment of the present invention.

FIG. 25 is a view for explaining the manufacturing method of the semiconductor device according to the fifth example of the present invention (No. 1).

FIG. 26 is a view for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention (No. 2).

FIG. 27 is a diagram for explaining the first modified example of the lead frame forming step.

FIG. 28 is a diagram for explaining a second modification example of the lead frame forming step.

FIG. 29 is a diagram for explaining a configuration in which a large number of lead frames are taken from one substrate.

FIG. 30 is a diagram for explaining a modified example of the sealing resin disposing step.

FIG. 31 is a diagram for explaining a modified example of the substrate removing step.

FIG. 32 is a diagram for explaining a modified example of the exterior process.

FIG. 33 is a configuration diagram of a semiconductor device of a conventional μBGA package.

[Explanation of symbols]

21A to 21E, 60, 90, 100, 120 semiconductor device 22 package 23 resin region 24 terminal region 25 pattern portion 26 external terminal portion 27 frame-shaped terminal portion 28, 68 columnar terminal portion 31 base layer 32 pattern layer 32a terminal connecting portion 32b Wire connection part 33, 35 Insulation layer 34 Opening part 36 Plating 41, 61 Semiconductor chip 42 Adhesive 43, 65 Wire 51a First insulation layer 51b Second insulation layer 52 Pattern layer 52a Wire connection part 53 Third insulation layer 53a Opening 62 Lead 63,116 Sealing resin 64 Solder resist 66 Lead 67 External connection terminal 69 Terminal end 70 Exterior film 71 Substrate 72,94 Lead frame 73,74,112,113 Photoresist material 75,76 , 93, 102, 107, 108 Opening 78 Soluble insulation 81 Liquid insulation Material 91 insoluble insulator 92 inner circumferential terminal portion 101 bumps 105 metal mask for the metal mask 106 under surface the upper surface 110 inner layer 111 outer membrane 115 resin stopper portion 125 notched portion 130 dimple plate 131 dimple 132 solder paste

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Eiji Sakoda             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Takashi Umoto             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Eiji Watanabe             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Masakazu Orishige             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Masanori Onodera             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited

Claims (5)

[Claims] 1. A semiconductor chip, a lead portion electrically connected to the semiconductor chip and extending in an outer direction of the semiconductor chip, integrally connected to the lead portion, and substantially connected to the lead portion. A lead body composed of an external connection terminal portion extending downward at a right angle, and a sealing resin for sealing the semiconductor chip and the lead portion with the lower surface of the semiconductor chip and the lower surface of the lead portion exposed. An insulating member which covers at least the lower surface of the semiconductor chip and the lower surface of the lead portion and is arranged in a state where the external connection terminal portion is penetrated, and the external connection terminal is the insulating member. A columnar terminal portion that is partially embedded in the insulating member and that protrudes from the lower surface of the insulating member, and a plurality of laminated structures, and the inner layer and the outer layer of the end are made of different metals. Wherein a is constituted by an end portion. 2. The semiconductor device according to claim 1, wherein the external connection terminal portion forming the lead body is composed of a columnar terminal portion and a terminal end portion formed at a lower end portion of the columnar terminal portion, Further, the semiconductor device is characterized in that the material of the lead portion and the terminal end portion is formed of a material having a resist action with respect to the material of the columnar terminal portion. 3. The semiconductor device according to claim 2, wherein the lead portion has a gold (A) layer on a nickel (Ni) layer, an aluminum (Al) layer, or a titanium (Ti) layer.
u) layer, silver (Ag) layer, or palladium (Pd) layer is formed, and the columnar terminal portion is formed of copper (Cu), and The terminal end portion has a gold (Au) layer, a silver (Ag) layer, or a palladium (Pd) layer under a nickel (Ni) layer, an aluminum (Al) layer, or a titanium (Ti) layer.
A semiconductor device having a structure in which layers are formed. 4. The semiconductor device according to claim 1, wherein a second insulating member is interposed between the semiconductor chip and the insulating member. 5. The semiconductor device according to claim 4, wherein the external connection terminal portion is provided on an inner peripheral portion of the semiconductor chip or on both an inner peripheral portion and an outer peripheral portion of the semiconductor chip. Semiconductor device.