JPH0385740A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0385740A
JPH0385740A JP22154789A JP22154789A JPH0385740A JP H0385740 A JPH0385740 A JP H0385740A JP 22154789 A JP22154789 A JP 22154789A JP 22154789 A JP22154789 A JP 22154789A JP H0385740 A JPH0385740 A JP H0385740A
Authority
JP
Japan
Prior art keywords
semiconductor chip
insulating film
conductor pattern
tape carrier
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22154789A
Other languages
Japanese (ja)
Inventor
Masakazu Kawada
政和 川田
Yasuo Matsui
松井 泰雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP22154789A priority Critical patent/JPH0385740A/en
Publication of JPH0385740A publication Critical patent/JPH0385740A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a semiconductor device by a tape carrier method high in yield rate, low in cost, and high in reliability by bringing a bonding tool into contact from the side of an insulating film and heating and pressurizing it so as to mount a semiconductor chip, and then injecting resin into the connection between the semiconductor chip and the lead of a conductor pattern and sealing it. CONSTITUTION:A slit 9 is formed at an insulating film between adjacent leads 4 in the vicinity of the lead top of a conductor pattern so as to manufacture a tape carrier 10. This tape carrier is placed, with the conductor pattern down, on a semiconductor chip 5, where a bump 6 is formed on the top side, and the positions of the bumps 6 on the chip and the ends of the leads 4 of the conductor pattern are aligned. Successively, the semiconductor chip 5 is connected to the conductor pattern while applying and pressurizing a bonding tool against it from the side of insulating film 1. Lastly, to protect the connection between the semiconductor chip 5 and the lead of conductor pattern, resin 8 is poured into it to seal the chip 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、テープキャリアに半導体チップを実装し、樹
脂封止をした半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a tape carrier and sealed with resin.

〔従来の技術〕[Conventional technology]

近年、デイスプレィ、電子計算機など半導体を用いるデ
バイスにおいて、小型・薄型・高密度化のため、テープ
キャリア方式が有望視されている。
In recent years, tape carrier systems have been viewed as promising for devices using semiconductors, such as displays and electronic computers, because they are smaller, thinner, and more dense.

しかしながら、従来のテープキャリアは、デバイス孔内
へ突き出したリードを形成する必要があったため工程が
複雑で、不安定なリードが変形するため歩留まりが悪く
、このため極めてコストも高いという欠点があった。
However, conventional tape carriers have the drawbacks of complicated processes because they require forming leads that protrude into device holes, poor yields due to unstable leads deformation, and extremely high costs. .

このような問題点を解消するため、本発明者らは先にデ
バイス孔へ突き出すリードを形成させることなく半導体
チップを実装する方法の発明をなし開示した。第3図に
この方法を示す。まず絶縁性フィルム(1)と導電体(
2)を接着剤(3)ではりあわせたフレキシブル基板上
に形成された導電体パターンに、バンプ(6)を上面に
形成した半導体チップ(5)をフェイスダウンで位置合
わせをする。その後、絶縁性フィルム側からボンディン
グツール(17)を当接させ、絶縁性フィルム(1)を
介して導電体パターンのリードの先端の接続部と半導体
チップ上のバンプ(6)を加熱加圧することにより半導
体チップ(5)を実装する。
In order to solve these problems, the present inventors have invented and disclosed a method for mounting a semiconductor chip without first forming leads protruding into device holes. Figure 3 shows this method. First, the insulating film (1) and the conductor (
A semiconductor chip (5) having bumps (6) formed on its upper surface is aligned face-down to a conductive pattern formed on a flexible substrate made by bonding 2) with an adhesive (3). After that, the bonding tool (17) is brought into contact with the insulating film side, and the connection part of the lead tip of the conductive pattern and the bump (6) on the semiconductor chip are heated and pressurized through the insulating film (1). The semiconductor chip (5) is mounted using the following steps.

最後に、半導体チップ(5)と導電体パターンのリード
との接続部を保護するため、第2図に示したように、開
孔(7)より樹脂(8)を注入して封止し、テープキャ
リア方式の半導体装置が完成する。この方法では、デバ
イス孔へ突き出すリードを形成する必要がないため、工
程が少なくて済み、しかもデバイス孔へ突き出している
導電体のリードが変形する不良発生がないため、歩留ま
りが高く低コストになりしかも接続部の信頼性が高いと
いう特徴があった。
Finally, in order to protect the connection between the semiconductor chip (5) and the leads of the conductor pattern, resin (8) is injected through the opening (7) and sealed, as shown in FIG. A tape carrier type semiconductor device is completed. With this method, there is no need to form leads that protrude into the device hole, so there are fewer steps, and there are no defects caused by deformation of the conductor leads that protrude into the device hole, resulting in high yields and low costs. Moreover, the connection part was characterized by high reliability.

ところが、樹脂封止をした製品を高温高温試験(HHT
)、飽和耐湿性試験(PCT)、熱ストレス試験(T/
C)などを行った場合、封止樹脂、銅箔(導電体)、絶
縁性フィルム、半導体デツプのそれぞれの線膨張係数・
湿度膨張係数の違いにより、樹脂(8)にクランクが生
したり、導電体パターンのリード(4)が断線するなど
の不良が生じる欠点が判明した。この問題を解決するに
は、封止樹脂や絶縁性フィルムの線膨張係数及び湿度膨
張係数を制御する方法が考えられるが、銅箔、半導体チ
ップの特性は変えることができないため、不良低減の効
果はあるものの根本的な解決策ではなかった。
However, resin-sealed products are subjected to high-temperature testing (HHT).
), saturated humidity test (PCT), heat stress test (T/
C) etc., the linear expansion coefficient and
It has been found that defects such as cracks in the resin (8) and disconnection of the leads (4) of the conductor pattern occur due to differences in humidity expansion coefficients. A possible solution to this problem is to control the linear expansion coefficient and humidity expansion coefficient of the encapsulating resin and insulating film, but since the characteristics of the copper foil and semiconductor chips cannot be changed, they are effective in reducing defects. However, it was not a fundamental solution.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は、従来技術のこのような欠点に鑑みて種々の検
討の結果なされたものであり、その目的とするところは
、歩留まりが高く、低コストで、且つ信頼性の高いテー
プキャリア方式の半導体装置を提供することにある。
The present invention was made as a result of various studies in view of the above drawbacks of the prior art, and its purpose is to provide a tape carrier type semiconductor with high yield, low cost, and high reliability. The goal is to provide equipment.

〔課題を解決するための手段〕[Means to solve the problem]

すなわち本発明は、可とう性のある絶縁性フィルム上に
導電体で形成した回路パターンを有するテープキャリア
に半導体チップを実装した半導体装置において、導電体
パターンのリード先端付近で隣接するリード間の絶縁性
フィルムの少なくとも1力所以上にスリットを設けると
共に、上面にバンプを形成した半導体チップ上に導電体
パターンを下側にしたテープキャリアを載置し、位置合
せして、前記絶縁性フィルム側からボンディングツール
を当接させ加熱加圧することにより半導体チップを実装
した後、半導体チップと導電体パターンのリードとの接
続部に樹脂を注入し封止したことを特徴とする半導体装
置である。
That is, the present invention provides a semiconductor device in which a semiconductor chip is mounted on a tape carrier having a circuit pattern formed of a conductor on a flexible insulating film, in which insulation between adjacent leads near the lead tips of the conductor pattern is improved. A tape carrier with a conductive pattern facing downward is placed on a semiconductor chip having a slit formed in at least one force position of the insulating film and bumps formed on the upper surface, aligned, and a slit is formed from the insulating film side. This is a semiconductor device characterized in that a semiconductor chip is mounted by bringing a bonding tool into contact and applying heat and pressure, and then a resin is injected into the connection portion between the semiconductor chip and the lead of the conductive pattern to seal it.

以下、図面により本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は本発明における半導体チップを実装する前のテ
ープキャリアを示す図、第2図は半導体チップを実装し
樹脂封止した完成品の断面図である。絶縁性フィルム(
1)と導電体(2)を接着剤(3)で貼りあわせたフレ
キシブル基板上に、フォトエツチングなどの方法により
形成された導電体(2)パターンのリードの表面にメツ
キを施し、次に、打抜きプレスなどを用いて、導電体パ
ターンのリード先端付近で隣接するリード間の絶縁フィ
ルム(1)にスリット(9)を形成し、第1図のような
テープキャリア(10)を作製する。
FIG. 1 is a diagram showing a tape carrier before mounting a semiconductor chip according to the present invention, and FIG. 2 is a sectional view of a completed product in which a semiconductor chip is mounted and resin-sealed. Insulating film (
Plating is applied to the surface of the lead of the conductor (2) pattern formed by a method such as photoetching on a flexible substrate in which the conductor (1) and the conductor (2) are bonded together with an adhesive (3), and then, Using a punching press or the like, slits (9) are formed in the insulating film (1) between adjacent leads in the vicinity of the lead tips of the conductive pattern to produce a tape carrier (10) as shown in FIG.

このテープキャリアの導電体パターンを下側にして、上
面側にバンプ(6)を形成した半導体チップ(5)の上
に載置し、チップ上のバンプ(6)と導電体パターンの
リードの先端との位置を合わせる。続いて、第3図のよ
うに絶縁性フィルム(1)側からボンディングツール(
17)を当て、押圧しながら導電体パターンに半導体チ
ップ(5)を接続する。最後に、半導体チップ(5)と
導電体パターン(2)のリードの接続部を保護するため
に樹脂(8〉を流し込み封止すれば、第2図に示すよう
な半導体装置が完成する。
With the conductor pattern of this tape carrier facing down, place it on top of the semiconductor chip (5) with bumps (6) formed on the top side, and connect the bumps (6) on the chip and the tips of the leads of the conductor pattern. Align with. Next, as shown in Figure 3, insert the bonding tool (
17) and connect the semiconductor chip (5) to the conductor pattern while pressing. Finally, a resin (8) is poured and sealed to protect the connection portions between the semiconductor chip (5) and the leads of the conductive pattern (2), thereby completing the semiconductor device as shown in FIG. 2.

このように、本発明では隣接する導電体パターン(2)
のリードの先端付近にスリット(−f+)を設けたこと
が特徴であり、このような構造にすることにより、封止
樹脂(8)、導電体(2)、絶縁性フィルム(1)、半
導体チップ(5)の線膨張係数および湿度膨張係数の違
いによって生じる応力を吸収することができ、樹脂のク
ランク、リードの断線などの不良の発生を防ぐことがで
きる。
In this way, in the present invention, adjacent conductor patterns (2)
The feature is that a slit (-f+) is provided near the tip of the lead, and with this structure, the sealing resin (8), the conductor (2), the insulating film (1), the semiconductor It is possible to absorb the stress caused by the difference in the coefficient of linear expansion and the coefficient of humidity expansion of the chip (5), and it is possible to prevent defects such as cranking of the resin and breakage of the leads.

また、本発明において樹脂封止をする際、半導体チップ
(5)と絶縁性フィルム(1)の間に隅々にまで樹脂が
入り込むように、導電体パターンのリードで囲まれた内
側の部位に開孔(7)を設け、この孔より樹脂を流し込
めばより信頼性の高い半導体装置を得ることが可能とな
る。
In addition, when performing resin sealing in the present invention, the inside part surrounded by the leads of the conductor pattern is sealed so that the resin gets into every corner between the semiconductor chip (5) and the insulating film (1). By providing an opening (7) and pouring resin through this hole, it becomes possible to obtain a more reliable semiconductor device.

本発明におけるスリット(9)の形成方法は、特に限定
するものではないが、コストの面ではプレス打抜き、リ
ードのピッチが細かくなってきた場合にはレーザ加工な
どを利用するのが好ましい。
The method of forming the slits (9) in the present invention is not particularly limited, but in terms of cost, it is preferable to use press punching, and when the pitch of the leads becomes finer, use laser processing.

また、本発明において使用する絶縁性フィルム(1,)
と導電体(2)の積層体は、通常フレキシブル印刷回路
用基板として用いられているものであれば何ら特定する
ものではないが、絶縁性フィルム(1)を介して加熱加
圧するため、絶縁性フィルム(1)、接着剤(3)はポ
リイミド樹脂などのように耐熱性があり、かつできるだ
け薄いものであるほうが望ましい。さらには、絶縁性フ
ィルム(1)上に華着、スパッタリング、メツキなどの
方法で金属膜を形威し、もしくは、金属箔上にエポキシ
樹脂、ポリイミド樹脂などの絶縁性樹脂を塗布、乾燥し
て得られた、接着剤を使用しない2層構造の積層体であ
れば、耐熱性を低下させ、あるいはボンディングツール
による加熱加圧の際に熱を遮る層が少なくなるので、よ
りよい結果を与える。
In addition, the insulating film (1,) used in the present invention
The laminate of the conductor (2) and the conductor (2) is not specified in any way as long as it is normally used as a flexible printed circuit board, but since it is heated and pressurized through the insulating film (1), it has an insulating property. It is desirable that the film (1) and adhesive (3) be heat resistant, such as polyimide resin, and as thin as possible. Furthermore, a metal film is formed on the insulating film (1) by a method such as garnishing, sputtering, or plating, or an insulating resin such as epoxy resin or polyimide resin is applied on the metal foil and dried. The resulting two-layer laminate that does not use an adhesive provides better results because there are fewer layers that reduce heat resistance or block heat during heating and pressing with a bonding tool.

導電体パターン表面上にはメツキを施しであるが、その
種類、厚み、溝底は特に限定するものではないが、半導
体チップ(5)上のバンプ(6)にあわせ金、錫、半田
など一般に用いられているものが好ましい。
The surface of the conductive pattern is plated, and its type, thickness, and groove bottom are not particularly limited, but gold, tin, solder, etc. are generally used to match the bumps (6) on the semiconductor chip (5). Those used are preferred.

また、封止樹脂(8)は、一般に半導体の封止用として
用いられているものであれば特に限定するものではない
が、耐湿性の高い液状エポキシ樹脂などが望ましい。
Further, the sealing resin (8) is not particularly limited as long as it is generally used for sealing semiconductors, but a liquid epoxy resin with high moisture resistance is desirable.

本発明の方法で使用するボンディングツール(17)は
、600°C11秒、200 g/リード以上の加熱加
圧ができ、半導体チップとの平行度が5μm以下の通常
使用されているものであれば特に限定するものではない
The bonding tool (17) used in the method of the present invention may be a commonly used bonding tool that can heat and press 200 g/lead or more at 600°C for 11 seconds and has a parallelism with the semiconductor chip of 5 μm or less. It is not particularly limited.

このように、本発明では、デバイス孔へ突き出すリード
を必要としない新しい構造のフィルムキャリア方式の半
導体装置において問題となっていた、樹脂封止後にクラ
ンクが生じたり、リードの断線が起こるという欠点を排
除することができ、高い歩留まりで、低コストかつ高信
頼性のフィルムキャリア方式の半導体装置が得られる。
As described above, the present invention solves the problems of cranking and breakage of leads after resin sealing, which have been problems in film carrier type semiconductor devices with a new structure that does not require leads protruding into device holes. It is possible to obtain a film carrier type semiconductor device with high yield, low cost, and high reliability.

以下、本発明の実施例と従来方式の比較例を示す。A comparative example between an embodiment of the present invention and a conventional method will be shown below.

〔実施例〕〔Example〕

厚さ35μmの電解銅箔にボリイ旦ド樹脂を塗布・乾燥
して厚さ25μmの絶縁層を形威し、2層構造の積層体
を得た。これを幅35mmのテープ状にスリットし、銅
箔面をエツチング加工によりパターン化し、表面にニッ
ケル5.0μmを下地にして金0.3μmのメツキを施
した。次に、プレス打抜きにより、銅パターンのリード
の先端にスリットを形成するとともに、半導体チップ上
の電極が囲む面積よりも小さい開孔をあけた。
A 25-μm-thick insulating layer was formed by coating a 35-μm-thick electrolytic copper foil with a polyimide resin and drying it to obtain a two-layered laminate. This was slit into a tape shape with a width of 35 mm, the copper foil surface was patterned by etching, and the surface was plated with 0.3 μm of gold with a nickel base of 5.0 μm. Next, a slit was formed at the tip of the lead of the copper pattern by press punching, and an opening smaller in area than the area surrounded by the electrode on the semiconductor chip was made.

続いて、半導体チップ上に形成された接続用金バンプと
テープキャリアの銅パターンのリードの先端とを位置合
わせし、ポリイミド樹脂絶縁層を介して、ボンディング
ツールを用いて、430°C11,5秒、荷重120 
g/リードで加熱加圧して接合し、半導体チップの実装
を行った。さらに、ボリイ2ド絶縁層に設けた開孔より
液状エポキシ樹脂を注入し、100°C13時間硬化さ
せた。
Next, the connection gold bumps formed on the semiconductor chip and the tips of the copper pattern leads of the tape carrier were aligned, and heated at 430°C for 11,5 seconds using a bonding tool through the polyimide resin insulating layer. , load 120
The semiconductor chip was mounted by heating and pressurizing and bonding with g/lead. Furthermore, liquid epoxy resin was injected through the opening provided in the BORIID insulating layer and cured at 100°C for 13 hours.

得られた半導体装置を環境試験したところ、HHT(8
5°C185%)1500時間、PCT(121’C,
100%)300時間、T/C(55°C,125°C
)300時間でいずれも封止樹脂のクラック、リードの
断線などの不良は発生しなかった。
When the obtained semiconductor device was subjected to an environmental test, HHT (8
5°C 185%) 1500 hours, PCT (121'C,
100%) 300 hours, T/C (55°C, 125°C
) After 300 hours, no defects such as cracks in the sealing resin or breakage of the leads occurred.

〔比較例〕[Comparative example]

スリットを形威しなかったこと以外は実施例と同じ構成
の、テープキャリア方式の半導体装置を作製し同様の環
境試験を行ったところ、HHT500時間で12%、P
CT100時間で26%、T/C200時間で24%の
不良が発生した。
A tape carrier type semiconductor device having the same configuration as the example except that the slit was not formed was fabricated and the same environmental test was conducted.
26% defects occurred at CT 100 hours and 24% defects occurred at T/C 200 hours.

〔発明の効果] このように、本発明に従うと、デバイス孔へ突き出すリ
ードのないテープキャリア方式の半導体装置の欠点であ
った、封止樹脂にクランクが生したり、導電体パターン
のリードが断線するという不良の発生を克服することが
でき、その結果、歩留まりが高く、低コストでかつ信頼
性の高い半導体装置を得ることが可能となる。
[Effects of the Invention] As described above, according to the present invention, problems such as cracks in the sealing resin and disconnection of the leads of the conductor pattern, which are disadvantages of tape carrier type semiconductor devices without leads protruding into device holes, can be avoided. As a result, it becomes possible to obtain a semiconductor device with high yield, low cost, and high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明における半導体チップを実装する前のテ
ープキャリアを示す図、第2図は半導体チップを実装し
樹脂封止した完成品の断面図で、第3図は本発明におけ
る半導体チップの実装方法を示す図である。
Fig. 1 is a diagram showing a tape carrier before mounting a semiconductor chip according to the present invention, Fig. 2 is a cross-sectional view of a finished product with a semiconductor chip mounted and resin-sealed, and Fig. 3 is a diagram showing a tape carrier before mounting a semiconductor chip according to the present invention. FIG. 3 is a diagram showing a mounting method.

Claims (1)

【特許請求の範囲】[Claims] (1)可とう性のある絶縁性フィルム上に導電体で形成
した回路パターンを有するテープキャリアに半導体チッ
プを実装した半導体装置において、導電体パターンのリ
ード先端付近で隣接するリード間の絶縁性フィルムの少
なくとも1カ所以上にスリットを設けると共に、上面に
バンプを形成した半導体チップ上に導電体パターンを下
側にしたテープキャリアを載置し、位置合せして、前記
絶縁性フィルム側からボンディングツールを当接させ加
熱加圧することにより半導体チップを実装した後、半導
体チップと導電体パターンのリードとの接続部に樹脂を
注入し封止したことを特徴とする半導体装置。
(1) In a semiconductor device in which a semiconductor chip is mounted on a tape carrier having a circuit pattern formed of a conductor on a flexible insulating film, an insulating film is formed between adjacent leads near the lead tips of the conductor pattern. A tape carrier with a conductor pattern facing down is placed on a semiconductor chip having a slit in at least one location and bumps formed on the upper surface, aligned, and a bonding tool is inserted from the insulating film side. 1. A semiconductor device characterized in that a semiconductor chip is mounted by bringing the semiconductor chip into contact with the leads under heat and pressure, and then a resin is injected into a connection portion between the semiconductor chip and a lead of a conductive pattern to seal it.
JP22154789A 1989-08-30 1989-08-30 Semiconductor device Pending JPH0385740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22154789A JPH0385740A (en) 1989-08-30 1989-08-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22154789A JPH0385740A (en) 1989-08-30 1989-08-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0385740A true JPH0385740A (en) 1991-04-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP22154789A Pending JPH0385740A (en) 1989-08-30 1989-08-30 Semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6407447B1 (en) 1999-04-07 2002-06-18 Nec Corporation Tape carrier package
JP2006204113A (en) * 2005-01-25 2006-08-10 Yasuo Seki Frozen zoni and method for producing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6407447B1 (en) 1999-04-07 2002-06-18 Nec Corporation Tape carrier package
JP2006204113A (en) * 2005-01-25 2006-08-10 Yasuo Seki Frozen zoni and method for producing the same
JP4680613B2 (en) * 2005-01-25 2011-05-11 靖夫 関 Frozen soup and method for producing the frozen soup

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