JPS60110129A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60110129A
JPS60110129A JP58217593A JP21759383A JPS60110129A JP S60110129 A JPS60110129 A JP S60110129A JP 58217593 A JP58217593 A JP 58217593A JP 21759383 A JP21759383 A JP 21759383A JP S60110129 A JPS60110129 A JP S60110129A
Authority
JP
Japan
Prior art keywords
semiconductor chip
gold
wire
wiring pattern
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58217593A
Other languages
Japanese (ja)
Inventor
Hisashi Oguro
小黒　寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP58217593A priority Critical patent/JPS60110129A/en
Publication of JPS60110129A publication Critical patent/JPS60110129A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent short-circuit between a semiconductor chip and metal fine lead by insulating the area in the vicinity of upper end of semiconductor chip prior to the electrical connection between a semiconductor chip and substrate by wire bonding method. CONSTITUTION:After depositing a chromium thin film and then a gold thin film on an insulated ceramic substrate 1 by the vacuum deposition method, electrolytic plating of gold is carried out in order to form a gold plated film on the thin film of gold. In succession, a wiring pattern 2 of the predetermined shape is formed by the photolithographic etching method. Thereafter, a semiconductor chip 3 is settled using a conductive bonding agent made of epoxy resin to the chip placing area 22 of the wiring pattern 2. Moreover, the area near the upper end of semiconductor chip 3, namely the four corners of upper surface is coated with an insulating paste 5 and this paste is dried up. Finally, the bonding pad 31 formed on the surface of semiconductor chip 3 and the bonding pad 21 formed in the predetermined area in the wiring pattern 2 on the ceramic substrate 1 are connected with a fine gold wire 6 using the nail head wire bonder.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に係り、特に基板上に
形成されたリードと半導体チップ表向上の所定の配線層
とを正しく接続するだめのワイヤづ？ンディング方法に
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for correctly connecting leads formed on a substrate and a predetermined wiring layer on the surface of a semiconductor chip. The wires? Regarding the landing method.

〔従来技術〕[Prior art]

通常、半導体装置の製造工程において、半導体チップを
基板上に固着し、電気的な接続を行なう実装工程では、
基板上の所定位置に半導体チップを載置し、接着した後
に、販半導体チップ表面に形成されたポンディングパッ
ドと、該基板上に形成されたポンプイングツｆツドとを
、ネイルヘッドワイヤデンディング方式によシ、金屑細
線を介して接続するという方法がとられている。Normally, in the manufacturing process of semiconductor devices, the mounting process involves fixing the semiconductor chip on the substrate and making electrical connections.
After placing the semiconductor chip at a predetermined position on the substrate and adhering it, the bonding pad formed on the surface of the sold semiconductor chip and the pumping pad formed on the substrate are connected using a nail head wire ending method. Well, the method used is to connect via thin scrap metal wire.

しかしながら、半導体装置の集積化が進むにつれて半導
体チップ自身の高密度化に加えて、基板の高密度化が高
まシ、金族細線同志の間隔および半導体チップ上のポン
ディングパッドと、基板上のボンディング・モッドとの
距離が短縮されると共に、線径の小さい金属細線は硬度
が充分でないことから、半導体チップの上縁と金属細線
とが短絡してしまうという不都合があった。However, as the integration of semiconductor devices progresses, not only the density of the semiconductor chip itself increases, but also the density of the substrate increases. In addition to shortening the distance to the bonding mod, the thin metal wire with a small wire diameter does not have sufficient hardness, resulting in a short circuit between the upper edge of the semiconductor chip and the thin metal wire.

〔発明の目的〕[Purpose of the invention]

本発明は、前記実情に鑑みてなされたもので、半導体チ
ップと基板と全ワイヤビンディングによって電気的に接
続するにあたシ、半導体チップと金属細線との間の短絡
を防止し、信頼性の篩い半導体装置を提供することを目
的とする。The present invention has been made in view of the above-mentioned circumstances, and is designed to prevent short circuits between the semiconductor chip and thin metal wires and improve reliability when electrically connecting the semiconductor chip and the substrate with all-wire binding. The object is to provide a sieve semiconductor device.

〔発明の構成〕[Structure of the invention]

上記目的を達成するため、木兄’ＪＪ＆よ、ワイヤ〆ン
ディング法によって半導体チップと基板上の間の電気的
接続を行なうのに先立ち、半導体チップの上縁近傍を絶
縁化しておくことを特徴とするものである。In order to achieve the above-mentioned purpose, Kien'JJ &Yo's method is characterized in that the vicinity of the upper edge of the semiconductor chip is insulated before electrical connection is made between the semiconductor chip and the substrate by the wire bonding method. It is something to do.

すなわち、半導体チップの上縁近傍を絶縁性物質で被覆
する等の方法によって、絶縁化しておくことによシ、金
属細線が半導体チップの上縁部に接触したとしても短絡
することがないようにし、半導体装置の信頼性を向上さ
せようとするもので必る。That is, by insulating the vicinity of the upper edge of the semiconductor chip by coating it with an insulating material, etc., it is possible to prevent a short circuit even if a thin metal wire comes into contact with the upper edge of the semiconductor chip. This is necessary in order to improve the reliability of semiconductor devices.

〔実施例〕〔Example〕

以下、本発明を、本発明実施例の半導体装置の製造方法
に基づき、図面を参照しつつ詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be explained in detail based on a method of manufacturing a semiconductor device according to an embodiment of the present invention, with reference to the drawings.

まず、絶縁性のセラミック基板１上に、真空蒸着法によ
って、クロム薄膜、次いで金尚膜を層膜した後、金の電
解メッキを行ない、金薄膜上に金メッキ膜を形成する。First, a thin chromium film and then a gold film are deposited on an insulating ceramic substrate 1 by vacuum evaporation, and then electroplated with gold to form a gold plating film on the gold thin film.

続いて、フォトリソエツチング法によシ、第１図に示す
如く、所定形状の配線／ぐターン２を形成する。Subsequently, as shown in FIG. 1, a wiring/gut turn 2 having a predetermined shape is formed by photolithography.

この後、該配線パターン２のチップ載置部（グイパッド
）２２に半導体チップ３を、エポキシ樹脂からなる導電
性接着剤を用いて、第２図に示す如く、固着する（ダイ
ボンディング工程）。Thereafter, the semiconductor chip 3 is fixed to the chip mounting portion (guid pad) 22 of the wiring pattern 2 using a conductive adhesive made of epoxy resin, as shown in FIG. 2 (die bonding step).

更に、第３図に示す如く、該半導体ナツツ３の上縁部近
傍４、ずなわち上面四方の角に絶縁性のペースト５を塗
布し乾燥する。Furthermore, as shown in FIG. 3, an insulating paste 5 is applied to the vicinity of the upper edge 4 of the semiconductor nut 3, that is, to the four corners of the upper surface, and then dried.

そして最後に、第４図に示す如く、ネイルヘッドワイヤ
ボンダーを使用し、半纏体チップ３表面に形成されたポ
ンディングパッド３１と前記セラミック基板１上の配線
／ぐターフ２内の所定位置に形成されたポンディングパ
ッド２１との間を金細線６で接続する。（ワイヤボンデ
ィング）このようにして形成された半導体装置では、金
細線６が半導体ナツツの上縁に接触したとしても、短絡
を起こすことがないため、装置としての信頼性が高い。Finally, as shown in FIG. 4, using a nail head wire bonder, a bonding pad 31 formed on the surface of the semi-integrated chip 3 and a predetermined position in the wiring/turf 2 on the ceramic substrate 1 are formed. A thin gold wire 6 is used to connect the bonding pads 21 that have been bonded to each other. (Wire Bonding) In the semiconductor device formed in this manner, even if the thin gold wire 6 comes into contact with the upper edge of the semiconductor nut, no short circuit will occur, so the device is highly reliable.

また、これによシ、基板上のチップ載置部２２と、がン
ディングパッド２１との距離ｔお↓ひ金細線の長さを第
５図に示す如く、更に短縮することが可能となシ、基板
の面密度化が可能となる。In addition, this makes it possible to further shorten the distance t between the chip mounting portion 22 on the board and the bonding pad 21, as well as the length of the thin metal wire, as shown in FIG. , it becomes possible to increase the areal density of the substrate.

さらには、半導体チップの高集積化（高′ｇ度化）に伴
い、ワイヤボンディングによって接続すべき金細線の数
が増えたとしても、金細勝が張着状態に近い状態となる
まで短縮できるため短絡事故は発生しにくい。Furthermore, even if the number of thin gold wires that need to be connected by wire bonding increases as semiconductor chips become more highly integrated (higher density), the wire bonding can be shortened to a state close to a bonded state. Therefore, short circuit accidents are less likely to occur.

従って、装置としての信頼性を低下させることなく、小
型の半導体装ｔを得ることが容易に可能とある。Therefore, it is possible to easily obtain a small semiconductor device t without reducing the reliability of the device.

なお、本発明実施例の方法においては、ダイボンｆ４ン
グ後、すなわち、基板上に半導体チップを固着した後に
、半導体ナツツの上縁部を絶縁化するという方法を用い
たが、基板への固着前、すなわち、半導体チップの状態
で、少なくとも上縁部近傍を絶縁化しても良いことは言
うまでもない。In the method of the embodiment of the present invention, a method was used in which the upper edge of the semiconductor nut was insulated after die bonding, that is, after the semiconductor chip was fixed on the substrate. That is, it goes without saying that at least the vicinity of the upper edge of the semiconductor chip may be insulated.

〔発明の効果〕〔Effect of the invention〕

以上、説明してきたように、本発明の方法によれば、基
板上の配線パターンと半導体チップとの間をワイヤがン
ディングによって電気的に接続するに先立ち、半導体チ
ップの上級部を絶縁化しているため、半導体チップと金
属細線とＶ間の短絡を防止し、配線パターンの面密度化
あるいは半導体チップの高集積化に際しても信頼性の高
い半導体装置を提供することが口」能となる。As described above, according to the method of the present invention, the upper part of the semiconductor chip is insulated before the wire is electrically connected between the wiring pattern on the board and the semiconductor chip by bonding. Therefore, it is necessary to prevent short circuits between the semiconductor chip, the thin metal wire, and V, and to provide a highly reliable semiconductor device even when the areal density of the wiring pattern is increased or the semiconductor chip is highly integrated.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第４図は不発ｎＡ実施例のワイヤボンディン
グ工程を示す図、第５図は本発明の他の実施例を示す図
である。 １・・・セラミック基板、２・・・配線パターン、２・
・・半導体チップ、４・・・上級部近傍、５・・・絶縁
ペースト、６・・・金細線、２１．３１・・・ポンディ
ングパッド、２２・・・チップ載置部。 第１回 第２図 ！。 ゝ１ 第３図 第４図 第５図1 to 4 are diagrams showing the wire bonding process of the non-explosion nA embodiment, and FIG. 5 is a diagram showing another embodiment of the present invention. 1... Ceramic board, 2... Wiring pattern, 2.
. . . Semiconductor chip, 4 . . . Near upper portion, 5 . . . Insulating paste, 6 . . . Fine gold wire, 21. 31 . 1st Figure 2! .ゝ1 Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 基板上に半導体チップを固着した後、ワイヤデンディン
グによって電気的接続を行なうにあたシ、ワイヤボンデ
ィングに先立ち、前記半導体チップの上級部を絶縁化す
る工程を含むことｔ％徴とする半導体装置の製造方法。A semiconductor device comprising the step of insulating an upper part of the semiconductor chip prior to wire bonding, after fixing the semiconductor chip on a substrate and making an electrical connection by wire bonding. manufacturing method.
JP58217593A 1983-11-18 1983-11-18 Manufacture of semiconductor device Pending JPS60110129A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58217593A JPS60110129A (en) 1983-11-18 1983-11-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58217593A JPS60110129A (en) 1983-11-18 1983-11-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60110129A true JPS60110129A (en) 1985-06-15

Family

ID=16706722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58217593A Pending JPS60110129A (en) 1983-11-18 1983-11-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60110129A (en)

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