JPH0888464A - Flip-chip-mounting method - Google Patents
Flip-chip-mounting methodInfo
- Publication number
- JPH0888464A JPH0888464A JP22440794A JP22440794A JPH0888464A JP H0888464 A JPH0888464 A JP H0888464A JP 22440794 A JP22440794 A JP 22440794A JP 22440794 A JP22440794 A JP 22440794A JP H0888464 A JPH0888464 A JP H0888464A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- substrate
- mounting method
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2902—Disposition
- H01L2224/29034—Disposition the layer connector covering only portions of the surface to be connected
- H01L2224/29036—Disposition the layer connector covering only portions of the surface to be connected covering only the central area of the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基板上にＩＣチップを
実装するフリップチップ実装方法に係り、特に生産性の
よい低コストのフリップチップ実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method for mounting an IC chip on a substrate, and more particularly to a low cost flip chip mounting method with high productivity.
【０００２】[0002]
【従来の技術】図２に従来のフリップチップ実装方法の
一例を示す。図２（ａ）において、セラミックや有機材
で構成された基板１上には、銅などでパターニングされ
た端子電極部としてのランド２が設けられている。基板
１の表面のランド２以外の部分に半田レジスト３を塗布
し、その上面に半田をプリコートすることにより、ラン
ド２上に半田部４が被覆される。さらに半田レジスト３
及び半田部４の表面にフラックス５を塗布する。2. Description of the Related Art FIG. 2 shows an example of a conventional flip chip mounting method. In FIG. 2A, a land 2 as a terminal electrode portion patterned with copper or the like is provided on a substrate 1 made of ceramic or an organic material. The solder resist 3 is applied to a portion other than the land 2 on the surface of the substrate 1, and the upper surface of the solder resist 3 is pre-coated with solder, whereby the solder portion 4 is coated on the land 2. Further solder resist 3
And the flux 5 is applied to the surface of the solder portion 4.
【０００３】次に、図２（ｂ）に示すように、予め所定
の位置に半田バンプ６が形成されたＩＣチップ７を、半
田バンプ６が基板１上に形成された半田部４に接するよ
うに搭載し、図２（ｃ）示すように、摂氏２１０度乃至
２３０度に加熱して半田付けを行なった後洗浄する。そ
の後、図２（ｄ）に示すように、ＩＣチップ７の周辺部
にディスペンサなどを用いて、フィラーが混入された樹
脂８を塗布し、摂氏８０度乃至１００度に加熱して封入
する。その後、摂氏１２０度乃至１６０度で本硬化させ
る。Next, as shown in FIG. 2 (b), the IC chip 7 having the solder bumps 6 previously formed at predetermined positions is brought into contact with the solder portions 4 formed on the substrate 1 by the solder bumps 6. 2C, as shown in FIG. 2C, heating is performed at 210 to 230 degrees Celsius to perform soldering, and then cleaning is performed. Then, as shown in FIG. 2D, a resin 8 mixed with a filler is applied to the peripheral portion of the IC chip 7 using a dispenser or the like, and heated to 80 to 100 degrees Celsius to be sealed. Then, the main curing is performed at 120 to 160 degrees Celsius.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記の
ような従来のフリップチップ実装方法によると、基板１
上にＩＣチップ７を半田付けしたときに、基板１とＩＣ
チップ７との間の間隔が狭いため、樹脂８を充填するた
めに時間がかかる。また、半田付けした後に樹脂８を充
填して封止するために、半田付け後の洗浄工程が必要と
なる。これらのために、従来の方法では生産性が悪くコ
スト高になるという問題があった。さらに、洗浄が均一
に行なわれないと、樹脂封止時に気泡が入りやすく、封
止の十分な信頼性が得られない恐れがあった。However, according to the conventional flip chip mounting method as described above, the substrate 1
When the IC chip 7 is soldered on top, the board 1 and the IC
Since the space between the chip 7 and the chip 7 is narrow, it takes time to fill the resin 8. In addition, a cleaning process after soldering is required to fill and seal the resin 8 after soldering. For these reasons, the conventional method has a problem that the productivity is poor and the cost is high. Furthermore, if the cleaning is not performed uniformly, bubbles may easily enter during the resin sealing, and sufficient sealing reliability may not be obtained.
【０００５】本発明はこのような状況に鑑みてなされた
もので、少ない工程で高い信頼性を持ってＩＣチップの
実装を行なうことのできる低コストのフリップチップ実
装方法を提供することを目的とする。The present invention has been made in view of such circumstances, and an object thereof is to provide a low-cost flip-chip mounting method capable of mounting an IC chip with high reliability in a small number of steps. To do.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、請求項１に記載の本発明は、基板１上に形成された
端子電極部（例えば図１のランド２）にＩＣチップ７を
搭載し、半田付けを行なうフリップチップ実装方法にお
いて、ランド２を半田部４で被覆し、基板１の半田部４
以外の表面に封止剤（例えば図１の樹脂８）を塗布し、
半田部４の表面にフラックス５を塗布した後に半田部４
上にＩＣチップ７を搭載し、加熱による半田付けと樹脂
８の充填とを同時に行なうことを特徴とする。To achieve the above object, the present invention according to claim 1 provides an IC chip 7 on a terminal electrode portion (for example, land 2 in FIG. 1) formed on a substrate 1. In the flip chip mounting method of mounting and soldering, the land 2 is covered with the solder portion 4, and the solder portion 4 of the substrate 1
Apply a sealant (for example, resin 8 in FIG. 1) to the surface other than
After applying the flux 5 to the surface of the solder portion 4, the solder portion 4
The IC chip 7 is mounted on the upper side, and soldering by heating and filling of the resin 8 are simultaneously performed.
【０００７】請求項２に記載のフリップチップ実装方法
は、加熱による半田付けが終了した後に再度加熱し、本
硬化させることを特徴とする。The flip-chip mounting method according to a second aspect is characterized in that after the soldering by heating is completed, it is heated again to be fully cured.
【０００８】請求項３に記載のフリップチップ実装方法
は、加熱による半田付けが終了した後に、ＩＣチップ７
の周辺部に樹脂８を塗布し、加熱による本硬化を行なう
ことを特徴とする。In the flip-chip mounting method according to the third aspect, after the soldering by heating is completed, the IC chip 7
The resin 8 is applied to the peripheral portion of and the main curing is performed by heating.
【０００９】[0009]
【作用】請求項１に記載のフリップチップ実装方法にお
いては、基板１上の半田部４の表面にフラックス５を塗
布し、半田部４以外の表面に樹脂８を塗布した後にＩＣ
チップ７を搭載して加熱するので、半田付けと樹脂封止
とが同時に行なわれる。この結果、工数及びコストの低
減を図ることができる。In the flip chip mounting method according to the first aspect, the flux 5 is applied to the surface of the solder portion 4 on the substrate 1, and the resin 8 is applied to the surface other than the solder portion 4 before the IC is applied.
Since the chip 7 is mounted and heated, soldering and resin sealing are performed simultaneously. As a result, man-hours and costs can be reduced.
【００１０】請求項２に記載のフリップチップ実装方法
においては、半田部４及び半田パンプ６が加熱により溶
融し、硬化するまでの間に、樹脂８が基板１とＩＣチッ
プ７との間に全面に封入される。その後、再度加熱する
ことにより樹脂８を本硬化させる。この結果、均一な樹
脂封止が可能となる。In the flip chip mounting method according to the second aspect, the resin 8 is entirely covered between the substrate 1 and the IC chip 7 until the solder portion 4 and the solder bump 6 are melted by heating and hardened. Is enclosed in. After that, the resin 8 is fully cured by heating again. As a result, uniform resin sealing is possible.
【００１１】請求項３に記載のフリップチップ実装方法
においては、半田付けが終了した後にＩＣチップ７の周
辺部に樹脂８を塗布し、さらにその後に本硬化を行なう
ようにしたので、ＩＣチップ７の周辺部を完全に封止す
ることができる。In the flip chip mounting method according to the third aspect, the resin 8 is applied to the peripheral portion of the IC chip 7 after the soldering is completed, and then the main curing is performed. The peripheral portion of the can be completely sealed.
【００１２】[0012]
【実施例】以下、本発明のフリップチップ実装方法の一
実施例を図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the flip chip mounting method of the present invention will be described below with reference to the drawings.
【００１３】図１に本発明の一実施例の工程を示す。図
１において、図２に示す従来例の部分と対応する部分に
は同一の符号を付してあり、その説明は適宜省略する。
図１（ａ）において、基板１上のランド２にプリコート
された半田部４上に、ディスペンサまたは印刷によりフ
ラックス５を塗布する。次に、基板１上の半田レジスト
３の表面の半田部４の間に、ディスペンサまたは印刷に
より樹脂８を所定の厚さに塗布する。この厚さは、図１
（ｂ）に示すように、ＩＣチップ７を半田部４上に搭載
したときの、基板１とＩＣチップ７との間の間隔Ａより
小さく、図１（ｃ）に示す半田付け後の間隔Ｂより大き
く形成する。FIG. 1 shows a process of one embodiment of the present invention. In FIG. 1, parts corresponding to those of the conventional example shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
In FIG. 1A, the flux 5 is applied to the solder portion 4 precoated on the land 2 on the substrate 1 by a dispenser or printing. Next, a resin 8 is applied to a predetermined thickness between the solder portions 4 on the surface of the solder resist 3 on the substrate 1 by a dispenser or printing. This thickness is
As shown in (b), it is smaller than the distance A between the substrate 1 and the IC chip 7 when the IC chip 7 is mounted on the solder portion 4, and the distance B after soldering shown in FIG. 1 (c). Form larger.
【００１４】図１（ｂ）に示すように、ＩＣチップ７を
基板１の半田部４上に搭載した後、図１（ｃ）に示すよ
うに、摂氏２１０度乃至２３０度に加熱して半田付けを
行なう。このとき、半田の張力とＩＣチップ７の自重に
より、ＩＣチップ７は基板１側に沈み込む。同時に、樹
脂８の封入が始まり、毛細管現象により全面に封入され
る。最後に、摂氏１２０度乃至１６０度で数時間低温で
加熱することにより樹脂８が硬化され、半田付けと樹脂
封入とを同時に行なうことができる。After mounting the IC chip 7 on the solder portion 4 of the substrate 1 as shown in FIG. 1B, it is heated to 210 to 230 degrees Celsius and soldered as shown in FIG. 1C. Make an attachment. At this time, the IC chip 7 sinks into the substrate 1 side due to the tension of the solder and the weight of the IC chip 7. At the same time, the encapsulation of the resin 8 begins and the resin 8 is encapsulated over the entire surface by the capillary phenomenon. Finally, the resin 8 is cured by heating at a low temperature of 120 to 160 degrees Celsius for several hours, so that soldering and resin encapsulation can be performed simultaneously.
【００１５】本実施例によれば、基板１上にフラックス
５及び樹脂８を塗布した後に、同時に半田付けと樹脂封
止を行なうことができ、樹脂封入の工程が不要となり、
工数とコストの低減を図ることができる。また、樹脂封
入前の洗浄工程も不要となるので、コストの低減と環境
の保全とを図ることができる。さらに、樹脂封入時の気
泡発生を防ぐことができ、樹脂封止の信頼性を向上させ
ることができる。しかも、予め基板１上に樹脂８を塗布
するので、基板１とＩＣチップ７との間隔の狭いフリッ
プチップの実装が可能となる。According to this embodiment, after the flux 5 and the resin 8 are applied on the substrate 1, the soldering and the resin sealing can be performed at the same time, and the step of resin encapsulation becomes unnecessary,
It is possible to reduce man-hours and costs. In addition, since the cleaning step before resin encapsulation is not necessary, cost reduction and environmental protection can be achieved. Further, it is possible to prevent bubbles from being generated when the resin is sealed, and it is possible to improve the reliability of resin sealing. Moreover, since the resin 8 is applied on the substrate 1 in advance, it is possible to mount a flip chip having a narrow gap between the substrate 1 and the IC chip 7.
【００１６】なお、図１（ｄ）に示すように、半田付け
部を終了した後に、ＩＣチップ７の周辺部に再度樹脂８
を塗布し、加熱硬化することにより、ＩＣチップ７の周
辺部を完全に封止することができる。Note that, as shown in FIG. 1D, after the soldering portion is finished, the resin 8 is again applied to the peripheral portion of the IC chip 7.
By coating and heat curing, the peripheral portion of the IC chip 7 can be completely sealed.
【００１７】[0017]
【発明の効果】以上説明したように、請求項１及び２に
記載のフリップチップ実装方法によれば、基板上に封止
剤及びフラックスを塗布した後に、同時に半田付けと封
止剤充填を行なうようにしたので、封止剤封止のための
工程が不要となり、工数及びコストの低減を図ることが
できる。また、封止剤充填の前の洗浄工程も不要となる
ので、コストの低減と環境の保全とを図ることができ
る。さらに、封止剤により封止を行なうときに気泡の発
生を防ぐことができ、封止の信頼性を向上させることが
できる。しかも、基板上に予め封止剤を塗布するので、
基板とＩＣチップとの間隔の狭いフリップチップの実装
が可能となる。As described above, according to the flip chip mounting method of the first and second aspects, after the sealant and the flux are applied on the substrate, the soldering and the sealant filling are simultaneously performed. As a result, the step for sealing the sealant becomes unnecessary, and the number of steps and cost can be reduced. Further, since a cleaning step before filling the sealant is not necessary, cost reduction and environmental protection can be achieved. Furthermore, it is possible to prevent bubbles from being generated when sealing is performed with the sealing agent, and it is possible to improve the reliability of sealing. Moreover, since the sealant is applied on the substrate in advance,
It is possible to mount a flip chip having a narrow gap between the substrate and the IC chip.
【００１８】請求項３に記載のフリップチップ実装方法
によれば、ＩＣチップの周辺部に封止剤を塗布した後に
半田を硬化するようにしたので、ＩＣチップの周辺部を
完全に封止することができる。According to the flip chip mounting method of the third aspect, since the solder is hardened after the sealing agent is applied to the peripheral portion of the IC chip, the peripheral portion of the IC chip is completely sealed. be able to.
【図１】本発明のフリップチップ実装方法の一実施例の
工程を示す説明図である。FIG. 1 is an explanatory view showing a process of an embodiment of a flip chip mounting method of the present invention.
【図２】従来のフリップチップ実装方法の一例の工程を
示す説明図である。FIG. 2 is an explanatory diagram showing a process of an example of a conventional flip chip mounting method.
１ 基板 ２ ランド（端子電極部） ４ 半田部 ５ フラックス ７ ＩＣチップ ８ 樹脂（封止剤） 1 substrate 2 land (terminal electrode part) 4 solder part 5 flux 7 IC chip 8 resin (sealant)
Claims (3)
ップを搭載し、半田付けを行なうフリップチップ実装方
法において、 前記端子電極部を半田部で被覆し、前記基板の前記半田
部以外の表面に封止剤を塗布し、前記半田部の表面にフ
ラックスを塗布した後に、前記半田部上に前記ＩＣチッ
プを搭載し、加熱による半田付けと前記封止剤の充填と
を同時に行なうことを特徴とするフリップチップ実装方
法。1. A flip-chip mounting method in which an IC chip is mounted on a terminal electrode portion formed on a substrate and soldering is performed. In the flip-chip mounting method, the terminal electrode portion is covered with a solder portion, and other than the solder portion of the substrate. After applying a sealant on the surface and applying a flux on the surface of the solder part, the IC chip is mounted on the solder part, and soldering by heating and filling of the sealant are performed simultaneously. Characteristic flip chip mounting method.
再度加熱し、本硬化させることを特徴とする請求項１に
記載のフリップチップ実装方法。2. The flip chip mounting method according to claim 1, wherein after the soldering by the heating is finished, the heating is performed again and the main curing is performed.
に、前記ＩＣチップの周辺部に前記封止剤を塗布し、加
熱による本硬化を行なうことを特徴とする請求項２に記
載のフリップチップ実装方法。3. The flip chip mounting according to claim 2, wherein after the soldering by heating is completed, the sealing agent is applied to the peripheral portion of the IC chip and main curing is performed by heating. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22440794A JPH0888464A (en) | 1994-09-20 | 1994-09-20 | Flip-chip-mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22440794A JPH0888464A (en) | 1994-09-20 | 1994-09-20 | Flip-chip-mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0888464A true JPH0888464A (en) | 1996-04-02 |
Family
ID=16813287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22440794A Withdrawn JPH0888464A (en) | 1994-09-20 | 1994-09-20 | Flip-chip-mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0888464A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001020676A1 (en) * | 1999-09-14 | 2001-03-22 | Alpha Metals, Inc. | Flip chip having integral mask and underfill providing two-stage bump formation |
| WO2002058108A3 (en) * | 2000-11-14 | 2003-03-13 | Henkel Loctite Corp | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
| EP1504468A2 (en) * | 2001-03-28 | 2005-02-09 | Freescale Semiconductor, Inc. | Microelectronic assembly with die support and method |
| US7408785B2 (en) | 2004-05-18 | 2008-08-05 | Alps Electric Co., Ltd | Structure for mounting electronic component on wiring board |
| WO2009081648A1 (en) * | 2007-12-21 | 2009-07-02 | Murata Manufacturing Co., Ltd. | Method for manufacturing element mounting substrate |
-
1994
- 1994-09-20 JP JP22440794A patent/JPH0888464A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001020676A1 (en) * | 1999-09-14 | 2001-03-22 | Alpha Metals, Inc. | Flip chip having integral mask and underfill providing two-stage bump formation |
| WO2002058108A3 (en) * | 2000-11-14 | 2003-03-13 | Henkel Loctite Corp | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
| US7109061B2 (en) | 2000-11-14 | 2006-09-19 | Henkel Corporation | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
| EP1504468A2 (en) * | 2001-03-28 | 2005-02-09 | Freescale Semiconductor, Inc. | Microelectronic assembly with die support and method |
| EP1504468A4 (en) * | 2001-03-28 | 2005-05-25 | Freescale Semiconductor Inc | Microelectronic assembly with die support and method |
| US7408785B2 (en) | 2004-05-18 | 2008-08-05 | Alps Electric Co., Ltd | Structure for mounting electronic component on wiring board |
| WO2009081648A1 (en) * | 2007-12-21 | 2009-07-02 | Murata Manufacturing Co., Ltd. | Method for manufacturing element mounting substrate |
| JP5282981B2 (en) * | 2007-12-21 | 2013-09-04 | 株式会社村田製作所 | Device mounting substrate manufacturing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20011120 |