JPH1074887A - Electronic part and its manufacture - Google Patents

Electronic part and its manufacture

Info

Publication number
JPH1074887A
JPH1074887A JP8231049A JP23104996A JPH1074887A JP H1074887 A JPH1074887 A JP H1074887A JP 8231049 A JP8231049 A JP 8231049A JP 23104996 A JP23104996 A JP 23104996A JP H1074887 A JPH1074887 A JP H1074887A
Authority
JP
Japan
Prior art keywords
substrate
chip
main surface
spacer
chip component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8231049A
Other languages
Japanese (ja)
Inventor
Takahisa Yoshimura
隆央 吉村
Mutsusada Itou
睦禎 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP8231049A priority Critical patent/JPH1074887A/en
Publication of JPH1074887A publication Critical patent/JPH1074887A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable mounting of a chip part on a solder ball formation side for improving its mounting density. SOLUTION: Chip parts 3, 6, 8 and 11 are mounted on opposing major surfaces 1a and 1b of a substrate 1 respectively, and spacers 12 and 13 which are higher in level than the mounted chip parts 8 and 11 are mounted also on the major surface 1b. The spacers 12 and 13 are arranged so that one major surfaces 12a and 13a of the spacers facing the substrate are conducted with major surfaces 12b and 13b thereof opposed thereto, solder balls 17 and 21 are placed on the spacers 12 and 13 to be connected with the chip parts 3, 6, 8, and 11 through the spacer 12 and 13, and function as terminals for interconnection with the external devices.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、基板上にベアチッ
プを搭載し、このベアチップと電気的に接続されるラン
ドを基板のベアチップ実装面と反対側の面に形成してお
き、上記ランド上に端子としてはんだボールを配した、
いわゆるボールグリッドアレイタイプの電子部品に関す
る。詳しくは、はんだボール形成面側にもベアチップを
実装可能とし、実装密度を向上させた電子部品に係わる
ものである。
The present invention relates to a method of mounting a bare chip on a substrate, forming a land electrically connected to the bare chip on a surface of the substrate opposite to the surface on which the bare chip is mounted, and mounting the land on the land. Arranged solder balls as terminals,
The present invention relates to a so-called ball grid array type electronic component. More specifically, the present invention relates to an electronic component in which a bare chip can be mounted on the solder ball forming surface side and the mounting density is improved.

【0002】[0002]

【従来の技術】ICパッケージ等の各種チップ部品がプ
リント配線がなされる基板に搭載されてなる電子部品に
おいては、面実装技術の急速な発展により、チップ部品
の高密度実装化が進められている。そこで、ICパッケ
ージの小型化等が進められているものの、現在以上の高
密度実装化は難しい。これに対し、近年においては、I
CチップをICパッケージから出して直接基板に実装す
る、いわゆるベア・チップ実装が検討されている。
2. Description of the Related Art With the rapid development of surface mounting technology, high-density mounting of chip components has been promoted in electronic components in which various chip components such as IC packages are mounted on a printed wiring board. . Thus, although the miniaturization of IC packages and the like are being promoted, it is difficult to achieve higher-density mounting than at present. In contrast, in recent years, I
So-called bare chip mounting, in which a C chip is taken out of an IC package and mounted directly on a substrate, is being studied.

【0003】そして、上記のベア・チップ実装を行う方
法としては、例えば、ボールグリッドアレイ方式(以
下、BGA方式と称する。)が挙げられる。上記BGA
方式は、ベアチップとされるICチップにおいて、プリ
ント配線がなされる基板をマザーボードと称されるプリ
ント配線板対向面側に配し、この基板のプリント配線板
対向面側にICチップの端子部と接続されるとともに、
外部との接続端子となる第2のランドを形成し、この第
2のランドにはんだボールをマウントしたボールグリッ
ドアレイタイプの電子部品(以下、BGAと称する。)
を用意しておき、上記はんだボールを溶融固化させてB
GAのランドとマザーボードと称されるプリント配線板
のランド間を接続し、当該プリント配線板上にBGAを
実装するものである。すなわち、上記BGAにおいて
は、はんだボールが実質的な外部との接続端子として機
能することとなる。
As a method for performing the above-described bare chip mounting, for example, a ball grid array system (hereinafter, referred to as a BGA system) can be cited. BGA above
In the method, in an IC chip that is a bare chip, a substrate on which printed wiring is performed is arranged on a printed wiring board facing surface side called a motherboard, and a terminal portion of the IC chip is connected to the printed wiring board facing surface side of this substrate. As well as
A ball grid array type electronic component (hereinafter, referred to as BGA) having a second land formed as a connection terminal with the outside and a solder ball mounted on the second land.
Is prepared, and the solder ball is melted and solidified, and B
The land of the GA is connected to the land of a printed wiring board called a motherboard, and a BGA is mounted on the printed wiring board. That is, in the BGA, the solder ball functions as a substantial connection terminal with the outside.

【0004】なお、上記BGAの基板においては、一主
面にICチップの端子部に対応し、これに接続されるよ
うな第1のランドが形成され、相対向する主面に上記第
1のランドと配線回路パターンにより接続される第2の
ランドが形成されており、第1のランドにICチップの
端子部を接続することによりICチップの端子部と第2
のランドが接続されるようになされている。すなわち、
上記BGA方式においては、ICチップの端子部を基板
を介して外部に引き出すこととなり、外部との接続端子
となる第2のランドの形成位置を比較的自由に決定する
ことが可能である。
In the BGA substrate, a first land corresponding to a terminal portion of an IC chip is formed on one main surface and connected to the terminal portion, and the first land is formed on an opposing main surface. A second land connected to the land by a wiring circuit pattern is formed, and the terminal of the IC chip is connected to the second land by connecting the terminal of the IC chip to the first land.
Are connected to each other. That is,
In the BGA method, the terminal portion of the IC chip is drawn out to the outside via the substrate, and the position of the second land serving as a connection terminal with the outside can be relatively freely determined.

【0005】上記BGAの具体的な形状としては、以下
に示すようなものが挙げられる。すなわち、図17に示
すように、基板101の一主面101a側にICチップ
のベアチップであるチップ部品102が搭載されてな
り、基板101の一主面101aに相対向する他方の主
面101b側にはんだボール103が形成されてなるも
のが挙げられる。上記チップ部品102はワイヤ104
によりワイヤボンディングされて基板101の一主面1
01a上の図示しない配線回路パターンに接続されてお
り、この配線回路パターンは基板101の一主面101
aに相対向する一主面101bに形成されている図示し
ないランドに接続されている。従って、チップ部品10
2と一主面101bに形成されているランドは電気的に
接続されており、はんだボール103が外部との接続端
子として機能することとなる。
[0005] Specific examples of the shape of the BGA include the following. That is, as shown in FIG. 17, a chip component 102 which is a bare chip of an IC chip is mounted on one main surface 101a side of a substrate 101, and the other main surface 101b side opposite to one main surface 101a of the substrate 101. In which a solder ball 103 is formed. The chip component 102 is a wire 104
Main surface 1 of substrate 101 by wire bonding
01a is connected to a wiring circuit pattern (not shown) on the main surface 101 of the substrate 101.
It is connected to a land (not shown) formed on one main surface 101b opposite to a. Therefore, the chip component 10
2 and the land formed on one main surface 101b are electrically connected, and the solder ball 103 functions as a connection terminal with the outside.

【0006】このようなBGAを一主面101b側から
見た図を図18に示すが、はんだボール103は例えば
図18中に示すように、基板101の四辺に沿うように
して形成されている。
FIG. 18 shows such a BGA as viewed from one main surface 101b side. Solder balls 103 are formed along the four sides of the substrate 101, for example, as shown in FIG. .

【0007】また、図17中に示すように、チップ部品
102に対してはこれを保護するために封止剤105を
配するようにしており、一主面101a側から見た図を
図19に示すが、封止剤105はチップ部品102を完
全に覆うように配されている。
As shown in FIG. 17, a sealant 105 is provided for the chip component 102 in order to protect the chip component 102. FIG. As shown in FIG. 5, the sealant 105 is disposed so as to completely cover the chip component 102.

【0008】そして、このようなBGAは、図20に示
すように、はんだボール103によりマザーボード10
6の一主面106a上の図示しない配線回路パターン中
のランドに対してはんだ付けすることにより実装され
る。
[0010] As shown in FIG. 20, such a BGA is formed by solder balls 103 on motherboard 10.
6 is mounted by soldering to a land in a wiring circuit pattern (not shown) on one main surface 106a.

【0009】[0009]

【発明が解決しようとする課題】ところで、このような
BGAといった電子部品においては実装密度を更に向上
させることが望まれている。そこで、図18に示すよう
な基板101の一主面101b側のはんだボール103
が形成されていない部分へもチップ部品を搭載すること
が考えられている。しかしながら、現在、はんだボール
103の高さは760μm程度と非常に小さく、このは
んだボール103形成面側にチップ部品を搭載すると、
チップ部品の高さがはんだボール103の高さよりも高
い場合が多く、はんだボール103によるマザーボード
106へのはんだ付けが不可能となってしまい、実現は
困難である。
By the way, it is desired to further improve the mounting density of such electronic components as BGA. Therefore, the solder ball 103 on one main surface 101b side of the substrate 101 as shown in FIG.
It has been considered that a chip component is also mounted on a portion where no is formed. However, at present, the height of the solder ball 103 is extremely small, about 760 μm, and when a chip component is mounted on the solder ball 103 forming surface side,
In many cases, the height of the chip component is higher than the height of the solder ball 103, so that soldering to the mother board 106 by the solder ball 103 becomes impossible, and it is difficult to realize.

【0010】さらには、様々な種類のチップ部品が実装
されるマルチ・チップ・モジュールにおいては、通常の
実装方法では小型化が困難で、上記のように基板の両面
への実装が強く望まれている。
Further, in a multi-chip module on which various types of chip components are mounted, it is difficult to reduce the size by a normal mounting method, and mounting on both sides of a substrate is strongly desired as described above. I have.

【0011】そこで本発明は、従来の実情に鑑みて提案
されたものであり、はんだボール形成面側へのチップ部
品の実装を可能とし、実装密度の向上を可能とする電子
部品及びその製造方法を提供することを目的とする。
In view of the above, the present invention has been proposed in view of the conventional situation, and an electronic component and a method of manufacturing the electronic component, which enable mounting of a chip component on a solder ball forming surface side and increase in mounting density. The purpose is to provide.

【0012】[0012]

【課題を解決するための手段】上述の目的を達成するた
めに本発明の電子部品は、基板の両面にチップ部品を搭
載し、これらのうち一方の主面にはチップ部品よりも高
さが高いスペーサーも搭載し、このスペーサーを、基板
対向面とこれに相対向する主面間が導通されたものと
し、スペーサー上にはんだボールを配し、当該スペーサ
ーを介してチップ部品と接続され、外部との接続端子と
して機能するはんだボールを配するようにしたことを特
徴とするものである。
In order to achieve the above object, an electronic component according to the present invention has chip components mounted on both sides of a substrate, and one of these main surfaces has a height higher than that of the chip component. A high spacer is also mounted, this spacer is assumed to be electrically connected between the substrate facing surface and the main surface facing the substrate, solder balls are arranged on the spacer, connected to chip components via the spacer, and external And a solder ball functioning as a connection terminal with the solder ball.

【0013】このとき、上記スペーサーは、平面長方形
のチップ状部材であることが好ましく、基板上の必要な
部分のみに配されるようにすれば良い。
At this time, it is preferable that the spacer is a chip-shaped member having a flat rectangular shape, and it is sufficient to dispose the spacer only on a necessary portion on the substrate.

【0014】また、本発明の電子部品を製造する製造方
法としては、基板の一方の主面上にチップ部品を搭載す
る工程と、基板の他方の主面上にチップ部品を搭載する
工程と、この主面上に、搭載されているチップ部品より
も高さが高く、基板対向面とこれに相対向する主面間が
導通されており、基板対向面に相対向する主面上にはん
だボールが配されてなるスペーサーを搭載する工程とを
有することを特徴とするものが挙げられる。
Further, a method of manufacturing an electronic component according to the present invention includes a step of mounting a chip component on one main surface of a substrate, a step of mounting a chip component on the other main surface of the substrate, On this main surface, the height is higher than the mounted chip component, and the conduction between the substrate facing surface and the main surface facing the substrate is conducted, and the solder ball is placed on the main surface facing the substrate facing surface. And a step of mounting a spacer on which is disposed.

【0015】そして、この製造工程中、基板の主面のう
ち、チップ部品とスペーサーが搭載される主面に、チッ
プ部品及びスペーサーをはんだ付けにより搭載する際に
は、これらの加熱処理を同時に行うことが好ましい。
During the manufacturing process, when the chip component and the spacer are mounted on the main surface of the substrate on which the chip component and the spacer are mounted by soldering, these heat treatments are performed simultaneously. Is preferred.

【0016】本発明の電子部品においては、基板の両面
にチップ部品を搭載し、この中の一方の主面側に、この
面に搭載されているチップ部品よりも高さが高いスペー
サーを搭載し、この上に外部との接続端子として機能す
るはんだボールを配することから、はんだボール形成面
側のチップ部品がはんだボールによるはんだ付けを妨げ
ることはない。
In the electronic component of the present invention, chip components are mounted on both sides of the substrate, and a spacer having a height higher than the chip components mounted on this surface is mounted on one of the main surfaces. Since the solder ball functioning as a connection terminal with the outside is arranged thereon, the chip component on the solder ball forming surface side does not hinder the soldering by the solder ball.

【0017】また、このスペーサーを平面長方形のチッ
プ状部材とすれば、基板の必要な部分にのみスペーサー
を形成することが容易となる。
Further, if the spacer is a chip-shaped member having a flat rectangular shape, it is easy to form the spacer only on a necessary portion of the substrate.

【0018】[0018]

【発明の実施の形態】以下、本発明の具体的な実施の形
態について図面を参照しながら詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

【0019】本例の電子部品は、図1に示すようなもの
である。すなわち、平面四角形の基板1の一主面1a側
に、はんだ2により固定されるとともに基板1の図示し
ない配線回路パターンに対して電気的な接続が確保され
ているチップ部品3や図示しないダイボンド剤により固
定されてワイヤ4により基板1の図示しない配線回路パ
ターンに対して電気的な接続が確保されて封止剤5によ
り封止されているIC等のチップ部品6が搭載されてい
る。
The electronic component of this embodiment is as shown in FIG. That is, a chip component 3 or a die bonding agent (not shown), which is fixed on one principal surface 1a side of the substrate 1 having a planar rectangular shape by solder 2 and which is electrically connected to a wiring circuit pattern (not shown) of the substrate 1. A chip component 6 such as an IC, which is secured by a wire 4 and secured by a wire 4 to a wiring circuit pattern (not shown) of the substrate 1 and sealed by a sealant 5, is mounted.

【0020】そして、本例の電子部品においては特に、
基板1の上記一主面1aに相対向する一主面1b側の略
中心部にも、はんだ7により固定されるとともに基板1
の図示しない配線回路パターンに対して電気的な接続が
確保されているチップ部品8や図示しないダイボンド剤
により固定されてワイヤ9により基板1の図示しない配
線回路パターンに対して電気的な接続が確保されて封止
剤10により封止されているIC等のチップ部品11が
搭載されている。
In the electronic component of this embodiment,
The substrate 1 is also fixed to the substantially central portion on the one main surface 1b side opposite to the one main surface 1a of the substrate 1 by the solder 7, and
Of the substrate 1 is secured by a die bonding agent (not shown) and electrically connected to a wiring circuit pattern (not shown) of the substrate 1. Then, a chip component 11 such as an IC sealed with a sealing agent 10 is mounted.

【0021】さらに、本例の電子部品においては、基板
1の一主面1b側にチップ部品8及び封止剤10により
封止された状態のチップ部品11よりも高さが高い平面
長方形のスペーサー12,13が基板1の四辺を囲むよ
うにして(ただし、図1中においては、二辺のみを示
す。)配されている。
Further, in the electronic component of this embodiment, a flat rectangular spacer having a height higher than that of the chip component 8 sealed with the chip component 8 and the sealing agent 10 on the one main surface 1 b side of the substrate 1. The substrates 12 and 13 are arranged so as to surround four sides of the substrate 1 (however, only two sides are shown in FIG. 1).

【0022】上記スペーサー12は、スルーホール14
を有し、基板対向面となる一主面12aとこれに相対向
する主面12bにそれぞれ形成されるランド15,16
間の電気的な接続が可能となされている。そして、基板
対向面となる一主面12aに相対向する主面12bのラ
ンド16上にはんだボール17が配されている。
The spacer 12 has a through hole 14
And lands 15 and 16 formed on one main surface 12a to be a substrate facing surface and main surface 12b opposed thereto, respectively.
The electrical connection between them is made possible. The solder balls 17 are arranged on the lands 16 on the main surface 12b opposed to the one main surface 12a serving as the substrate facing surface.

【0023】一方のスペーサー13も同様であり、スル
ーホール18を有し、基板対向面となる一主面13aと
これに相対向する主面13bにそれぞれ形成されるラン
ド19,20間の電気的な接続が可能となされている。
そして、基板対向面となる一主面13aに相対向する主
面13bのランド20上にはんだボール21が配されて
いる。
Similarly, one spacer 13 has a through hole 18 and has an electrical connection between lands 19 and 20 formed on one main surface 13a, which is a substrate facing surface, and a main surface 13b opposed thereto. Connection is possible.
The solder balls 21 are arranged on the lands 20 on the main surface 13b facing the one main surface 13a serving as the substrate facing surface.

【0024】さらに、これらスペーサー12,13にお
いては、はんだ22,23により基板対向面となる一主
面12a,13a側のランド15,19が基板1の図示
しない配線回路パターンに接続されている。
Further, in the spacers 12 and 13, the lands 15 and 19 on one of the principal surfaces 12a and 13a, which are the substrate facing surfaces, are connected to a wiring circuit pattern (not shown) of the substrate 1 by solders 22 and 23.

【0025】そして、基板1においては、チップ部品
3,6,8,11から導出された端子がランド15,1
9に接続されるような配線回路パターンが形成されてい
る。
In the substrate 1, the terminals derived from the chip components 3, 6, 8, 11 are connected to the lands 15, 1
9 is formed.

【0026】従って、各チップ部品3,6,8,11か
ら導出された端子は基板1の一主面1b側の図示しない
配線回路パターンに集積され、この配線回路パターンに
接続されるスペーサー12,13を介してスペーサー1
2,13の表面に形成されて外部への接続端子として機
能するはんだボール17,21に接続されることとな
る。
Therefore, the terminals derived from each of the chip components 3, 6, 8, and 11 are integrated in a wiring circuit pattern (not shown) on the one main surface 1b side of the substrate 1, and the spacers 12 and 13 through spacer 1
The solder balls 17 and 21 are formed on the surfaces of the solder balls 17 and 21 and function as external connection terminals.

【0027】すなわち、本例の電子部品を基板1の一主
面1b側から見ると、基板1の四辺に沿ってスペーサー
が配され、図18に示したような形状にはんだボールが
形成されることとなる。そして、基板の略中心部のはん
だボールが形成されない部分にチップ部品8,11が配
されていることとなる。
That is, when the electronic component of this embodiment is viewed from the one main surface 1b side of the substrate 1, spacers are arranged along four sides of the substrate 1, and solder balls are formed in a shape as shown in FIG. It will be. Then, the chip components 8 and 11 are arranged at a substantially central portion of the substrate where no solder ball is formed.

【0028】本例の電子部品をマザーボードに搭載した
状態を図2に示す。本例の電子部品においては、はんだ
ボール17,21を溶融固化させることによりマザーボ
ード24の一主面24a上の図示しない配線回路パター
ンに電気的に接続するとともに固定して実装を行う。こ
のとき、本例の電子部品においては、はんだボール1
7,21が一主面1b側に配されるチップ部品8及び封
止剤10により封止された状態のチップ部品11よりも
高さが高いスペーサー12,13の上に配されており、
一主面1b側にチップ部品8,11を配しても、はんだ
ボール17,21によるはんだ付けを妨げることはな
い。
FIG. 2 shows a state in which the electronic component of this embodiment is mounted on a motherboard. In the electronic component of the present embodiment, the solder balls 17, 21 are melted and solidified to be electrically connected and fixed to a wiring circuit pattern (not shown) on one main surface 24a of the motherboard 24, and mounted. At this time, in the electronic component of this example, the solder ball 1
7, 21 are disposed on spacers 12, 13 which are higher than the chip component 8 disposed on the one main surface 1b side and the chip component 11 sealed with the sealing agent 10,
Even if the chip components 8 and 11 are arranged on the one main surface 1b side, the soldering by the solder balls 17 and 21 is not hindered.

【0029】従って基板1の両面にチップ部品を搭載す
ることが可能となり、実装密度を向上させることが可能
となる。
Therefore, chip components can be mounted on both sides of the substrate 1, and the mounting density can be improved.

【0030】また、本例の電子部品のようにスペーサー
12,13を平面長方形のチップ状部材とすれば、基板
1の必要な部分にのみスペーサー12,13を形成する
ことが可能であり、本例中に示したようにはんだボール
17,21を基板1の四辺に沿って形成するようにし、
その内側にチップ部品8,11を配するようにする等、
形状の変更が容易である。
Further, if the spacers 12 and 13 are formed as planar rectangular chip-shaped members as in the electronic component of the present embodiment, it is possible to form the spacers 12 and 13 only on necessary portions of the substrate 1. As shown in the example, the solder balls 17, 21 are formed along the four sides of the substrate 1,
The chip components 8 and 11 are arranged inside the
It is easy to change the shape.

【0031】次に、本例の電子部品の製造方法について
述べる。先ず、スペーサーの製造方法について述べる。
なお、ここではスペーサー12を例にとって説明する。
すなわち、図3(a),(b)に示すように、基板対向
面となる一主面12aからこれに相対向する一主面12
bにわたって形成される貫通孔であり、内壁面に図示し
ない導電膜が形成されているスルーホール14が形成さ
れ、このスルーホール14の上下の開口部に対応する位
置に導電性を有する平面円形のパターンであるランド1
5,16が形成されて一主面12aのランド15と一主
面12bのランド16間の導通がなされたスペーサー1
2を用意する。なお、このスペーサー12においては、
スルーホール14の内部に紫外線硬化型樹脂等の樹脂2
5が充填されている。
Next, a method for manufacturing the electronic component of this embodiment will be described. First, a method for manufacturing a spacer will be described.
Here, the spacer 12 will be described as an example.
In other words, as shown in FIGS. 3A and 3B, one main surface 12a which is the substrate facing surface is shifted from one main surface 12a facing the substrate.
b, a through hole 14 in which a conductive film (not shown) is formed on the inner wall surface, and a conductive circular flat hole is formed at a position corresponding to the upper and lower openings of the through hole 14. Land 1 which is a pattern
Spacer 1 in which lands 15 on one main surface 12a and lands 16 on one main surface 12b are formed and conduction is established between them.
Prepare 2 In addition, in this spacer 12,
Resin 2 such as an ultraviolet curable resin is provided inside through hole 14.
5 are filled.

【0032】次いで、図4に示すように、基板対向面と
なる一主面12aと反対側の主面12bの全面に図示し
ないフラックスを塗布してランド16上にはんだボール
17を載置する。その後、リフローと称される加熱処理
を行ってはんだボール17とランド16間を接続し、残
存フラックスの洗浄を行ってスペーサー12を完成す
る。そして、これと同様にしてスペーサー13も製造す
る。
Next, as shown in FIG. 4, a flux (not shown) is applied to the entire surface of the main surface 12b opposite to the one main surface 12a which is the substrate facing surface, and the solder balls 17 are mounted on the lands 16. Thereafter, a heat treatment called reflow is performed to connect the solder balls 17 and the lands 16, and the remaining flux is washed to complete the spacer 12. Then, the spacer 13 is manufactured in the same manner.

【0033】次に、図5に示すように相対向する一主面
1a,1bに図示しない所定の配線回路パターンが形成
され、必要に応じてこれらが接続されている基板1を用
意する。次に、この基板1のはんだボールを形成しない
側の面となる一主面1aのはんだ付けによる実装を行う
チップ部品の実装位置に、例えばスクリーン印刷によ
り、クリームはんだ26を塗布する。
Next, as shown in FIG. 5, a predetermined wiring circuit pattern (not shown) is formed on the opposing main surfaces 1a and 1b, and a substrate 1 to which these are connected as necessary is prepared. Next, a cream solder 26 is applied, for example, by screen printing, to the mounting position of the chip component to be mounted by soldering on one main surface 1a of the substrate 1 on the side where the solder balls are not formed.

【0034】次に、図6に示すように、所定の位置に塗
布されたクリームはんだ26上にはんだ付けにより実装
されるチップ部品3を載置する。そして、リフローと称
される加熱処理を行い、クリームはんだ26を溶融固化
させて、図7に示すようにチップ部品3をはんだ2によ
り固定するとともに基板1の一主面1aの図示しない配
線回路パターンと電気的な接続を確保してチップ部品3
を実装する。
Next, as shown in FIG. 6, the chip component 3 to be mounted by soldering is placed on the cream solder 26 applied to a predetermined position. Then, a heat treatment called reflow is performed to melt and solidify the cream solder 26, fix the chip component 3 with the solder 2 as shown in FIG. And electrical connection with the chip component 3
Implement

【0035】次に、図8に示すように、基板1の一主面
1a側にIC等のチップ部品6を図示しないダイボンド
剤を塗布した上に載置し、これにキュアーと称される加
熱処理を例えば125℃×1時間の条件で施してチップ
部品6を基板1上に接着する。
Next, as shown in FIG. 8, a chip component 6 such as an IC is placed on one main surface 1a side of the substrate 1 after applying a die bonding agent (not shown) thereto, and a heating called a cure is performed. The processing is performed, for example, under the condition of 125 ° C. × 1 hour, and the chip component 6 is bonded onto the substrate 1.

【0036】続いて、図9に示すように、チップ部品6
の端子と基板1の一主面1a上の図示しない配線回路パ
ターン間を金又はアルミニウム等よりなるワイヤー4に
よりワイヤボンディングして、これらの間の電気的な接
続を確保する。
Subsequently, as shown in FIG.
Is bonded by wire 4 made of gold or aluminum or the like between the terminal and the wiring circuit pattern (not shown) on one main surface 1a of the substrate 1 to secure an electrical connection therebetween.

【0037】さらに、チップ部品6を樹脂である封止剤
により覆い、これにキュアーと称される加熱処理を施し
て、図10に示すように、チップ部品6を封止剤5によ
り封止する。
Further, the chip component 6 is covered with a sealing agent, which is a resin, and is subjected to a heat treatment called curing, and the chip component 6 is sealed with the sealing agent 5 as shown in FIG. .

【0038】次に、基板1を裏返して、図11に示すよ
うに、基板1の一主面1aと相対向する一主面1bのは
んだ付けによる実装を行うチップ部品の実装位置に、例
えばスクリーン印刷により、クリームはんだ27を塗布
し、スペーサーの実装位置にもクリームはんだ28を塗
布する。
Next, as shown in FIG. 11, the substrate 1 is turned upside down and, for example, a screen is placed at a mounting position of a chip component for mounting by soldering one main surface 1b opposite to one main surface 1a of the substrate 1. The cream solder 27 is applied by printing, and the cream solder 28 is also applied to the mounting position of the spacer.

【0039】続いて、図12に示すように、基板1の一
主面1bのはんだ付けによる実装を行うチップ部品の実
装位置に塗布されたクリームはんだ27の上にチップ部
品8を載置する。そして、リフローと称される加熱処理
を行い、クリームはんだ27を溶融固化させて、図13
に示すようにチップ部品8をはんだ7により固定すると
ともに基板1の一主面1bの図示しない配線回路パター
ンと電気的な接続を確保してチップ部品8を実装する。
Subsequently, as shown in FIG. 12, the chip component 8 is placed on the cream solder 27 applied to the mounting position of the chip component to be mounted on one main surface 1b of the substrate 1 by soldering. Then, a heat treatment called a reflow is performed to melt and solidify the cream solder 27, and FIG.
As shown in FIG. 7, the chip component 8 is fixed by the solder 7 and the chip component 8 is mounted while securing electrical connection with a wiring circuit pattern (not shown) on the one main surface 1b of the substrate 1.

【0040】さらに、図13中に示すように、基板1の
一主面1b側にIC等のチップ部品11を図示しないダ
イボンド剤を塗布した上に載置し、これにキュアーと称
される加熱処理を例えば125℃×1時間の条件で施し
てチップ部品11を基板1上に接着する。
Further, as shown in FIG. 13, a chip component 11 such as an IC is placed on one principal surface 1b side of the substrate 1 after applying a die bonding agent (not shown), and a heating called a cure is performed. The processing is performed under the conditions of, for example, 125 ° C. × 1 hour, and the chip component 11 is bonded to the substrate 1.

【0041】続いて、図14に示すように、チップ部品
11の端子と基板1の一主面1b上の図示しない配線回
路パターン間を金又はアルミニウム等よりなるワイヤー
9によりワイヤボンディングして、これらの間の電気的
な接続を確保する。
Subsequently, as shown in FIG. 14, the terminals of the chip component 11 and the wiring circuit patterns (not shown) on the one main surface 1b of the substrate 1 are wire-bonded by wires 9 made of gold or aluminum. To secure the electrical connection between

【0042】さらに、チップ部品11を樹脂である封止
剤により覆い、これにキュアーと称される加熱処理を施
して、図15に示すように、チップ部品11を封止剤1
0により封止する。
Further, the chip component 11 is covered with a sealant, which is a resin, and is subjected to a heat treatment called curing, so that the chip component 11 is covered with the sealant 1 as shown in FIG.
Seal with 0.

【0043】そして最後に、図16に示すように、基板
1の一主面1bのスペーサー実装位置に配されているク
リームはんだ28上に、先に述べた方法で製造されたス
ペーサー12,13を載置し、リフローと称される加熱
処理を行って、図1に示すような本例の電子部品を完成
する。
Finally, as shown in FIG. 16, the spacers 12, 13 manufactured by the above-described method are placed on the cream solder 28 disposed at the spacer mounting position on one main surface 1b of the substrate 1. The electronic component of this example as shown in FIG. 1 is completed by mounting and performing a heating process called reflow.

【0044】本例の電子部品においては、スペーサー1
2,13を平面長方形のチップ状部材としていることか
ら、通常のチップ部品と同様にしてスペーサー12,1
3を基板上に配することが可能であり、従来の製造工程
を大幅に変更することなく、製造することが可能であ
る。
In the electronic component of this embodiment, the spacer 1
Since the chip members 2 and 13 are flat rectangular chip members, the spacers 12 and 1 are formed in the same manner as a normal chip component.
3 can be arranged on a substrate, and can be manufactured without significantly changing a conventional manufacturing process.

【0045】また、本例の電子部品を製造する際に、基
板1の一主面1b側のチップ部品8のリフローとスペー
サー12,13のリフローと称される加熱処理を同時に
行うようにしても良く、製造工程が短縮され、好まし
い。
When the electronic component of this embodiment is manufactured, a heat treatment called reflow of the chip component 8 on one main surface 1b side of the substrate 1 and reflow of the spacers 12 and 13 may be performed simultaneously. It is preferable because the manufacturing process is shortened.

【0046】[0046]

【発明の効果】以上の説明からも明らかなように、本発
明の電子部品においては、基板の両面にチップ部品を搭
載し、この中の一方の主面側に、この面に搭載されてい
るチップ部品よりも高さが高いスペーサーを搭載し、こ
の上に外部との接続端子として機能するはんだボールを
配しており、はんだボール形成面側のチップ部品がはん
だボールによるはんだ付けを妨げることはなく、基板の
両面を使用して実装密度を向上することが可能となる。
As is apparent from the above description, in the electronic component of the present invention, chip components are mounted on both sides of the substrate, and one of the main surfaces is mounted on this surface. A spacer that is higher than the chip component is mounted, and solder balls that function as connection terminals with the outside are arranged on this.The chip component on the solder ball forming surface side does not prevent soldering with solder balls. Instead, the mounting density can be improved by using both sides of the substrate.

【0047】また、このスペーサーを平面長方形のチッ
プ状部材とすれば、基板の必要な部分にのみスペーサー
を形成することが容易となるとともに、製造工程を大幅
に変更することなく製造を行うことが可能であり、その
工業的価値は非常に高い。
Further, if the spacer is a chip-shaped member having a flat rectangular shape, it becomes easy to form the spacer only on a necessary portion of the substrate, and it is possible to carry out the manufacturing without largely changing the manufacturing process. It is possible and its industrial value is very high.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を適用した電子部品を示す要部概略断面
図である。
FIG. 1 is a schematic sectional view of a main part showing an electronic component to which the present invention is applied.

【図2】本発明を適用した電子部品をマザーボード上に
実装した状態を示す要部概略断面図である。
FIG. 2 is a main part schematic cross-sectional view showing a state where an electronic component to which the present invention is applied is mounted on a motherboard.

【図3】本発明を適用した電子部品の製造方法を工程順
に示すものであり、スペーサーを製造する工程を示す要
部概略平面図及び要部概略断面図である。
FIG. 3 shows a method of manufacturing an electronic component to which the present invention is applied in order of steps, and is a schematic plan view and a schematic cross-sectional view of a main part showing a step of manufacturing a spacer.

【図4】本発明を適用した電子部品の製造方法を工程順
に示すものであり、スペーサー上にはんだボールを配す
る工程を示す要部概略断面図である。
FIG. 4 is a schematic cross-sectional view of a main part showing a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, showing a step of arranging solder balls on spacers.

【図5】本発明を適用した電子部品の製造方法を工程順
に示すものであり、基板の一主面上にクリームはんだを
塗布する工程を示す要部概略断面図である。
FIG. 5 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps and showing a step of applying cream solder on one main surface of a substrate.

【図6】本発明を適用した電子部品の製造方法を工程順
に示すものであり、クリームはんだ上にチップ部品を載
置する工程を示す要部概略断面図である。
FIG. 6 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and showing a step of mounting a chip component on cream solder.

【図7】本発明を適用した電子部品の製造方法を工程順
に示すものであり、チップ部品を実装する工程を示す要
部概略断面図である。
FIG. 7 is a schematic cross-sectional view of a main part showing a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, showing a step of mounting a chip component.

【図8】本発明を適用した電子部品の製造方法を工程順
に示すものであり、チップ部品を基板上に接着する工程
を示す要部概略断面図である。
FIG. 8 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and showing a step of bonding a chip component onto a substrate.

【図9】本発明を適用した電子部品の製造方法を工程順
に示すものであり、チップ部品をワイヤボンディングす
る工程を示す要部概略断面図である。
FIG. 9 is a schematic cross-sectional view of a main part showing a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, showing a step of wire-bonding a chip part.

【図10】本発明を適用した電子部品の製造方法を工程
順に示すものであり、チップ部品を封止剤により封止す
る工程を示す要部概略断面図である。
FIG. 10 is a schematic cross-sectional view of a principal part showing a method of manufacturing an electronic component to which the present invention is applied, in the order of steps, showing a step of sealing a chip component with a sealing agent.

【図11】本発明を適用した電子部品の製造方法を工程
順に示すものであり、基板の他方の主面上にクリームは
んだを塗布する工程を示す要部概略断面図である。
FIG. 11 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps and showing a step of applying cream solder on the other main surface of the substrate.

【図12】本発明を適用した電子部品の製造方法を工程
順に示すものであり、クリームはんだ上にチップ部品を
載置する工程を示す要部概略断面図である。
FIG. 12 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and showing a step of mounting a chip component on cream solder.

【図13】本発明を適用した電子部品の製造方法を工程
順に示すものであり、チップ部品を実装する工程とチッ
プ部品を基板上に接着する工程を示す要部概略断面図で
ある。
FIG. 13 is a schematic cross-sectional view of a main part showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps, showing a step of mounting a chip part and a step of bonding the chip part onto a substrate.

【図14】本発明を適用した電子部品の製造方法を工程
順に示すものであり、チップ部品をワイヤボンディング
する工程を示す要部概略断面図である。
FIG. 14 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and showing a step of wire-bonding a chip component.

【図15】本発明を適用した電子部品の製造方法を工程
順に示すものであり、チップ部品を封止剤により封止す
る工程を示す要部概略断面図である。
FIG. 15 is a schematic cross-sectional view of a main part, illustrating a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and illustrating a step of sealing a chip component with a sealing agent.

【図16】本発明を適用した電子部品の製造方法を工程
順に示すものであり、スペーサーを載置する工程を示す
要部概略断面図である。
FIG. 16 is a schematic cross-sectional view of a main part, showing a method of manufacturing an electronic component to which the present invention is applied in the order of steps, and showing a step of mounting a spacer.

【図17】従来のBGAの構造を示す要部概略断面図で
ある。
FIG. 17 is a schematic cross-sectional view of a main part showing a structure of a conventional BGA.

【図18】従来のBGAの構造を示す要部概略底面図で
ある。
FIG. 18 is a schematic bottom view showing the structure of a conventional BGA.

【図19】従来のBGAの構造を示す要部概略平面図で
ある。
FIG. 19 is a schematic plan view of a main part showing a structure of a conventional BGA.

【図20】従来のBGAをマザーボード上に実装した状
態を示す要部概略断面図である。
FIG. 20 is a schematic cross-sectional view of a main part showing a state where a conventional BGA is mounted on a motherboard.

【符号の説明】 1 基板、1a,1b 一主面、3,6,8,11 チ
ップ部品、12,13スペーサー、14,18 スルー
ホール、17,21 はんだボール
[Description of Signs] 1 substrate, 1a, 1b one main surface, 3, 6, 8, 11 chip components, 12, 13 spacer, 14, 18 through hole, 17, 21 solder ball

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板の両面にチップ部品が搭載され、こ
れらのうち一方の主面にはチップ部品よりも高さが高い
スペーサーが搭載されており、このスペーサーにおいて
は、基板対向面とこれに相対向する主面間が導通されて
おり、当該スペーサーを介してチップ部品の外部との接
続端子であるはんだボールが配されていることを特徴と
する電子部品。
1. A chip component is mounted on both sides of a substrate, and a spacer having a height higher than that of the chip component is mounted on one main surface of the chip components. An electronic component, wherein the opposing main surfaces are electrically connected to each other, and solder balls, which are connection terminals with the outside of the chip component, are arranged via the spacer.
【請求項2】 スペーサーが平面長方形のチップ状部材
であることを特徴とする請求項1記載の電子部品。
2. The electronic component according to claim 1, wherein the spacer is a chip-shaped member having a flat rectangular shape.
【請求項3】 基板の一方の主面上にチップ部品を搭載
する工程と、 基板の他方の主面上にチップ部品を搭載する工程と、 この主面上に、搭載されているチップ部品よりも高さが
高く、基板対向面とこれに相対向する主面間が導通され
ており、基板対向面に相対向する主面上にはんだボール
が配されてなるスペーサーを搭載する工程とを有するこ
とを特徴とする電子部品の製造方法。
A step of mounting a chip component on one main surface of the substrate; a step of mounting a chip component on the other main surface of the substrate; and a step of mounting the chip component on the main surface. And a step of mounting a spacer in which solder balls are arranged on the main surface opposite to the substrate facing surface, in which electrical conduction is provided between the substrate facing surface and the main surface facing the substrate. A method for manufacturing an electronic component, comprising:
【請求項4】 基板の主面のうち、チップ部品とスペー
サーが搭載される主面に、チップ部品及びスペーサーを
はんだ付けにより搭載する際、これらの加熱処理を同時
に行うことを特徴とする請求項3記載の電子部品の製造
方法。
4. When the chip component and the spacer are mounted on the main surface of the substrate on which the chip component and the spacer are mounted by soldering, these heat treatments are performed simultaneously. 3. The method for manufacturing an electronic component according to 3.
JP8231049A 1996-08-30 1996-08-30 Electronic part and its manufacture Withdrawn JPH1074887A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8231049A JPH1074887A (en) 1996-08-30 1996-08-30 Electronic part and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8231049A JPH1074887A (en) 1996-08-30 1996-08-30 Electronic part and its manufacture

Publications (1)

Publication Number Publication Date
JPH1074887A true JPH1074887A (en) 1998-03-17

Family

ID=16917491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8231049A Withdrawn JPH1074887A (en) 1996-08-30 1996-08-30 Electronic part and its manufacture

Country Status (1)

Country Link
JP (1) JPH1074887A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
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WO2000047027A1 (en) * 1999-02-05 2000-08-10 Novatec S.A. Method for making electronic modules with ball connector or with integrated preforms capable of being soldered on a printed circuit and implementing device
JP2005136380A (en) * 2003-10-06 2005-05-26 Elpida Memory Inc Mounting structure and semiconductor device of semiconductor part
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Publication number Priority date Publication date Assignee Title
FR2789541A1 (en) * 1999-02-05 2000-08-11 Novatec Sa Soc METHOD FOR PRODUCING ELECTRONIC MODULES WITH BALL CONNECTOR OR INTEGRATED PREFORM FOR BRAZABLE ON PRINTED CIRCUIT AND DEVICE FOR IMPLEMENTING SAME
WO2000047027A1 (en) * 1999-02-05 2000-08-10 Novatec S.A. Method for making electronic modules with ball connector or with integrated preforms capable of being soldered on a printed circuit and implementing device
US7032306B1 (en) 1999-02-05 2006-04-25 Societe Novatec S.A. Method for producing module
KR100708050B1 (en) * 2002-02-20 2007-04-16 앰코 테크놀로지 코리아 주식회사 semiconductor package
JP4591816B2 (en) * 2003-10-06 2010-12-01 エルピーダメモリ株式会社 Semiconductor device
JP2005136380A (en) * 2003-10-06 2005-05-26 Elpida Memory Inc Mounting structure and semiconductor device of semiconductor part
KR101001816B1 (en) * 2005-10-03 2010-12-15 로무 가부시키가이샤 Hybrid integrated circuit device and method for manufacturing same
JP2007103553A (en) * 2005-10-03 2007-04-19 Rohm Co Ltd Hybrid integrated circuit device and manufacturing method thereof
JP4676855B2 (en) * 2005-10-03 2011-04-27 ローム株式会社 Hybrid integrated circuit device and manufacturing method thereof
WO2007040193A1 (en) * 2005-10-03 2007-04-12 Rohm Co., Ltd. Hybrid integrated circuit device and method for manufacturing same
US7733668B2 (en) 2005-10-03 2010-06-08 Rohm Co., Ltd. Hybrid integrated circuit device and method for manufacturing same
JP2007266249A (en) * 2006-03-28 2007-10-11 Sony Chemical & Information Device Corp Method of manufacturing substrate with electric part
WO2007111290A1 (en) * 2006-03-28 2007-10-04 Sony Chemical & Information Device Corporation Method for manufacturing substrate having electric component
US8402645B2 (en) 2006-03-28 2013-03-26 Sony Chemical & Information Device Corporation Method for producing an electric component-mounted substrate
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JP2011061132A (en) * 2009-09-14 2011-03-24 Zycube:Kk Interposer
JP2011222791A (en) * 2010-04-12 2011-11-04 Murata Mfg Co Ltd Method for manufacturing module substrate
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US10368439B2 (en) 2014-12-26 2019-07-30 Intel Corporation Assembly architecture employing organic support for compact and improved assembly throughput

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