JPH05226416A - Flip chip mounting method - Google Patents
Flip chip mounting methodInfo
- Publication number
- JPH05226416A JPH05226416A JP3167283A JP16728391A JPH05226416A JP H05226416 A JPH05226416 A JP H05226416A JP 3167283 A JP3167283 A JP 3167283A JP 16728391 A JP16728391 A JP 16728391A JP H05226416 A JPH05226416 A JP H05226416A
- Authority
- JP
- Japan
- Prior art keywords
- flux
- flip chip
- substrate
- chip mounting
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、フリップチップの実装
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、沖研究開発 第１３８号、Ｖｏｌ．５５，Ｎ
ｏ．２，第４５〜５０頁に記載されるものがあった。図
３はかかる従来のフリップチップ接続フロー図である。
この図に示すように、基板にフラックスを塗布して、そ
の基板にハンダバンプ付き半導体素子（ＩＣ）を搭載
し、ハンダリフローを行い、その後、樹脂により封止す
るようにしている。2. Description of the Related Art Conventionally, as a technique in such a field,
For example, Oki R & D No. 138, Vol. 55, N
o. 2, pages 45-50. FIG. 3 is a flow chart of such a conventional flip chip connection.
As shown in this figure, flux is applied to a substrate, a semiconductor element (IC) with solder bumps is mounted on the substrate, solder reflow is performed, and then sealing is performed with a resin.
【０００３】図４はかかる従来のフリップチップの概略
実装工程断面図である。図４（ａ）に示すように、フラ
ックス２が塗布された基板１にハンダバンプ４付きＩＣ
３を搭載し、フラックスキュアを行い、その後、ハンダ
リフローを行い、図４（ｂ）に示すように、樹脂５によ
り封止するようにしていた。FIG. 4 is a schematic sectional view of a conventional flip chip mounting process. As shown in FIG. 4A, an IC with solder bumps 4 on the substrate 1 coated with the flux 2
3 was mounted, flux cure was performed, and then solder reflow was performed, and as shown in FIG. 4B, the resin 5 was used for sealing.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、以上述
べた従来のフリップチップの実装方法では、フラックス
の中に含まれている溶剤分が温度上昇によって、突沸が
発生し、搭載されるチップずれの原因となり、実装歩留
を低下させるといった問題があった。本発明は、以上述
べたフラックスの突沸によるチップずれを低減させると
ともに、ＩＣの搭載の際に、フラックスの塗布、ＩＣの
搭載、キュア工程を一括して行ない得るフリップチップ
の実装方法を提供することを目的とする。However, in the conventional flip-chip mounting method described above, the solvent component contained in the flux causes bumping due to the temperature rise and causes the chip misalignment to be mounted. Therefore, there is a problem that the mounting yield is reduced. The present invention provides a flip chip mounting method capable of reducing the chip displacement due to the bumping of the flux as described above, and performing the flux application, the IC mounting, and the curing step collectively when the IC is mounted. With the goal.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために、フリップチップの実装方法において、予
めフラックスを塗布し溶剤分を乾燥させた半導体素子を
用意し、前記フラックスが融ける温度に加熱されている
基板に前記半導体素子を搭載して接続を行なうようにし
たものである。In order to achieve the above object, the present invention provides a semiconductor device in which a flux is applied in advance and a solvent is dried in a flip chip mounting method, and the temperature at which the flux melts is prepared. The semiconductor element is mounted on a substrate which is heated to the above to make connection.
【０００６】[0006]
【作用】本発明によれば、上記したように、予めフラッ
クスを塗布し溶剤分を乾燥させた半導体素子を用意し、
前記フラックスが融ける温度に加熱されている基板に前
記半導体素子を搭載して接続を行なうようにしたので、
ＩＣ搭載の際に、フラックス塗布、ＩＣの搭載、キュア
工程を一括して行なうことができる。According to the present invention, as described above, a semiconductor element prepared by applying flux beforehand and drying the solvent is prepared,
Since the semiconductor element is mounted on the substrate heated to a temperature at which the flux melts, connection is made,
When mounting the IC, the flux application, the IC mounting, and the curing process can be collectively performed.
【０００７】また、予めＩＣにフラックスを塗布して、
溶剤分を乾燥させるようにしたので、ＩＣ搭載時にフラ
ックスに溶剤分が含まれていないため、突沸によるチッ
プずれが生じることがない。Also, by applying flux to the IC in advance,
Since the solvent component is dried, the flux does not contain the solvent component when the IC is mounted, so chip displacement due to bumping does not occur.
【０００８】[0008]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の実施例を示すフ
リップチップの実装工程断面図、図２はそのフリップチ
ップ接続フローを示す図である。まず、図１（ａ）に示
すように、半導体素子（ＩＣ）１１上にハンダバンプ１
２を形成する。Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a sectional view of a flip-chip mounting process showing an embodiment of the present invention, and FIG. 2 is a view showing the flip-chip connection flow. First, as shown in FIG. 1A, a solder bump 1 is formed on a semiconductor element (IC) 11.
Form 2.
【０００９】次に、図１（ｂ）に示すように、フラック
ス１３を塗布し、硬化させる。次に、図１（ｃ）に示す
ように、１００Ｃ°に加熱されている基板１４の電極１
５上にＩＣ１１のハンダバンプ１２の位置合わせを行
う。次いで、図１（ｄ）に示すように、フラックス１３
が塗布されたハンダバンプ１２を有するＩＣ１１を、１
００Ｃ°に加熱されている基板１４にＩＣ１１を搭載し
て接続を行なう。つまり、搭載後フラックス１３が融け
て、基板１４に濡れて、ＩＣ１１が仮固定される。Next, as shown in FIG. 1B, the flux 13 is applied and cured. Next, as shown in FIG. 1C, the electrode 1 of the substrate 14 heated to 100 ° C.
The solder bumps 12 of the IC 11 are aligned on the top surface of the IC 5. Then, as shown in FIG.
1 of the IC 11 having the solder bumps 12 coated with
The IC 11 is mounted on the substrate 14 heated to 00 ° C. to make the connection. That is, the flux 13 melts after mounting, wets the substrate 14, and the IC 11 is temporarily fixed.
【００１０】次いで、図１（ｅ）に示すように、ハンダ
リフローを行い、ハンダバンプ１２を溶かし、基板１４
に接続する。最後に、図１（ｆ）に示すように、接続部
を樹脂からなる封止材１６により封止する。このよう
に、構成するために、従来のように、フラックスの中に
含まれている溶剤分が温度上昇によって、突沸が発生
し、搭載されるチップずれを生じることもなくなり、Ｉ
Ｃ搭載の際、フラックス塗布、ＩＣの搭載、キュア工程
を一括して行なうことができ、工程を簡単にすることが
できる。Next, as shown in FIG. 1 (e), solder reflow is performed to melt the solder bumps 12, and the substrate 14
Connect to. Finally, as shown in FIG. 1F, the connecting portion is sealed with a sealing material 16 made of resin. In this way, because of the configuration, unlike the conventional case, the solvent content contained in the flux does not cause bumping due to the temperature rise, and the mounted chips are not displaced.
When C is mounted, flux coating, IC mounting, and curing steps can be collectively performed, and the steps can be simplified.
【００１１】また、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.
【００１２】[0012]
【発明の効果】以上、説明したように、本発明によれ
ば、予めフラックスを塗布したＩＣを用い、フラックス
が融ける温度に加熱されている基板に前記半導体素子を
搭載することによって、ＩＣ搭載の際に、フラックス塗
布、ＩＣの搭載、キュア工程を一括して行なうことがで
きる。As described above, according to the present invention, by using an IC to which a flux is applied in advance and mounting the semiconductor element on a substrate heated to a temperature at which the flux melts, the IC can be mounted on the substrate. At this time, the flux coating, the IC mounting, and the curing process can be collectively performed.
【００１３】また、予めＩＣにフラックスを塗布して、
溶剤分を乾燥させるようにしたので、ＩＣ搭載時にフラ
ックスに溶剤分が含まれていないため、突沸によるチッ
プずれが生じることがなくなる。従って、ＩＣ実装の歩
留の向上を図ることができる。Further, by applying flux to the IC in advance,
Since the solvent component is dried, the flux does not contain the solvent component when the IC is mounted, so that chip displacement due to bumping does not occur. Therefore, the yield of IC mounting can be improved.
【図１】本発明の実施例を示すフリップチップの実装工
程断面図である。FIG. 1 is a sectional view of a flip chip mounting process showing an embodiment of the present invention.
【図２】本発明の実施例を示すフリップチップの接続フ
ローを示す図である。FIG. 2 is a diagram showing a flip-chip connection flow according to an embodiment of the present invention.
【図３】従来のフリップチップの接続フローを示す図で
ある。FIG. 3 is a diagram showing a connection flow of a conventional flip chip.
【図４】従来のフリップチップの実装工程断面図であ
る。FIG. 4 is a cross-sectional view of a conventional flip chip mounting process.
１１ 半導体素子 １２ ハンダバンプ １３ フラックス １４ 基板 １５ 電極 １８ 封止材 11 semiconductor element 12 solder bump 13 flux 14 substrate 15 electrode 18 encapsulant
Claims (1)
燥させた半導体素子を用意し、 （ｂ）前記フラックスが融ける温度に、加熱されている
基板に前記半導体素子を搭載して接続を行なうことを特
徴とするフリップチップの実装方法。1. A semiconductor element prepared by applying a flux and drying a solvent in advance is prepared. (B) The semiconductor element is mounted on a substrate which is heated to a temperature at which the flux melts, and connections are made. A flip-chip mounting method characterized by performing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3167283A JPH05226416A (en) | 1991-07-09 | 1991-07-09 | Flip chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3167283A JPH05226416A (en) | 1991-07-09 | 1991-07-09 | Flip chip mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05226416A true JPH05226416A (en) | 1993-09-03 |
Family
ID=15846884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3167283A Withdrawn JPH05226416A (en) | 1991-07-09 | 1991-07-09 | Flip chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05226416A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998025297A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Production process of semiconductor device |
| KR100501094B1 (en) * | 1996-12-04 | 2005-12-01 | 세이코 엡슨 가부시키가이샤 | Electronic components and semiconductor devices, and methods of manufacturing them |
| US7109061B2 (en) | 2000-11-14 | 2006-09-19 | Henkel Corporation | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US7726543B2 (en) | 2001-09-14 | 2010-06-01 | Smart Pac Gmbh Technology Services | Method for the production of a soldered joint |
-
1991
- 1991-07-09 JP JP3167283A patent/JPH05226416A/en not_active Withdrawn
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US6730589B2 (en) | 1996-12-04 | 2004-05-04 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Production process of semiconductor device |
| WO1998025297A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US6475896B1 (en) | 1996-12-04 | 2002-11-05 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| KR100501094B1 (en) * | 1996-12-04 | 2005-12-01 | 세이코 엡슨 가부시키가이샤 | Electronic components and semiconductor devices, and methods of manufacturing them |
| US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| JP4513973B2 (en) * | 1996-12-04 | 2010-07-28 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
| US7109061B2 (en) | 2000-11-14 | 2006-09-19 | Henkel Corporation | Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith |
| US7726543B2 (en) | 2001-09-14 | 2010-06-01 | Smart Pac Gmbh Technology Services | Method for the production of a soldered joint |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981008 |