JPH0543294B2 - - Google Patents
Info
- Publication number
- JPH0543294B2 JPH0543294B2 JP28822086A JP28822086A JPH0543294B2 JP H0543294 B2 JPH0543294 B2 JP H0543294B2 JP 28822086 A JP28822086 A JP 28822086A JP 28822086 A JP28822086 A JP 28822086A JP H0543294 B2 JPH0543294 B2 JP H0543294B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead
- bond pad
- wire bond
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 8
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばリードフレーム等の基台上の
チツプを樹脂封止してなるICパツケージに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC package in which a chip on a base such as a lead frame is sealed with a resin.
従来、この種のICパツケージは第３図ａおよ
びｂに示すように構成されている。これを同図に
基づいて概略説明すると、同図において、符号１
で示すものはフレームダイボンドパツド２および
フレームワイヤボンドパツド３を有するリードフ
レーム、４はこのリードフレーム１のフレームダ
イボンドパツド２上に接着剤５によつて固着され
かつパツケージ（図示せず）によつて樹脂封止さ
れチツプ基板６およびチツプパターン７を有する
ICチツプ、８はこのICチツプ４のチツプワイヤ
ボンドパツド９と前記リードフレーム１のフレー
ムワイヤボンドパツド３とを接続するワイヤであ
る
このように構成されたICパツケージを組み立
てるには、接着剤５によつてフレームダイボンド
パツド２上にICチツプ４を固着し、このICチツ
プ４のチツプワイヤボンドパツド９とリードフレ
ーム１のフレームワイヤボンドパツド３とをワイ
ヤ８によつて接続した後、パツケージ（図示せ
ず）によつてICチツプ４を樹脂封止することに
より行われる。
Conventionally, this type of IC package has been constructed as shown in FIGS. 3a and 3b. This will be briefly explained based on the figure. In the figure, reference numeral 1
4 is a lead frame having a frame die bond pad 2 and a frame wire bond pad 3, and 4 is fixed to the frame die bond pad 2 of the lead frame 1 with an adhesive 5 and a package (not shown). It has a chip substrate 6 and a chip pattern 7 sealed with resin.
The IC chip 8 is a wire that connects the chip wire bond pad 9 of this IC chip 4 and the frame wire bond pad 3 of the lead frame 1. After fixing the IC chip 4 on the frame die bond pad 2 with the wire 5 and connecting the chip wire bond pad 9 of the IC chip 4 with the frame wire bond pad 3 of the lead frame 1 with the wire 8. , by sealing the IC chip 4 with resin using a package (not shown).
ところで、この種のICパツケージにおいては、
リードフレーム１の外部接続用リード１ａがIC
チツプ４の周囲に位置付けられているため、それ
だけICの実装面積が大きくなり、パツケージ全
体が大型化するという問題があつた。また、リー
ドフレーム１の外部接続用リード１ａとICチツ
プ４のチツプパターン７とはワイヤ８によつて接
続されているため、ワイヤボンデイング工程後に
行うIC組立工程で外部接続用リード1aおよびIC
チツプ４が相対振動することによりワイヤ８が破
損する虞があつた。
By the way, in this type of IC package,
External connection lead 1a of lead frame 1 is IC
Since it is located around the chip 4, the mounting area of the IC increases accordingly, causing the problem that the overall package becomes larger. Furthermore, since the external connection lead 1a of the lead frame 1 and the chip pattern 7 of the IC chip 4 are connected by the wire 8, the external connection lead 1a and the IC chip pattern 7 of the lead frame 1 are connected by the wire 8.
There was a risk that the wire 8 would be damaged due to the relative vibration of the chip 4.
本発明はこのような事情に鑑みなされたもの
で、パツケージ全体の小型化を図ることができる
と共に、ワイヤボンデイング工程後のIC組立工
程におけるワイヤの破損を防止することができる
ICパツケージを提供するものである。 The present invention was developed in view of these circumstances, and it is possible to reduce the size of the entire package, and also to prevent wire breakage in the IC assembly process after the wire bonding process.
It provides IC packages.
本発明に係るICパツケージは、ICチツプ主面
上で、主面の対向する二辺に沿つてボンデイング
パツドを配置し、このボンデイングパツドに対向
し近接させてリードの一端を配置し、各リードが
互いに交叉しなようにICチツプ主面上に絶縁材
を介して配設し、他端を外部接続用リードとして
ボンデイングパツドが配置された二辺以外の一辺
に配列したものである。
In the IC package according to the present invention, bonding pads are arranged on the main surface of an IC chip along two opposing sides of the main surface, one end of the lead is arranged opposite to and close to the bonding pad, and each The leads are arranged on the main surface of the IC chip via an insulating material so as not to cross each other, and the other end is used as an external connection lead and arranged on one side other than the two sides where the bonding pads are arranged.
また、上記絶縁材をプリント配線板としたもの
である。 Further, the above insulating material is a printed wiring board.
本発明においては、ICの実装面積を小さくす
ることができると共に、ICチツプおよび外部接
続用リードの相対振動を抑止することができる。
In the present invention, the mounting area of the IC can be reduced, and relative vibration between the IC chip and external connection leads can be suppressed.
第１図ａおよびｂは本発明に係るICパツケー
ジを示す平面図と断面図である。同図において、
符号１１で示すものはパツケージ（図示せず）に
よつて封止される矩形状のICチツプで、チツプ
基板１２および基板１２の一主面に設けられたチ
ツプパターン１３とからなり、このうちチツプパ
ターン１３表面上の両側にチツプワイヤボンドパ
ツド１４が形成されている。１５はリードフレー
ム１６の外部接続用リードで、接着剤１７によつ
て前記ICチツプ１１に固定されており、そのリ
ードワイヤボンドパツド１８は前記両チツプワイ
ヤボンドパツド１４間に介在するように前記チツ
プパターン１３の表面上に位置付けられている。
また、各外部接続用リード１５は、ICチツプ１
１におけるチツプワイヤボンドパツド１４が設け
られていない１側方からチツプパターン１３表面
上に延設されている。そして、各外部接続用リー
ド１５のリードワイヤボンドパツド１８は前記チ
ツプワイヤボンドパツド１４の近傍に位置付けら
れている。すなわち、各外部接続用リード１５の
一端はチエプワイヤボンドパツド１４に近接して
配置され、他端がICチツプ１１の一辺の配列さ
れることになる。なお、外部接続用リード１５は
ICチツプ１１から導出した部分が外部リードと
される。１９は、この外部接続用リード１５のリ
ードワイヤボンドパツド１８と前記ICチツプ１
１のチツプワイヤボンドパツド１４とを接続する
ワイヤである。
FIGS. 1a and 1b are a plan view and a sectional view showing an IC package according to the present invention. In the same figure,
11 is a rectangular IC chip sealed by a package (not shown), and is composed of a chip substrate 12 and a chip pattern 13 provided on one main surface of the substrate 12. Chip wire bond pads 14 are formed on both sides of the pattern 13 surface. Reference numeral 15 denotes an external connection lead of the lead frame 16, which is fixed to the IC chip 11 with adhesive 17, and its lead wire bond pad 18 is interposed between both chip wire bond pads 14. It is positioned on the surface of the chip pattern 13.
In addition, each external connection lead 15 connects to the IC chip 1.
The chip wire bond pad 14 in FIG. 1 is extended onto the surface of the chip pattern 13 from one side where the chip wire bond pad 14 is not provided. The lead wire bond pad 18 of each external connection lead 15 is positioned near the chip wire bond pad 14. That is, one end of each external connection lead 15 is placed close to the chip wire bond pad 14, and the other end is arranged on one side of the IC chip 11. Note that the external connection lead 15 is
The portion led out from the IC chip 11 is used as an external lead. 19 is a lead wire bond pad 18 of this external connection lead 15 and the IC chip 1.
This wire connects to the chip wire bond pad 14 of No. 1.
このように構成されたICパツケージにおいて
は、ICチツプ１１に外部接続用リード１５を固
定し、リードワイヤボンドパツド１８をチツプパ
ターン１３面上に位置付けたから、ICの実装面
積を小さくすることができると共に、ワイヤボン
デイング工程後に行うIC組立工程でのICチツプ
１１および外部接続用リード１５の相対振動を抑
止することができる。 In the IC package configured in this manner, the external connection leads 15 are fixed to the IC chip 11 and the lead wire bond pads 18 are positioned on the surface of the chip pattern 13, so the mounting area of the IC can be reduced. At the same time, relative vibration of the IC chip 11 and the external connection leads 15 can be suppressed during the IC assembly process performed after the wire bonding process.
次に、このように構成されたICパツケージの
組立方法について説明する。 Next, a method of assembling the IC package configured as described above will be explained.
先ず、接着剤１７によつてチツプパターン１３
の表面上に固着する。次に、このチツプパターン
１３上のチツプワイヤボンドパツド１４と外部接
続用リード１５のリードワイヤボンドパツド１８
とをワイヤ１９によつて接続する。そして、パツ
ケージ（図示せず）によつてICチツプ１１を樹
脂封止する。 First, the chip pattern 13 is attached using adhesive 17.
sticks to surfaces. Next, the chip wire bond pad 14 on this chip pattern 13 and the lead wire bond pad 18 of the external connection lead 15 are connected.
and are connected by a wire 19. Then, the IC chip 11 is sealed with resin using a package (not shown).
このようにしてICパツケージを組み立てるこ
とができる。 In this way, the IC package can be assembled.
なお、本実施例においては、ICチツプ１１と
リードフレーム１６とを接続する場合に適用する
例を示したが、本発明にこれに限定されるもので
はなく、第２図ａおよびｂに示すようにICチツ
プ１１とプリント配線板２０とを接続する場合に
も適用することができる。ここで、２１はリード
ワイヤボンドパツド、２２はリードである。 Although this embodiment shows an example in which the IC chip 11 and the lead frame 16 are connected, the present invention is not limited to this, and as shown in FIGS. 2a and 2b, It can also be applied to the case where the IC chip 11 and the printed wiring board 20 are connected to each other. Here, 21 is a lead wire bond pad, and 22 is a lead.
ICチツプ１１とプリント配線板２０との位置
決めは、ICチツプ１１とリードフレーム１６と
の位置決めに較べて比較的正確に行うことができ
る。このため、ICチツプ１１とプリント配線板
２０とを正確に位置決めし両者を接着することに
よつて、ICチツプ１１上のチツプワイヤボンド
パツド１４とプリント配線板２０のリードワイヤ
ボンドパツド２１とが自ずから精度良く位置決め
される。また、リード２２がプリント配線板２０
上にすでにプリントされているので、それぞれの
リードワイヤボンドパツド２１とチツプワイヤボ
ンドパツド１４との相対高さも自ずと定まりリー
ドワイヤボンドパツド２１とチツプワイヤボンド
パツド１４との相対高さのばらつきが少なくな
る。すなわち、精度の良い位置決めと相対高さの
ばらつき少ないことが相俟つてワイヤボンデイン
グが容易となり、組み立て工程の時間短縮が図ら
れ、歩留りが向上する。 The positioning of the IC chip 11 and the printed wiring board 20 can be performed relatively accurately compared to the positioning of the IC chip 11 and the lead frame 16. Therefore, by accurately positioning the IC chip 11 and the printed wiring board 20 and bonding them together, the chip wire bond pads 14 on the IC chip 11 and the lead wire bond pads 21 of the printed wiring board 20 can be bonded. is automatically positioned with high precision. Further, the lead 22 is connected to the printed wiring board 20.
Since the relative heights of each lead wire bond pad 21 and chip wire bond pad 14 are already printed, the relative height of each lead wire bond pad 21 and chip wire bond pad 14 is determined automatically. Less variation. That is, the combination of highly accurate positioning and little variation in relative height facilitates wire bonding, reduces assembly process time, and improves yield.
また、本発明におけるICチツプ１１の個数は
前述した実施例に限定されず、複数のICチツプ
と外部接続用リードとを接続してもよく、その個
数は適宜変更することが自由である。 Further, the number of IC chips 11 in the present invention is not limited to the above-mentioned embodiment, and a plurality of IC chips and external connection leads may be connected, and the number can be changed as appropriate.
以上説明したように本発明に係るICパツケー
ジは、一主面上の所定の位置に複数個の電極が配
設されたICチツプと、このICチツプの上記電極
に対応して上記主面上に絶縁材を介して互いに交
叉しないように接着されると共に上記電極と電気
的に接続されたその一端が上記電極に近接して配
置されその他端が上記主面の一辺に配列されて外
部リードとされたリードと、上記外部リードを除
いて上記のICチツプとリードとを封止する封止
材料とを備えたため、それだけICの実装面積を
小さくすることができ、パツケージ全体の小型化
を図ることができる。また、ICチツプおよび外
部接続用リードの相対振動を抑止するとができる
から、ワイヤボンデイング工程後のIC組立工程
におけるワイヤの破損を防止することができる。
As explained above, the IC package according to the present invention includes an IC chip having a plurality of electrodes arranged at predetermined positions on one main surface, and a plurality of electrodes arranged on the main surface corresponding to the electrodes of the IC chip. The leads are bonded to each other through an insulating material so as not to cross each other and are electrically connected to the electrodes, one end of which is placed close to the electrodes, and the other end of which is arranged on one side of the main surface to serve as an external lead. Since it is equipped with a lead and a sealing material that seals the IC chip and the leads except for the external leads, the mounting area of the IC can be reduced accordingly, and the overall package can be made smaller. can. Furthermore, since the relative vibration of the IC chip and the external connection leads can be suppressed, it is possible to prevent wire breakage in the IC assembly process after the wire bonding process.
さらに、リードがパツケージの２側部や４側部
から突出するものは実装基板に実装するときIC
チツプの主面に応じたパツケージの表面積が実装
面積として必要になるが、本発明のICパツケー
ジはICチツプの主面が実装基板に垂直になる方
向に立てて実装されるので、実装面積が小さくな
りICパツケージを多数実装するときにコンパク
トにまとめることができ実装効率を向上する。 Furthermore, if the leads protrude from the 2nd or 4th side of the package, when mounting the IC on the mounting board,
The surface area of the package that corresponds to the main surface of the chip is required as the mounting area, but since the IC package of the present invention is mounted with the main surface of the IC chip perpendicular to the mounting board, the mounting area is small. When mounting a large number of IC packages, it can be made compact and improve mounting efficiency.
第１図ａおよびｂは本発明に係るICパツケー
ジを示す平面図と断面図、第２ａおよびｂは他の
実施例を示す平面図と断面図、第３図ａおよびｂ
は従来のICパツケージを示す平面図と断面図で
ある。
１１……ICチツプ、１３……チツプパターン、
１４……チツプワイヤボンドパツド、１５……外
部接続用リード、１８……リードワイヤボンドパ
ツド。
FIGS. 1a and b are a plan view and a sectional view showing an IC package according to the present invention, FIGS. 2a and b are a plan view and a sectional view showing another embodiment, and FIGS. 3a and b are
1 is a plan view and a sectional view showing a conventional IC package. 11...IC chip, 13...chip pattern,
14... Chip wire bond pad, 15... Lead for external connection, 18... Lead wire bond pad.
Claims (1)
する二辺に沿つて複数個のボンデイングパツドが
配設されたICチツプと、 このICチツプの上記ボンデイングパツドのそ
れぞれに対向し近接して配置されたその一端が上
記ボンデイングパツドと電気的に接続され、その
他端が上記主面の、上記二辺以外の一辺に配列さ
れて外部接続用リードとされると共に上記主面上
に絶縁材を介してそれぞれが互いに交叉しないよ
うに接着されたリードと、 を備えたICパツケージ。 ２ 上記絶縁材がプリント配線板であることを特
徴とする特許請求範囲第１項記載のICパツケー
ジ。[Claims] 1. An IC chip having a rectangular principal surface and a plurality of bonding pads arranged along two opposing sides of the principal surface, and the bonding pads of this IC chip. One end of the bonding pad, which is placed opposite and close to each of the pads, is electrically connected to the bonding pad, and the other end is arranged on one side of the main surface other than the two sides, and is used as an external connection lead. and leads that are bonded to the main surface via an insulating material so that the leads do not cross each other. 2. The IC package according to claim 1, wherein the insulating material is a printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61288220A JPS63141329A (en) | 1986-12-03 | 1986-12-03 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61288220A JPS63141329A (en) | 1986-12-03 | 1986-12-03 | Ic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63141329A JPS63141329A (en) | 1988-06-13 |
| JPH0543294B2 true JPH0543294B2 (en) | 1993-07-01 |
Family
ID=17727374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61288220A Granted JPS63141329A (en) | 1986-12-03 | 1986-12-03 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63141329A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327562A (en) * | 1989-06-23 | 1991-02-05 | Nec Corp | Semiconductor device |
| JPH061095A (en) * | 1992-06-19 | 1994-01-11 | Toshiba Corp | Memory card |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5992556A (en) * | 1982-11-19 | 1984-05-28 | Hitachi Ltd | Semiconductor device |
| JPS61236130A (en) * | 1985-04-12 | 1986-10-21 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-12-03 JP JP61288220A patent/JPS63141329A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5992556A (en) * | 1982-11-19 | 1984-05-28 | Hitachi Ltd | Semiconductor device |
| JPS61236130A (en) * | 1985-04-12 | 1986-10-21 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63141329A (en) | 1988-06-13 |
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