JPS63141329A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPS63141329A JPS63141329A JP61288220A JP28822086A JPS63141329A JP S63141329 A JPS63141329 A JP S63141329A JP 61288220 A JP61288220 A JP 61288220A JP 28822086 A JP28822086 A JP 28822086A JP S63141329 A JPS63141329 A JP S63141329A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wire bond
- lead
- pattern
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 11
- 239000007767 bonding agent Substances 0.000 abstract 2
- 230000010355 oscillation Effects 0.000 abstract 2
- 230000000452 restraining effect Effects 0.000 abstract 2
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばリードフレーム等の基台上のチップを
樹脂封止してなるＩＣパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC package in which a chip on a base such as a lead frame is sealed with a resin.
従来、この種のＩＣパッケージは第３図（ａｌおよび（
ｂ）に示すように構成されている。これを同図に基づい
て概略説明すると、同図において、符号ｌで示すものは
フレームダイボンドパッド２およびフレームワイヤボン
ドパッド３を有するリードフレーム、４はこのリードフ
レーム１のフレームダイボンドパッド２上に接着剤５に
よって固着されかつパンケージ（図示せず）によって樹
脂封止されチップ基板６およびチップパターン７を有す
るＩＣチップ、８はこのＩＣチップ４のチップワイヤボ
ンドパッド９と前記リードフレーム１のフレームワイヤ
ボンドパッド３とを接続するワイヤである。Conventionally, this type of IC package is shown in Fig. 3 (al and ()).
It is configured as shown in b). This will be briefly explained based on the same figure. In the figure, what is indicated by the symbol l is a lead frame having a frame die bond pad 2 and a frame wire bond pad 3, and 4 is bonded on the frame die bond pad 2 of this lead frame 1. An IC chip which is fixed by an agent 5 and resin-sealed by a pan cage (not shown) and has a chip substrate 6 and a chip pattern 7; 8 is a chip wire bond pad 9 of this IC chip 4 and a frame wire bond of the lead frame 1; This is a wire that connects the pad 3.
このように構成されたＩＣパッケージを組み立てるには
、接着剤５によってフレームワイヤボンドパッド２上に
ＩＣチップ４を固着し、このＩＣチップ４のチップワイ
ヤボンドパッド９とリードフレーム１のフレームワイヤ
ボンドパッド３とをワイヤ８によって接続した後、パッ
ケージ（図示せず）によってＩＣチップ４を樹脂封止す
ることにより行われる。To assemble the IC package configured in this way, the IC chip 4 is fixed onto the frame wire bond pad 2 with an adhesive 5, and the chip wire bond pad 9 of the IC chip 4 and the frame wire bond pad of the lead frame 1 are bonded together. This is done by connecting the IC chip 4 to the IC chip 3 with a wire 8, and then sealing the IC chip 4 with a resin using a package (not shown).
、〔発明が解決しようとする問題点〕
ところで、この種のＩＣパッケージにおいては、リード
クレーム１の外部接続用リードｌａがＩＣチップ４の周
囲に位置付けられているため、それだけｒｃの実装面積
が大きくなり、パッケージ全体が大型化するという問題
があった。また、リードフレーム１の外部接続用リード
１ａとＩＣチップ４のチップパターン７とはワイヤ８に
よって接続されているため、ワイヤボンディング工程後
に行うＩＣ組立工程での外部接続用リード１ａおよびＩ
Ｃチップ４が相対振動することによりワイヤ８が破損す
る虞があった。[Problems to be Solved by the Invention] Incidentally, in this type of IC package, since the external connection leads la of lead claim 1 are positioned around the IC chip 4, the mounting area of the rc is correspondingly large. Therefore, there was a problem that the entire package became larger. Furthermore, since the external connection leads 1a of the lead frame 1 and the chip pattern 7 of the IC chip 4 are connected by the wires 8, the external connection leads 1a and the I
There was a risk that the wire 8 would be damaged due to the relative vibration of the C-chip 4.
本発明はこのような事情に鑑みなされたもので、パッケ
ージ全体の小型化を図ることができると共に、ワイヤボ
ンディング工程後のＩＣ組立工程におけるワイヤの破福
を防止することができるＩＣパッケージを提供するもの
である。The present invention has been made in view of the above circumstances, and provides an IC package that can reduce the size of the entire package and prevent wires from breaking during the IC assembly process after the wire bonding process. It is something.
本発明に係るＩＣパッケージは、パターン面上にチップ
ワイヤボンドバッドを有するＩＣチップに接着剤によっ
て外部接続用リードを固定し、この外部接続用リードの
リードワイヤボンドパッドをＩＣチップのパターン面上
に位置付けたものである。In the IC package according to the present invention, an external connection lead is fixed with an adhesive to an IC chip having a chip wire bond pad on a pattern surface, and the lead wire bond pad of the external connection lead is fixed to an IC chip having a chip wire bond pad on the pattern surface of the IC chip. It was positioned as such.
本発明においては、ＩＣの実装面積を小さくすることが
できると共に、ＩＣチップおよび外部接続用リードの相
対振動を抑止することができる。According to the present invention, the mounting area of the IC can be reduced, and relative vibration between the IC chip and external connection leads can be suppressed.
第１図（ａｌおよび（ｂｌは本発明に係るＩＣパッケー
ジを示す平面図と断面図である。同図において、符号１
１で示すものはパッケージ（図示せず）によって封止さ
れる矩形状のＩＣチップで、チップ基板１２およびチッ
プパターン１３からなり、このうちチップパターン１３
表面上の両側にチップワイヤボンドバッド１４が形成さ
れている。１５はリードフレーム１６の外部接続用リー
ドで、接着剤１７によって前記ＩＣチップ１１に固定さ
れており、そのリードワイヤボンドパッド１８は前記両
チップワイヤボンドバッド１４間に介在するように前記
チップパターン１３の表面上に位置付けられている。ま
た、１９はこの外部接続用リード１５のリードワイヤボ
ンドパッド１８と前記ＩＣチップ１１のチップワイヤボ
ンドバッド１４とを接続するワイヤである。FIG. 1 (al and (bl) are a plan view and a sectional view showing an IC package according to the present invention. In the figure, reference numeral 1
1 is a rectangular IC chip sealed by a package (not shown), which is composed of a chip substrate 12 and a chip pattern 13, of which the chip pattern 13
Chip wire bond pads 14 are formed on both sides on the surface. Reference numeral 15 denotes an external connection lead of the lead frame 16, which is fixed to the IC chip 11 with adhesive 17, and its lead wire bond pad 18 is connected to the chip pattern 13 so as to be interposed between both the chip wire bond pads 14. is located on the surface of Further, 19 is a wire that connects the lead wire bond pad 18 of this external connection lead 15 and the chip wire bond pad 14 of the IC chip 11.
このように構成されたＩＣパッケージにおいては、ＩＣ
チップ１１に外部接続用リード１５を固定し、リードワ
イヤボンドバンド１８をチップパターン１３上に位置付
けたから、ＴＣの実装面積を小さくすることができると
共に、ワイヤボンディング工程後に行うＩＣ組立工程で
のＩＣチップ１１および外部接続用リード１５の相対振
動を抑止することができる。In the IC package configured in this way, the IC
Since the external connection leads 15 are fixed to the chip 11 and the lead wire bond bands 18 are positioned on the chip pattern 13, the mounting area of the TC can be reduced, and the IC chip can be easily removed during the IC assembly process performed after the wire bonding process. 11 and the external connection lead 15 can be suppressed from relative vibration.
次に、このように構成されたＩＣパッケージの組立方法
について説明する。Next, a method for assembling the IC package configured as described above will be explained.
先ず、接着剤１７によってチップパターン１３の表面上
に固着する。次に、このチップパターン１３上のチップ
ワイヤボンドバッド１４と外部接続用リード１５のリー
ドワイヤボンドパッド１８とをワイヤ１９によって接続
する。そして、パッケージ（図示せず）によってＩＣチ
ップ１１を樹脂封止する。First, it is fixed onto the surface of the chip pattern 13 using an adhesive 17. Next, the chip wire bond pads 14 on this chip pattern 13 and the lead wire bond pads 18 of the external connection leads 15 are connected by wires 19. Then, the IC chip 11 is sealed with resin using a package (not shown).
このようにしてＩＣパッケージを組み立てることができ
る。In this way, the IC package can be assembled.
なお、本実施例においては、ＩＣチップ１１とリードフ
レーム１６とを接続する場合に適用する例を示したが、
本発明はこれに限定されるものではなく、第２図（ａ）
およびｆｂｌに示すようにＩＣチップ１１とプリント配
線板２０とを接続する場合にも適用することができる。Note that in this embodiment, an example is shown where the IC chip 11 and the lead frame 16 are connected.
The present invention is not limited to this, but as shown in FIG. 2(a).
The present invention can also be applied to the case where the IC chip 11 and the printed wiring board 20 are connected as shown in FIG.
ここで、２１はリードワイヤボンドバンド、２２はリー
ドである。Here, 21 is a lead wire bond band, and 22 is a lead.
また、本発明におけるＩＣチップ１１の個数は前述した
実施例に限定されず、複数のＩＣチップと外部接続用リ
ードとを接続してもよく、その個数は適宜変更すること
が自由である。Further, the number of IC chips 11 in the present invention is not limited to the above-described embodiment, and a plurality of IC chips and external connection leads may be connected, and the number can be changed as appropriate.
以上説明したように本発明によれば、そのパターン面上
にチップワイヤボンドバッドを有するＩＣチップに接着
剤によって外部接続用リードを固定し、この外部接続用
リードのリードワイヤボンドパッドをＩＣチップのパタ
ーン面上に位置付けたので、それだけＩＣの実装面積を
小さくすることができ、パッケージ全体の小型化を図る
ことができる。また、ＩＣチ、プおよび外部接続用り−
ドの相対振動を抑止することができるから、ワイヤボン
ディング工程後のＩＣ組立工程におけるワイヤの破損を
防止することができる。As explained above, according to the present invention, an external connection lead is fixed with an adhesive to an IC chip having a chip wire bond pad on the pattern surface, and the lead wire bond pad of the external connection lead is attached to the IC chip. Since it is positioned on the pattern surface, the mounting area of the IC can be reduced accordingly, and the overall package can be made smaller. Also, for IC chips and external connections.
Since the relative vibration of the wire can be suppressed, breakage of the wire in the IC assembly process after the wire bonding process can be prevented.
第１図（ａ）および（ｂ）は本発明に係るＩＣパッケー
ジを示す平面図と断面図、第２図（ａ）および（ｂ）は
他の実施例を示す平面図と断面図、第３図（８１および
（ｂｌは従来のＩＣパッケージを示す平面図と断面図で
ある。
１１・・・・ＩＣチップ、１３・・・・チップパターン
、１４・・・・チップワイヤボンドパッド、１５・・・
・外部接続用リード、１８・・・・リードワイヤボンド
パッド。
代 理 人 大 岩 増 雄
第１図
１１：ＩＣケッフ０
１３：チッフ″バクーン1(a) and (b) are a plan view and a cross-sectional view showing an IC package according to the present invention, FIGS. 2(a) and (b) are a plan view and a cross-sectional view showing another embodiment, and FIG. Figures (81 and (bl) are a plan view and a cross-sectional view showing a conventional IC package. 11...IC chip, 13...chip pattern, 14...chip wire bond pad, 15...・
・Lead for external connection, 18...Lead wire bond pad. Agent Masuo Oiwa Figure 1 11: IC Keff 0 13: CHIFF'' Bakun
Claims (1)
ＩＣチップに接着剤によって外部接続用リードを固定し
、この外部接続用リードのリードワイヤボンドパッドを
前記パターン面上に位置付けたことを特徴とするＩＣパ
ッケージ。An IC package characterized in that an external connection lead is fixed to an IC chip having a chip wire bond pad on the pattern surface with an adhesive, and the lead wire bond pad of the external connection lead is positioned on the pattern surface. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61288220A JPS63141329A (en) | 1986-12-03 | 1986-12-03 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61288220A JPS63141329A (en) | 1986-12-03 | 1986-12-03 | Ic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63141329A true JPS63141329A (en) | 1988-06-13 |
| JPH0543294B2 JPH0543294B2 (en) | 1993-07-01 |
Family
ID=17727374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61288220A Granted JPS63141329A (en) | 1986-12-03 | 1986-12-03 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63141329A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327562A (en) * | 1989-06-23 | 1991-02-05 | Nec Corp | Semiconductor device |
| US5420756A (en) * | 1992-06-19 | 1995-05-30 | Kabushiki Kaisha Toshiba | Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5992556A (en) * | 1982-11-19 | 1984-05-28 | Hitachi Ltd | Semiconductor device |
| JPS61236130A (en) * | 1985-04-12 | 1986-10-21 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-12-03 JP JP61288220A patent/JPS63141329A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5992556A (en) * | 1982-11-19 | 1984-05-28 | Hitachi Ltd | Semiconductor device |
| JPS61236130A (en) * | 1985-04-12 | 1986-10-21 | Hitachi Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327562A (en) * | 1989-06-23 | 1991-02-05 | Nec Corp | Semiconductor device |
| US5420756A (en) * | 1992-06-19 | 1995-05-30 | Kabushiki Kaisha Toshiba | Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543294B2 (en) | 1993-07-01 |
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