JPH09306934A - Manufacture of chip semiconductor device - Google Patents
Manufacture of chip semiconductor deviceInfo
- Publication number
- JPH09306934A JPH09306934A JP8124537A JP12453796A JPH09306934A JP H09306934 A JPH09306934 A JP H09306934A JP 8124537 A JP8124537 A JP 8124537A JP 12453796 A JP12453796 A JP 12453796A JP H09306934 A JPH09306934 A JP H09306934A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- recesses
- chip
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はチップ型半導体装置
の製造方法に係り、特に半導体素子を内蔵したチップ型
半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a chip-type semiconductor device, and more particularly to a method for manufacturing a chip-type semiconductor device having a built-in semiconductor element.
【0002】[0002]
【従来の技術】従来より、半導体素子を内蔵したチップ
型半導体装置の製造方法として、複数個の素子に一度に
キャップを被せることができるようにしたチップ型半導
体装置の製造方法が知られている(特開平4−1485
53号公報)。この従来の製造方法では、図4に示すよ
うに、複数個分の基板を含む親基板21の上面と下面の
それぞれに複数の上面電極及び下面電極を設け、上面電
極と下面電極をつなげるために貫通孔22を設け、スル
ーホール23により導通させ、更に隣り合うスルーホー
ル23の間の親基板21の上に素子26をそれぞれ搭載
して素子26のそれぞれと上面電極とをワイヤ27によ
り電気的に接続する。2. Description of the Related Art Conventionally, as a method of manufacturing a chip-type semiconductor device having a built-in semiconductor element, a method of manufacturing a chip-type semiconductor device in which a plurality of elements can be capped at once has been known. (Japanese Patent Laid-Open No. 4-1485
No. 53). In this conventional manufacturing method, as shown in FIG. 4, in order to connect the upper surface electrode and the lower surface electrode, a plurality of upper surface electrodes and lower surface electrodes are provided on each of the upper surface and the lower surface of the parent substrate 21 including a plurality of substrates. Through holes 22 are provided, conduction is provided by through holes 23, and elements 26 are respectively mounted on the parent substrate 21 between adjacent through holes 23, and each of the elements 26 and the upper surface electrode are electrically connected by wires 27. Connecting.
【0003】次に、図5に示すように、下面に凹所32
が形成された封止用親蓋31を素子26の上から親基板
21の上に固着して各素子26を凹所32内に封入させ
る。この後、図5のC−C線に沿って親基板21及び封
止用親蓋31を各素子26毎にそれぞれ切り離し、図6
に示すようなチップ型部品41を複数個製造する。Next, as shown in FIG. 5, a recess 32 is formed in the lower surface.
The encapsulating parent lid 31 on which the elements are formed is fixed onto the parent substrate 21 from above the elements 26 to enclose each element 26 in the recess 32. Thereafter, the parent board 21 and the sealing parent lid 31 are separated for each element 26 along the line CC of FIG.
A plurality of chip components 41 as shown in FIG.
【0004】[0004]
【発明が解決しようとする課題】しかるに、上記の従来
方法では、封止用親蓋31を用いて各素子26を封止す
るため、親基板21と封止用親蓋31の厚みによってチ
ップサイズ、特に厚みが決定されるため、製造されたチ
ップ型部品41がリードレスパッケージとしては有効だ
が、チップサイズを小さくするためには限界がある。However, in the above-mentioned conventional method, since each element 26 is sealed by using the sealing parent lid 31, the chip size is determined by the thickness of the parent substrate 21 and the sealing parent lid 31. Since the thickness is determined in particular, the manufactured chip-type component 41 is effective as a leadless package, but there is a limit in reducing the chip size.
【0005】また、親基板21と封止用親蓋31の接着
に加熱プロセスを使うと、親基板21と封止用親蓋31
の応力差により親基板21が反るため、ダイシングで切
り離す際に精度良く切り離すことができない。また、加
熱プロセスを使用しない場合は、封止用親蓋31を用い
て各素子26を封止するため、封止の力が弱く、信頼性
に乏しい。If a heating process is used to bond the parent substrate 21 and the sealing parent lid 31, the parent substrate 21 and the sealing parent lid 31 are used.
Since the parent substrate 21 warps due to the difference in stress, it cannot be accurately separated when it is separated by dicing. When the heating process is not used, each element 26 is sealed using the sealing parent lid 31, so the sealing force is weak and the reliability is poor.
【0006】本発明は以上の点に鑑みなされたもので、
小型なチップ型半導体装置を製造し得るチップ型半導体
装置の製造方法を提供することを目的とする。[0006] The present invention has been made in view of the above points,
It is an object of the present invention to provide a method of manufacturing a chip-type semiconductor device capable of manufacturing a small chip-type semiconductor device.
【0007】また、本発明の他の目的は、より信頼性の
高いチップ型半導体装置の製造方法を提供することにあ
る。Another object of the present invention is to provide a more reliable method of manufacturing a chip type semiconductor device.
【0008】[0008]
【課題を解決するための手段】本発明は上記の目的を達
成するため、内部に第1のパターン電極と半導体素子を
それぞれ有する複数個の凹部が表面に形成され、第2の
パターン電極が裏面に形成され、第1及び第2のパター
ン電極がスルーホールを介して電気的に接続された基板
を切り離すことによりチップ型半導体装置を製造するこ
とを特徴とする。In order to achieve the above-mentioned object, the present invention has a plurality of recesses each having a first pattern electrode and a semiconductor element therein, and a second pattern electrode being a back surface. Characterized in that the chip-type semiconductor device is manufactured by cutting off the substrate formed on the first and second pattern electrodes and electrically connected through the through hole.
【0009】また、本発明はそれぞれ内部に第1のパタ
ーン電極が形成された複数個の凹部が表面に形成され、
第2のパターン電極が裏面に形成され、第1及び第2の
パターン電極がスルーホールを介して電気的に接続され
た基板の凹部のそれぞれに半導体素子を搭載する第1の
工程と、半導体素子をワイヤボンディングする第2の工
程と、半導体素子が搭載された凹部内に液状樹脂を注入
した後硬化させる第3の工程と、基板を前記複数個の凹
部毎に切り離す第4の工程とを含むことを特徴とする。Further, according to the present invention, a plurality of recesses each having a first pattern electrode formed therein are formed on the surface,
A first step of mounting a semiconductor element in each of the recesses of the substrate in which the second pattern electrode is formed on the back surface and the first and second pattern electrodes are electrically connected through the through holes; Wire bonding, a third step of injecting a liquid resin into the recesses in which the semiconductor elements are mounted and then hardening, and a fourth step of separating the substrate into the plurality of recesses. It is characterized by
【0010】本発明では、基板上に搭載した半導体素子
を封止するように親蓋を被せるのではなく、基板に凹部
を形成してその凹部内に半導体素子を搭載した後、基板
を切り離すようにしたため、親蓋を不要にすることがで
きる。According to the present invention, a recess is formed in the substrate to mount the semiconductor element on the substrate, and then the semiconductor element is mounted on the substrate, and then the substrate is separated. Therefore, the parent lid can be eliminated.
【0011】また、本発明では、基板の凹部内の半導体
素子を液状樹脂で封止するようにしたため、基板全体の
熱応力を考慮した基板の厚み、材質の検討を不要にする
ことができる。Further, in the present invention, since the semiconductor element in the recess of the substrate is sealed with the liquid resin, it is not necessary to consider the thickness and material of the substrate in consideration of the thermal stress of the entire substrate.
【0012】[0012]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。図1(A)、(B)及び(C)
は本発明になるチップ型半導体装置の製造方法の一実施
の形態で用いる基板の表面図、裏面図及び同図(A)の
C−C’線に沿う断面図を示す。基板1には複数個の凹
部4が形成されており、その凹部4内に上面パターン電
極2が印刷されている。基板1の裏面には、下面パター
ン電極5が印刷されている。上面パターン電極2と下面
パターン電極5とはそれぞれスルーホール3により電気
的に接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. 1 (A), (B) and (C)
Shows a front view and a back view of a substrate used in an embodiment of a method for manufacturing a chip-type semiconductor device according to the present invention, and a cross-sectional view taken along the line CC ′ of FIG. A plurality of recesses 4 are formed in the substrate 1, and the upper surface pattern electrodes 2 are printed in the recesses 4. A bottom surface pattern electrode 5 is printed on the back surface of the substrate 1. The upper surface pattern electrode 2 and the lower surface pattern electrode 5 are electrically connected to each other through through holes 3.
【0013】図2は図1の基板1を使ってチップ型半導
体装置を製造する本発明方法の一実施の形態の各工程の
装置断面図を示す。まず、図2(A)に示すように、図
1に示した基板1の凹部4に半導体素子6を搭載し、ワ
イヤ7で半導体素子6と上面パターン電極2との間をボ
ンディングする。FIG. 2 is a sectional view of the device in each step of one embodiment of the method of the present invention for manufacturing a chip type semiconductor device using the substrate 1 of FIG. First, as shown in FIG. 2A, the semiconductor element 6 is mounted in the concave portion 4 of the substrate 1 shown in FIG. 1, and the semiconductor element 6 and the upper surface pattern electrode 2 are bonded by the wire 7.
【0014】次に、図2(B)に示すように、凹部4に
封止用液状樹脂8を注入し、樹脂8の硬化プロセスによ
り熱あるいは光により硬化させる。続いて、図2(B)
のA−A線に沿って、つまり隣り合う凹部4と凹部4の
間の基板部分を通るラインに沿って基板1を切断し、図
2(C)に示すように、複数個のチップ型半導体装置9
として分離させる。ここで、図2(C)中、8’は硬化
後の封止用液状樹脂を示す。このように、この実施の形
態によれば、各半導体素子6毎にそれぞれ切り離すこと
により、図3の斜視図に示すようなチップ型半導体装置
9を複数個製造する。Next, as shown in FIG. 2B, a liquid resin 8 for sealing is injected into the recess 4 and is cured by heat or light by a curing process of the resin 8. Then, FIG. 2 (B)
2A, that is, the substrate 1 is cut along a line passing through the substrate portion between the adjacent concave portions 4 and the concave portion 4, and as shown in FIG. Device 9
To separate as. Here, in FIG. 2C, 8'denotes the liquid resin for sealing after curing. Thus, according to this embodiment, a plurality of chip-type semiconductor devices 9 as shown in the perspective view of FIG. 3 are manufactured by separating each semiconductor element 6.
【0015】本実施の形態によれば、基板上に封止用親
蓋を被せるのではなく、基板1に形成した凹部4内に半
導体素子6を搭載するようにしたため、チップ型半導体
装置9の厚みは、半導体素子6の厚みに極めて近い厚み
まで薄くすることができる。また、基板1の材質、サイ
ズによる熱応力を考慮して基板1を用意する必要がな
く、精度良く基板1を切り離すことができる。According to the present embodiment, the semiconductor element 6 is mounted in the concave portion 4 formed in the substrate 1 instead of covering the substrate with the sealing parent lid. The thickness can be reduced to a thickness extremely close to the thickness of the semiconductor element 6. Further, it is not necessary to prepare the substrate 1 in consideration of thermal stress due to the material and size of the substrate 1, and the substrate 1 can be separated with high accuracy.
【0016】[0016]
【発明の効果】以上説明したように、本発明によれば、
基板に凹部を形成してその凹部内に半導体素子を搭載し
た後、基板を切り離すことにより、親蓋を不要にしたた
め、チップ型半導体装置の厚みを半導体素子の厚みに限
りなく近付けることができ、よって、従来よりもチップ
型半導体装置を大幅に小型、軽量化することができる。As described above, according to the present invention,
After forming the concave portion on the substrate and mounting the semiconductor element in the concave portion, by separating the substrate, the parent lid is unnecessary, so that the thickness of the chip-type semiconductor device can be made as close as possible to the thickness of the semiconductor element, Therefore, the chip-type semiconductor device can be made significantly smaller and lighter than the conventional one.
【0017】また、本発明によれば、封止用親蓋を基板
に固着するのではなく、基板の凹部内の半導体素子を液
状樹脂で封止するようにしたため、基板全体の熱応力を
考慮した基板の厚み、材質の検討を不要にすることがで
き、よって、熱応力による基板の反りが全く無く、高精
度に基板を切り離すことができ、製造されたチップ型半
導体装置の信頼性を向上することができる。Further, according to the present invention, the semiconductor element in the concave portion of the substrate is sealed with the liquid resin instead of fixing the sealing parent lid to the substrate, so that the thermal stress of the entire substrate is taken into consideration. Since it is not necessary to consider the thickness and material of the substrate, the substrate is not warped due to thermal stress, and the substrate can be separated with high precision, improving the reliability of the manufactured chip-type semiconductor device. can do.
【図1】本発明製造方法で用いる基板の一実施の形態で
用いる基板の表面図、裏面図及び断面図である。FIG. 1 is a front view, a back view and a sectional view of a substrate used in an embodiment of a substrate used in a manufacturing method of the present invention.
【図2】本発明製造方法の一実施の形態の各工程説明用
装置断面図である。FIG. 2 is a cross-sectional view of an apparatus for explaining each step of the embodiment of the manufacturing method of the present invention.
【図3】図2の製造方法で製造されたチップ型半導体装
置の斜視図である。3 is a perspective view of a chip-type semiconductor device manufactured by the manufacturing method of FIG.
【図4】従来の製造方法の一例の第1の工程の装置断面
図である。FIG. 4 is a device cross-sectional view of a first step of an example of a conventional manufacturing method.
【図5】従来の製造方法の一例の第2の工程の装置断面
図である。FIG. 5 is a sectional view of a device in a second step of an example of a conventional manufacturing method.
【図6】図4及び図5の製造方法で製造されたチップ型
部品の斜視図である。6 is a perspective view of a chip-type component manufactured by the manufacturing method of FIGS. 4 and 5. FIG.
1 基板 2 上面パターン電極 3 スルーホール 4 凹部 5 下面パターン電極 6 半導体素子 7 ワイヤ 8 封止用液状樹脂 8’硬化後の封止用液状樹脂 9 チップ型半導体装置 DESCRIPTION OF SYMBOLS 1 Substrate 2 Upper surface pattern electrode 3 Through hole 4 Recess 5 Lower surface pattern electrode 6 Semiconductor element 7 Wire 8 Liquid resin for sealing 8'Liquid resin for sealing after curing 9 Chip type semiconductor device
Claims (3)
をそれぞれ有する複数個の凹部が表面に形成され、第2
のパターン電極が裏面に形成され、該第1及び第2のパ
ターン電極がスルーホールを介して電気的に接続された
基板を切り離すことによりチップ型半導体装置を製造す
ることを特徴とするチップ型半導体装置の製造方法。1. A plurality of recesses each having a first pattern electrode and a semiconductor element therein are formed on the surface, and a second recess is formed.
A chip-type semiconductor device is manufactured by separating the substrate on which the pattern electrodes of (1) are formed on the back surface and the first and second pattern electrodes are electrically connected through the through holes. Device manufacturing method.
成された複数個の凹部が表面に形成され、第2のパター
ン電極が裏面に形成され、該第1及び第2のパターン電
極がスルーホールを介して電気的に接続された基板の該
凹部のそれぞれに半導体素子を搭載する第1の工程と、 前記半導体素子をワイヤボンディングする第2の工程
と、 前記半導体素子が搭載された前記凹部内に液状樹脂を注
入した後硬化させる第3の工程と、 前記基板を前記複数個の凹部毎に切り離す第4の工程と
を含むことを特徴とするチップ型半導体装置の製造方
法。2. A plurality of recesses, each having a first pattern electrode formed therein, are formed on the front surface, a second pattern electrode is formed on the back surface, and the first and second pattern electrodes are through holes. A first step of mounting a semiconductor element in each of the recesses of the substrate electrically connected via a substrate, a second step of wire bonding the semiconductor element, and a recess in which the semiconductor element is mounted. A method for manufacturing a chip-type semiconductor device, comprising: a third step of injecting a liquid resin into the substrate and then curing the resin; and a fourth step of separating the substrate into the plurality of recesses.
は光により硬化することを特徴とする請求項2記載のチ
ップ型半導体装置の製造方法。3. The method of manufacturing a chip type semiconductor device according to claim 2, wherein the liquid resin is cured by heat or light in the third step.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8124537A JP2867954B2 (en) | 1996-05-20 | 1996-05-20 | Manufacturing method of chip type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8124537A JP2867954B2 (en) | 1996-05-20 | 1996-05-20 | Manufacturing method of chip type semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09306934A true JPH09306934A (en) | 1997-11-28 |
JP2867954B2 JP2867954B2 (en) | 1999-03-10 |
Family
ID=14887938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8124537A Expired - Fee Related JP2867954B2 (en) | 1996-05-20 | 1996-05-20 | Manufacturing method of chip type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2867954B2 (en) |
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-
1996
- 1996-05-20 JP JP8124537A patent/JP2867954B2/en not_active Expired - Fee Related
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EP1143508A3 (en) * | 2000-03-23 | 2004-06-23 | Infineon Technologies AG | Apparatus for packaging electronic components |
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WO2005071732A1 (en) * | 2004-01-22 | 2005-08-04 | Fico B.V. | Carrier for electronic components and methods for encapsulating and separating an electronic component |
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