JPH0778910A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0778910A JPH0778910A JP22158693A JP22158693A JPH0778910A JP H0778910 A JPH0778910 A JP H0778910A JP 22158693 A JP22158693 A JP 22158693A JP 22158693 A JP22158693 A JP 22158693A JP H0778910 A JPH0778910 A JP H0778910A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- resin
- sealing resin
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂封止した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
【0002】[0002]
【従来の技術】従来の半導体装置のうち樹脂封止された
半導体装置は、ダイパッドと呼ばれる金属の上に半導体
チップを固定,保持し、半導体装置の端子を構成するリ
ードと半導体チップ上のボンディングパッドとをボンデ
ィングワイヤにより接続している。図2はこのように樹
脂封止された従来の半導体装置の一例の断面図である。
図2に於いて、半導体チップ2はダイパッド1の上に固
定,保持されており、半導体装置の端子を構成するリー
ド4と半導体チップ2表面に設けられたボンディングパ
ッド5とをボンディングワイヤ6により接続した状態で
封止樹脂3によって封止されている。2. Description of the Related Art Among conventional semiconductor devices, a resin-sealed semiconductor device is a semiconductor device in which a semiconductor chip is fixed and held on a metal called a die pad, and leads forming a terminal of the semiconductor device and a bonding pad on the semiconductor chip. And are connected by a bonding wire. FIG. 2 is a sectional view of an example of a conventional semiconductor device thus resin-sealed.
In FIG. 2, the semiconductor chip 2 is fixed and held on the die pad 1, and the leads 4 constituting the terminals of the semiconductor device and the bonding pads 5 provided on the surface of the semiconductor chip 2 are connected by the bonding wires 6. In this state, it is sealed with the sealing resin 3.
【0003】一方、このような従来の半導体装置に対
し、近年LOC(Lead On Chipの略)と呼
ばれる新しい技術により組立られた半導体装置が現われ
ている。これは、図2に示す半導体チップ2を固定し保
持するダイパッド1をなくしてパッケージの端子を構成
するリード4自体により半導体チップ2を固定し保持す
るものである。図3に従来のLOC技術により組立てら
れた半導体装置の樹脂封止後の断面図を示す。なお、図
2で示した従来の半導体装置と同一機能を有する部分に
は同一番号を付す。On the other hand, in contrast to such a conventional semiconductor device, a semiconductor device assembled by a new technology called LOC (abbreviation of Lead On Chip) has recently appeared. This eliminates the die pad 1 for fixing and holding the semiconductor chip 2 shown in FIG. 2 and fixes and holds the semiconductor chip 2 by the leads 4 themselves forming the terminals of the package. FIG. 3 shows a cross-sectional view of a semiconductor device assembled by a conventional LOC technique after resin sealing. The parts having the same functions as those of the conventional semiconductor device shown in FIG.
【0004】図3に於いては、半導体チップ2はポリイ
ミド層7を介して、粘着テープ8でリード4に直接固定
されている。ここでポリイミド層7は主に半導体チップ
2表面を保護するために用いられている。このLOC技
術を用いると、ダイパッドとリードとを分離する必要が
ないので、従来の組立技術を用いた場合と比較して、そ
の分離領域に相当する寸法だけ大きな半導体チップ2
を、同じ大きさのパッケージに組立てることが出来ると
いう利点がある。またリード4が、半導体チップ2上に
配置されているため、その形状を変えることにより、半
導体チップ2上のボンディングパッド5の配置の自由度
が増すという利点もある。例えば、ボンディングパッド
5を半導体チップ2の中央に配置するということも、従
来技術ではボンディングワイヤが長くなって、半導体チ
ップに接触するという不具合が発生したが、このLOC
技術ではそのような問題も生じない。In FIG. 3, the semiconductor chip 2 is directly fixed to the lead 4 with an adhesive tape 8 via a polyimide layer 7. Here, the polyimide layer 7 is mainly used to protect the surface of the semiconductor chip 2. When this LOC technology is used, it is not necessary to separate the die pad from the leads, so that the semiconductor chip 2 which is larger than the conventional assembly technology by the size corresponding to the separation region is used.
Have the advantage that they can be assembled into a package of the same size. Further, since the lead 4 is arranged on the semiconductor chip 2, there is also an advantage that the degree of freedom in arranging the bonding pad 5 on the semiconductor chip 2 is increased by changing the shape thereof. For example, arranging the bonding pad 5 at the center of the semiconductor chip 2 also causes a problem that the bonding wire becomes long and contacts the semiconductor chip in the conventional technique.
Technology does not cause such problems.
【0005】[0005]
【発明が解決しようとする課題】しかるに、従来のLO
C構造の半導体装置では、半導体チップ下部で封止樹脂
にクラック等損傷が発生するおそれがある。以下にこの
問題点について詳しく説明する。However, the conventional LO
In the semiconductor device having the C structure, damage such as cracks may occur in the sealing resin below the semiconductor chip. This problem will be described in detail below.
【0006】半導体装置が高温に保持されるなどの熱的
ストレスを受けると、裏面の半導体チップと封止樹脂
と、表面のポリイミド層とリードとの熱膨張率の違いか
ら、両者の接触面に熱応力が発生する。そしてこの応力
により接触面に剥離がおこり、この隙間に封止樹脂中に
含まれていた水分が出てきて気化し、その蒸気圧が大き
くなると封止樹脂にクラック等の損傷が発生する。半導
体チップの表面の側では、リードが複雑に半導体チップ
表面に配置されているので、適度に熱応力が分散される
とともに、封止樹脂との密着性を高めている。これに対
し、半導体チップの裏面では広い面積にわたって封止樹
脂と平面で接触する部分ができているので、接触面の剥
離が発生しやすくなっている。しかも、LOC技術を用
いる半導体装置は、ペレット面積が大きいものがほとん
どで、ペレット端部からパッケージの側壁までの距離が
小さく、封止樹脂によりクラック等の損傷が発生しやす
い。When the semiconductor device is subjected to thermal stress such as being kept at a high temperature, the contact surface of the semiconductor chip and the sealing resin on the back surface and the polyimide layer on the front surface and the leads differ in thermal expansion coefficient. Thermal stress occurs. Then, due to this stress, peeling occurs on the contact surface, water contained in the sealing resin comes out in this gap and is vaporized, and when the vapor pressure becomes large, damage such as cracks occurs in the sealing resin. On the surface side of the semiconductor chip, the leads are arranged intricately on the surface of the semiconductor chip, so that the thermal stress is appropriately dispersed and the adhesion with the sealing resin is improved. On the other hand, the back surface of the semiconductor chip has a flat surface that comes into contact with the sealing resin over a large area, so that peeling of the contact surface is likely to occur. Moreover, most of the semiconductor devices using the LOC technology have a large pellet area, the distance from the end of the pellet to the side wall of the package is small, and damage such as cracks is likely to occur due to the sealing resin.
【0007】そこで本発明の目的は、以上の問題点を解
決して半導体チップを保持し、封止樹脂にクラック等の
損傷が発生するのを防ぐ事のできる半導体装置を提供す
ることにある。Therefore, an object of the present invention is to solve the above problems and to provide a semiconductor device which holds a semiconductor chip and can prevent damage such as cracks in a sealing resin.
【0008】[0008]
【課題を解決するための手段】本発明は、半導体チップ
表面とパッケージのリードとを接着する手段を用いて前
記リードに前記半導体チップを固定し樹脂封止した半導
体装置に於いて、前記半導体チップの裏面に凹凸を設け
ている。SUMMARY OF THE INVENTION The present invention provides a semiconductor device in which the semiconductor chip is fixed to the leads by means of a means for adhering the surface of the semiconductor chip to the leads of the package and resin-sealed. The back surface of the has unevenness.
【0009】[0009]
【実施例】以下に、図面を用いて本発明の実施例につい
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0010】図1は本発明の一実施例を示した半導体装
置の断面図である。図1に於いて、半導体チップ2は半
導体チップ2上に塗布されたポリイミド層7を介して、
粘着テープ8でリード4に固定されている。そして、図
3に示す従来の半導体装置と異なる点は半導体チップ裏
面に凹凸を設けている点である。このように、半導体チ
ップ2裏面に凹凸を設ける事により、半導体チップ2裏
面と封止樹脂3の接触面積が増え、封止樹脂3との密着
性が向上し熱応力による剥離を防止することができる。
なお、半導体チップ2裏面に凹凸を設ける手段として
は、半導体ウエハの裏面を研削してウエハ厚を薄くする
際に、意図的に凹凸を設ける方法などが考えられる。FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. In FIG. 1, the semiconductor chip 2 has a polyimide layer 7 applied on the semiconductor chip 2,
It is fixed to the lead 4 with an adhesive tape 8. The difference from the conventional semiconductor device shown in FIG. 3 is that unevenness is provided on the back surface of the semiconductor chip. In this way, by providing unevenness on the back surface of the semiconductor chip 2, the contact area between the back surface of the semiconductor chip 2 and the sealing resin 3 increases, the adhesiveness with the sealing resin 3 is improved, and peeling due to thermal stress can be prevented. it can.
As a means for providing the back surface of the semiconductor chip 2 with unevenness, a method of intentionally providing the unevenness when the back surface of the semiconductor wafer is ground to reduce the wafer thickness is considered.
【0011】[0011]
【発明の効果】以上説明したように本発明は、半導体チ
ップ表面とパッケージのリードとを接着する手段を用い
てリードに半導体チップを固定し樹脂封止した半導体装
置に於いて、半導体チップの裏面に凹凸を設ける事で、
半導体チップ裏面に接触しているパッケージの封止樹脂
が熱応力によりクラック等の損傷を受けるのを防ぐ効果
を有する。As described above, according to the present invention, in the semiconductor device in which the semiconductor chip is fixed to the lead by means of the means for adhering the surface of the semiconductor chip to the lead of the package and resin-sealed, the back surface of the semiconductor chip By providing unevenness on the
This has an effect of preventing the sealing resin of the package, which is in contact with the back surface of the semiconductor chip, from being damaged by thermal stress such as cracks.
【図1】本発明の一実施例を示した半導体装置の断面図
である。FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.
【図2】樹脂封止された従来の半導体装置の一例の断面
図である。FIG. 2 is a sectional view of an example of a conventional semiconductor device sealed with a resin.
【図3】従来のLOC技術により組立られた半導体装置
の樹脂封止後の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device assembled by a conventional LOC technique after resin sealing.
1 ダイパッド 2 半導体チップ 3 封止樹脂 4 リード 5 ボンディングパッド 6 ボンディングワイヤ 7 ポリイミド層 8 粘着テープ 1 Die Pad 2 Semiconductor Chip 3 Sealing Resin 4 Lead 5 Bonding Pad 6 Bonding Wire 7 Polyimide Layer 8 Adhesive Tape
Claims (1)
とを接着する手段を用いて前記リードに前記半導体チッ
プを固定し樹脂封止した半導体装置に於いて、前記半導
体チップの裏面に凹凸を設けた事を特徴とする半導体装
置。1. In a semiconductor device in which the semiconductor chip is fixed to the lead by means of bonding the surface of the semiconductor chip to a lead of a package and resin-encapsulated, unevenness is provided on the back surface of the semiconductor chip. A semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22158693A JPH0778910A (en) | 1993-09-07 | 1993-09-07 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22158693A JPH0778910A (en) | 1993-09-07 | 1993-09-07 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0778910A true JPH0778910A (en) | 1995-03-20 |
Family
ID=16769073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22158693A Pending JPH0778910A (en) | 1993-09-07 | 1993-09-07 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0778910A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100234708B1 (en) * | 1996-12-18 | 1999-12-15 | Hyundai Micro Electronics Co | Blp type semiconductor package and mounting structure thereof |
CN1101597C (en) * | 1996-11-08 | 2003-02-12 | 三星电子株式会社 | Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same |
JP2004296690A (en) * | 2003-03-26 | 2004-10-21 | Shinko Electric Ind Co Ltd | Manufacturing method of multilayer circuit board with built-in semiconductor device |
KR100468024B1 (en) * | 1997-06-30 | 2005-05-18 | 삼성전자주식회사 | Loc package |
-
1993
- 1993-09-07 JP JP22158693A patent/JPH0778910A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1101597C (en) * | 1996-11-08 | 2003-02-12 | 三星电子株式会社 | Lead-on-chip type semiconductor chip package using adhesive deposited on chip active surfaces in wafer level and method for manufacturing the same |
KR100234708B1 (en) * | 1996-12-18 | 1999-12-15 | Hyundai Micro Electronics Co | Blp type semiconductor package and mounting structure thereof |
KR100468024B1 (en) * | 1997-06-30 | 2005-05-18 | 삼성전자주식회사 | Loc package |
JP2004296690A (en) * | 2003-03-26 | 2004-10-21 | Shinko Electric Ind Co Ltd | Manufacturing method of multilayer circuit board with built-in semiconductor device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990202 |