JPH09326463A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH09326463A
JPH09326463A JP8114586A JP11458696A JPH09326463A JP H09326463 A JPH09326463 A JP H09326463A JP 8114586 A JP8114586 A JP 8114586A JP 11458696 A JP11458696 A JP 11458696A JP H09326463 A JPH09326463 A JP H09326463A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
semiconductor device
chip support
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8114586A
Other languages
Japanese (ja)
Inventor
Nobuhito Oouchi
伸仁 大内
Etsuo Yamada
悦夫 山田
Yasushi Shiraishi
靖 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP8114586A priority Critical patent/JPH09326463A/en
Priority to US08/848,286 priority patent/US5969410A/en
Priority to TW086105897A priority patent/TW408407B/en
Priority to KR1019970017636A priority patent/KR100373891B1/en
Priority to CNB971111677A priority patent/CN1135609C/en
Priority to DE69739619T priority patent/DE69739619D1/en
Priority to EP03022551A priority patent/EP1381084A1/en
Priority to EP97107671A priority patent/EP0807972B1/en
Publication of JPH09326463A publication Critical patent/JPH09326463A/en
Priority to US09/240,612 priority patent/US6258621B1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/787—Means for aligning
    • H01L2224/78703—Mechanical holding means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress cracks from growing to provide a thin device by contacting leads to a circuit forming face of a semiconductor element and adhering this element to a chip support with an insulation tape to thereby connect them, without fixing the leads to the circuit-forming face. SOLUTION: A semiconductor element 1 has a polyimide wafer coat 9 on a circuit-forming face and is mounted on a lead frame having leads 3 and chip support 10 between which the support 10 is adhered and fixed to the wafer coat 9 through an insulation tape 2 with the leads 3 not fixed to the wafer coat 9 but remaining in contact with the wafer coat 9. An Au wire plating on the upper surfaces of the leads 3 is connected to Au balls 5 on the semiconductor element 1 through Au wires 6 and the outside thereof is sealed with a resin 7 and cut off from the lead frame.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、樹脂封止型半導体
装置の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a resin-sealed semiconductor device.

【０００２】[0002]

【従来の技術】半導体素子や金線等を外部からの応力や
湿気、汚染から保護するのに、樹脂材で被覆してなる樹
脂封止型の半導体装置がある。2. Description of the Related Art There is a resin-encapsulated semiconductor device in which a semiconductor element, a gold wire or the like is covered with a resin material in order to protect it from external stress, moisture and contamination.

【０００３】図７は従来における樹脂封止型半導体装置
の一例を示す概略断面図である。この樹脂封止型半導体
装置は、半導体素子５１の表面に絶縁テープ５２を介し
てリード５３を接着するとともに、リード５３の上面に
施された金線メッキ５４と半導体素子５１上の金球５５
とを金線５６で接続し、さらにその外側が樹脂材５７で
封止された構造になっている。FIG. 7 is a schematic sectional view showing an example of a conventional resin-sealed semiconductor device. In this resin-encapsulated semiconductor device, the leads 53 are bonded to the surface of the semiconductor element 51 via the insulating tape 52, and the gold wire plating 54 applied to the upper surfaces of the leads 53 and the gold balls 55 on the semiconductor element 51.
Are connected with a gold wire 56, and the outside is further sealed with a resin material 57.

【０００４】ところで、この種の樹脂封止型半導体装置
は、ペレット（チップ）の大型化に伴い、パッケージ側
端５８と半導体素子５１との間の寸法が一段と狭くなる
傾向にある。これは、半導体素子５１が大きくなってい
るのに、これを収納するパッケージのサイズが規格化さ
れているため、大きくできないことに起因する。そこ
で、今日では、図７に示したように半導体素子５１の表
面に絶縁テープ５２でリード５３を接着させたＬＯＣ
（Lead On Chip）構造とした半導体装置が用いられるよ
うになって来ている。By the way, in this type of resin-sealed semiconductor device, the size between the package side end 58 and the semiconductor element 51 tends to become narrower as the size of the pellet (chip) increases. This is because the semiconductor element 51 is large, but the size of the package that accommodates the semiconductor element 51 is standardized, and therefore cannot be increased. Therefore, today, as shown in FIG. 7, the LOC in which the lead 53 is adhered to the surface of the semiconductor element 51 with the insulating tape 52 is used.
Semiconductor devices having a (Lead On Chip) structure have come to be used.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、半導体
装置の大きな課題として、基板実装時の熱によって、例
えば図８に示すように、樹脂材５７にクラック５９が生
じて機能を損ねることがある。原因は、空気中に保管さ
れたときに水分が吸収されて湿気ったところに、基板実
装時の熱で水分が蒸気化され、その力でクラックに至る
と考えられる。特に、絶縁テープ５２は水分を吸収し易
く、絶縁テープ５２の箇所からのクラックの発生が多
い。また、他の課題としては、半導体装置の薄型化に対
しては絶縁テープ５２があるため、余り適さない。However, as a major problem of the semiconductor device, there is a problem that the heat generated when the board is mounted causes cracks 59 in the resin material 57 to impair its function as shown in FIG. It is considered that the cause is that when stored in the air, the moisture is absorbed and humidified, and the heat at the time of mounting the board vaporizes the moisture, and the force causes cracks. In particular, the insulating tape 52 easily absorbs moisture, and cracks often occur at the insulating tape 52. Further, as another problem, the insulating tape 52 is not suitable for thinning the semiconductor device, which is not suitable.

【０００６】本発明は、上記問題点に鑑みてなされたも
のであり、その目的はクラックの発生を抑えて、かつ薄
型化が可能な樹脂封止型半導体装置を提供することにあ
る。The present invention has been made in view of the above problems, and an object of the present invention is to provide a resin-encapsulated semiconductor device capable of suppressing the occurrence of cracks and reducing the thickness.

【０００７】[0007]

【課題を解決するための手段】本発明は上記目的を達成
するために、次の技術手段を講じたことを特徴とする。
すなわち、半導体素子の表面にチップサポート及びリー
ドが延在されている樹脂封止型半導体装置において、前
記リードを前記半導体素子の回路形成面に当接させて前
記チップサポートと前記半導体素子の間を絶縁テープで
接着して、前記リードと前記回路形成面との間は固定せ
ずに接続してなる構成とした。Means for Solving the Problems The present invention is characterized by taking the following technical means in order to achieve the above object.
That is, in a resin-sealed semiconductor device in which a chip support and a lead are extended on the surface of a semiconductor element, the lead is brought into contact with a circuit forming surface of the semiconductor element so that a space between the chip support and the semiconductor element is provided. The leads and the circuit forming surface were bonded together with an insulating tape, and were connected without being fixed.

【０００８】この構成では、リードと回路形成面は接し
ているのみで特に固定するための材料がないのでリード
と半導体素子を含めた厚みは薄くできる。これにより、
全体の薄型化が可能になる。また、半導体素子を固定す
るのは、チップサポートに接着されている絶縁テープの
みであるため、従来装置の構造（図７及び図８参照）が
半導体と各リードの間に絶縁テープを配設していたのに
比べて、テープ面積は極めて少なくなる。これにより、
絶縁テープに起因するクラックの発生を抑えて品質を向
上させることができる。In this structure, since the leads and the circuit forming surface are only in contact with each other and there is no particular fixing material, the thickness including the leads and the semiconductor element can be reduced. This allows
The overall thickness can be reduced. Further, since the semiconductor element is fixed only by the insulating tape adhered to the chip support, the structure of the conventional device (see FIGS. 7 and 8) has an insulating tape disposed between the semiconductor and each lead. However, the tape area is extremely small. This allows
It is possible to suppress the occurrence of cracks due to the insulating tape and improve the quality.

【０００９】[0009]

【発明の実施の形態】図１及び図２は本発明の第１の形
態例としての樹脂封止型半導体装置を示すもので、図１
はその装置の縦断側面図、図２は図１とは異なる部分で
断面してその装置の要部構造を示す縦断側面図である。
また、図３は本発明に係る樹脂封止型半導体装置の配置
例を製造途中の状態で示す図である。1 and 2 show a resin-sealed semiconductor device according to a first embodiment of the present invention.
2 is a vertical cross-sectional side view of the device, and FIG. 2 is a vertical cross-sectional side view showing a main part structure of the device in cross section at a portion different from FIG.
Further, FIG. 3 is a view showing an arrangement example of the resin-encapsulated semiconductor device according to the present invention in a state of being manufactured.

【００１０】そこで、図３に示す製造途中の状態図と共
に図１及び図２の樹脂封止型半導体装置の構造を説明す
ると、半導体素子１は回路形成面の上にポリイミドウエ
ハコート９が設けられている。この半導体素子１は、リ
ード３とチップサポート１０とが形成されている厚みが
約０．１２５ミリのリードフレーム１２に搭載される。
このとき、チップサポート１０と半導体素子１との間に
は約０．１５ミリの厚みを有した絶縁テープ２が介装さ
れ、この絶縁テープ２でチップサポート１０とポリイミ
ドウエハコート９との間が接着固定される。これに対し
て、リード３とポリイミドウエハコート９との間は接し
た状態におかれるが、特に固定はされない。図３はこの
ようにしてリードフレーム１２に半導体素子１が配置さ
れている状態を示している。The structure of the resin-encapsulated semiconductor device shown in FIGS. 1 and 2 will now be described with reference to the state diagram during manufacturing shown in FIG. 3. The semiconductor element 1 is provided with a polyimide wafer coat 9 on the circuit formation surface. ing. The semiconductor element 1 is mounted on a lead frame 12 having a lead 3 and a chip support 10 and a thickness of about 0.125 mm.
At this time, the insulating tape 2 having a thickness of about 0.15 mm is interposed between the chip support 10 and the semiconductor element 1, and the insulating tape 2 is provided between the chip support 10 and the polyimide wafer coat 9. Adhesively fixed. On the other hand, although the lead 3 and the polyimide wafer coat 9 are kept in contact with each other, they are not particularly fixed. FIG. 3 shows a state in which the semiconductor element 1 is arranged on the lead frame 12 in this way.

【００１１】次に、リード３の上面に施されている金線
メッキ（不図示）と半導体素子１上の金球５とを金線６
で接続し、さらにその外側が樹脂材７で封止されるとと
もに、リードフレーム１２より切り離すと図１及び図２
に示す樹脂封止型半導体装置が完成される。また、この
樹脂封止型半導体装置におけるチップサポート１０は、
半導体素子１の端部外側で絶縁テープ２の略厚み分（約
０．１５ミリ）だけ曲げ加工（図２中に符号１１で示す
部分）されている。Next, the gold wire plating (not shown) provided on the upper surface of the lead 3 and the gold ball 5 on the semiconductor element 1 are connected to the gold wire 6.
1 and FIG. 2 when the outside is sealed with the resin material 7 and separated from the lead frame 12.
The resin-encapsulated semiconductor device shown in is completed. Further, the chip support 10 in this resin-sealed semiconductor device is
Outside the end of the semiconductor element 1, the insulating tape 2 is bent by a thickness (about 0.15 mm) (a portion indicated by reference numeral 11 in FIG. 2).

【００１２】したがって、第１の形態例としての樹脂封
止型半導体装置の構造では、リード３と回路形成面であ
るポリイミドウエハコート９は接しているのみで特に固
定するための材料がないのでリード３と半導体素子１を
含めた厚みは薄くできる。これにより、全体の薄型化が
可能になる。また、半導体素子１を固定するのは、チッ
プサポート１０に接着されている絶縁テープ２のみであ
るため、従来装置の構造（図７及び図８参照）が半導体
と各リードの間に絶縁テープを配設していたのに比べ
て、テープ面積は極めて少なくなる。これにより、絶縁
テープ２の水分吸収が減り、基板実装時に生じる熱によ
るクラックの発生を抑えることができ、品質を向上させ
ることができる。Therefore, in the structure of the resin-encapsulated semiconductor device as the first embodiment, the lead 3 and the polyimide wafer coat 9 which is the circuit forming surface are only in contact with each other, and there is no particular fixing material. 3 and the semiconductor element 1 can be thinned. As a result, the overall thickness can be reduced. Further, since the semiconductor element 1 is fixed only by the insulating tape 2 bonded to the chip support 10, the structure of the conventional device (see FIGS. 7 and 8) has an insulating tape between the semiconductor and each lead. The tape area is extremely small as compared with the case where the tape is arranged. As a result, moisture absorption of the insulating tape 2 is reduced, and it is possible to suppress the generation of cracks due to heat generated when mounting the board, and it is possible to improve the quality.

【００１３】図４及び図５は本発明の第２の形態例とし
ての樹脂封止型半導体装置を示すもので、図４はその装
置の縦断側面図、図５は図４とは異なる部分で断面して
その装置の要部構造を示す縦断側面図である。また、図
６は本発明に係る樹脂封止型半導体装置の配置例を製造
途中の状態で示す図である。なお、図４乃至図６におい
て図１乃至図３と同一符号を付したものは図１乃至図３
と同一のものを示している。FIGS. 4 and 5 show a resin-sealed semiconductor device as a second embodiment of the present invention. FIG. 4 is a vertical sectional side view of the device, and FIG. 5 is a portion different from FIG. FIG. 3 is a vertical cross-sectional side view showing a structure of a main part of the device in cross section. Further, FIG. 6 is a view showing an arrangement example of the resin-encapsulated semiconductor device according to the present invention in a state of being manufactured. 4 to FIG. 6 are denoted by the same reference numerals as those in FIG. 1 to FIG.
It shows the same thing as.

【００１４】そこで、図６に示す製造途中の状態図と共
に図４及び図５の樹脂封止型半導体装置の構造を説明す
ると、図４乃至図６において、半導体素子１は回路形成
面の上にポリイミドウエハコート９が設けられている。
この半導体素子１は、リード３とチップサポート１０と
が形成されているリードフレーム１２に搭載される。こ
のとき、リード３とポリイミドウエハコート９との間は
固定はされずに、単に接した状態におかれる。これに対
して、チップサポート１０は、ポリイミドウエハコート
９と略面一で、かつ先端が半導体素子１の端側部分との
間に所定の隙間Ｓ（図５参照）を保って突き出されて非
接触の状態で配置され、さらにポリイミドウエハコート
９の上面とチップサポート１０の上面とにまたがって絶
縁テープ２が貼り付けられ、この絶縁テープ２でポリイ
ミドウエハコート９とチップサポート１０の間が接着さ
れて固定される。図６はこのようにしてリードフレーム
１２に半導体素子１が配置されている状態を示してい
る。The structure of the resin-encapsulated semiconductor device shown in FIGS. 4 and 5 will now be described with reference to the state diagram during manufacturing shown in FIG. 6, and in FIGS. 4 to 6, the semiconductor element 1 is placed on the circuit formation surface. A polyimide wafer coat 9 is provided.
The semiconductor element 1 is mounted on a lead frame 12 on which the leads 3 and the chip support 10 are formed. At this time, the lead 3 and the polyimide wafer coat 9 are not fixed but are simply in contact with each other. On the other hand, the chip support 10 is substantially flush with the polyimide wafer coat 9 and has a tip protruding from the end side portion of the semiconductor element 1 with a predetermined gap S (see FIG. 5) being kept therebetween. The insulating tape 2 is placed in contact with the polyimide wafer coat 9 and the chip support 10 over the upper surface of the polyimide wafer coat 9 and the upper surface of the chip support 10. The insulating tape 2 bonds the polyimide wafer coat 9 and the chip support 10 together. Fixed. FIG. 6 shows a state in which the semiconductor element 1 is arranged on the lead frame 12 in this way.

【００１５】次に、リード３の上面に施されている金線
メッキ（不図示）と半導体素子１上の金球５とを金線６
で接続し、さらにその外側が樹脂材７で封止されるとと
もに、リードフレーム１２より切り離すと図４及び図５
に示す樹脂封止型半導体装置が完成される。また、この
樹脂封止型半導体装置におけるリード３は、半導体素子
１の端部外側で下方（半導体素子１側）に曲げ加工（図
４中に符号２１で示す部分）されている。Next, the gold wire plating (not shown) provided on the upper surface of the lead 3 and the gold ball 5 on the semiconductor element 1 are connected to the gold wire 6.
4 and FIG. 5 when the outside is sealed with the resin material 7 and separated from the lead frame 12.
The resin-encapsulated semiconductor device shown in is completed. The leads 3 in this resin-encapsulated semiconductor device are bent downward (on the side of the semiconductor element 1) outside the end of the semiconductor element 1 (the portion indicated by reference numeral 21 in FIG. 4).

【００１６】したがって、第２の形態例としての樹脂封
止型半導体装置の構造では、リード３と回路形成面であ
るポリイミドウエハコート９は接しているのみで特に固
定するための材料がないのでリード３と半導体素子１を
含めた厚みは薄くできる。これにより、全体の薄型化が
可能になる。また、半導体素子１を固定するのは、ポリ
イミドウエハコート９とチップサポート１０とにまたが
って接着されている絶縁テープ２のみであるため、従来
装置の構造（図７及び図８参照）が半導体と各リードの
間に絶縁テープを配設していたのに比べて、テープ面積
は極めて少なくなる。これにより、絶縁テープ２の水分
吸収が減り、基板実装時に生じる熱によるクラックの発
生を抑え、品質を向上させることができる。Therefore, in the structure of the resin-encapsulated semiconductor device as the second embodiment, the lead 3 and the polyimide wafer coat 9 as the circuit forming surface are only in contact with each other, and there is no particular material for fixing. 3 and the semiconductor element 1 can be thinned. As a result, the overall thickness can be reduced. Further, since the semiconductor element 1 is fixed only by the insulating tape 2 which is adhered across the polyimide wafer coat 9 and the chip support 10, the structure of the conventional device (see FIGS. 7 and 8) is a semiconductor device. The tape area is extremely small as compared with the case where the insulating tape is arranged between the leads. Thereby, moisture absorption of the insulating tape 2 is reduced, cracks due to heat generated at the time of mounting on the substrate are suppressed, and the quality can be improved.

【００１７】[0017]

【発明の効果】以上説明したとおり、本発明の樹脂封止
型半導体装置によれば、全体の薄型化が可能になるとと
もに、接着用の絶縁テープに起因するクラックの発生を
抑えて品質を向上させることができる。As described above, according to the resin-encapsulated semiconductor device of the present invention, it is possible to reduce the thickness of the entire device and suppress the occurrence of cracks due to the insulating tape for bonding to improve the quality. Can be made.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の形態例として示す樹脂封止型半
導体装置の縦断側面図である。FIG. 1 is a vertical sectional side view of a resin-encapsulated semiconductor device shown as a first embodiment of the present invention.

【図２】図１とは異なる部分で断面して同上装置を示す
要部縦断側面図である。FIG. 2 is a vertical cross-sectional side view of an essential part showing the same device as shown in FIG.

【図３】第１の形態例に係る同上装置の配置例を製造途
中の状態で示す図である。FIG. 3 is a view showing an arrangement example of the same apparatus according to the first embodiment in the state of being manufactured.

【図４】本発明の第２の形態例として示す樹脂封止型半
導体装置の縦断側面図である。FIG. 4 is a vertical sectional side view of a resin-sealed semiconductor device shown as a second embodiment of the present invention.

【図５】図４とは異なる部分で断面して同上装置を示す
要部縦断側面図である。FIG. 5 is a vertical cross-sectional side view of essential parts showing the same device as shown in FIG.

【図６】第２の形態例に係る同上装置の配置例を製造途
中の状態で示す図である。FIG. 6 is a view showing an arrangement example of the same apparatus according to the second embodiment in the state of being manufactured.

【図７】従来装置の一例を示す断面図である。FIG. 7 is a cross-sectional view showing an example of a conventional device.

【図８】従来装置の問題点を説明するための断面図であ
る。FIG. 8 is a cross-sectional view for explaining a problem of the conventional device.

【符号の説明】[Explanation of symbols]

１ 半導体素子 ２ 絶縁テープ ３ リード ７ 封止用樹脂材 ９ ポリイミドウエハコート １０ チップサポート １１，２１ 曲げ加工 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Insulation tape 3 Lead 7 Resin material for sealing 9 Polyimide wafer coat 10 Chip support 11 and 21 Bending process

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子の表面にチップサポート及び
リードが延在されている樹脂封止型半導体装置におい
て、 前記リードを前記半導体素子の回路形成面に当接させて
前記チップサポートと前記半導体素子の間を絶縁テープ
で接着して、前記リードと前記回路形成面との間は固定
せずに接続してなることを特徴とする樹脂封止型半導体
装置。1. A resin-encapsulated semiconductor device in which a chip support and a lead extend on the surface of a semiconductor element, wherein the lead is brought into contact with a circuit formation surface of the semiconductor element and the chip support and the semiconductor element. The resin-sealed semiconductor device is characterized in that the leads and the circuit forming surface are connected to each other without being fixed by bonding them with an insulating tape. 【請求項２】 前記回路形成面上で前記リードとの間に
前記絶縁テープを挟んで前記リードと前記チップサポー
トを接着するとともに、 前記半導体素子の端部外側で前記チップサポートが前記
絶縁テープの略厚み分だけ前記半導体素子側に曲げ加工
されている請求項１に記載の樹脂封止型半導体装置。2. The insulating tape is sandwiched between the lead and the chip support on the circuit formation surface to bond the lead and the chip support, and the chip support is formed of the insulating tape outside the end of the semiconductor element. The resin-encapsulated semiconductor device according to claim 1, wherein the resin-encapsulated semiconductor device is bent on the side of the semiconductor element by substantially the thickness. 【請求項３】 前記回路形成面の外側で前記回路形成面
と略面一状にして前記チップサポートを配置し、前記回
路形成面と前記チップサポートにまたがって前記絶縁テ
ープを貼り付けて前記回路形成面と前記チップサポート
とを接着するとともに、 前記半導体素子の端部外側で前記リードが前記半導体素
子側に曲げ加工されている請求項１に記載の樹脂封止型
半導体装置。3. The circuit board is arranged on the outside of the circuit forming surface so as to be substantially flush with the circuit forming surface, and the insulating tape is attached to the circuit forming surface and the chip support. The resin-encapsulated semiconductor device according to claim 1, wherein the formation surface and the chip support are bonded together, and the leads are bent outside the end of the semiconductor element toward the semiconductor element.
JP8114586A 1996-05-09 1996-05-09 Resin-sealed semiconductor device Pending JPH09326463A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP8114586A JPH09326463A (en) 1996-05-09 1996-05-09 Resin-sealed semiconductor device
US08/848,286 US5969410A (en) 1996-05-09 1997-04-29 Semiconductor IC device having chip support element and electrodes on the same surface
TW086105897A TW408407B (en) 1996-05-09 1997-05-03 Semiconductor device and method of its fabrication method
KR1019970017636A KR100373891B1 (en) 1996-05-09 1997-05-08 Semiconductor device and method of its fabrication
CNB971111677A CN1135609C (en) 1996-05-09 1997-05-09 Semiconductor device and method of its fabrication
DE69739619T DE69739619D1 (en) 1996-05-09 1997-05-09 Semiconductor arrangement and manufacturing method
EP03022551A EP1381084A1 (en) 1996-05-09 1997-05-09 Semiconductor device and method of its fabrication
EP97107671A EP0807972B1 (en) 1996-05-09 1997-05-09 Semiconductor device and method of its fabrication
US09/240,612 US6258621B1 (en) 1996-05-09 1999-02-01 Method of fabricating a semiconductor device having insulating tape interposed between chip and chip support

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8114586A JPH09326463A (en) 1996-05-09 1996-05-09 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH09326463A true JPH09326463A (en) 1997-12-16

Family

ID=14641569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8114586A Pending JPH09326463A (en) 1996-05-09 1996-05-09 Resin-sealed semiconductor device

Country Status (3)

Country Link
JP (1) JPH09326463A (en)
CN (1) CN1135609C (en)
TW (1) TW408407B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3882712B2 (en) * 2002-08-09 2007-02-21 住友電気工業株式会社 Submount and semiconductor device
US7253506B2 (en) * 2003-06-23 2007-08-07 Power-One, Inc. Micro lead frame package
US7663211B2 (en) * 2006-05-19 2010-02-16 Fairchild Semiconductor Corporation Dual side cooling integrated power device package and module with a clip attached to a leadframe in the package and the module and methods of manufacture
US7489026B2 (en) * 2006-10-31 2009-02-10 Freescale Semiconductor, Inc. Methods and apparatus for a Quad Flat No-Lead (QFN) package

Also Published As

Publication number Publication date
CN1135609C (en) 2004-01-21
CN1166053A (en) 1997-11-26
TW408407B (en) 2000-10-11

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