CN1166053A - Semiconductor device and method of its fabrication - Google Patents
Semiconductor device and method of its fabrication Download PDFInfo
- Publication number
- CN1166053A CN1166053A CN97111167A CN97111167A CN1166053A CN 1166053 A CN1166053 A CN 1166053A CN 97111167 A CN97111167 A CN 97111167A CN 97111167 A CN97111167 A CN 97111167A CN 1166053 A CN1166053 A CN 1166053A
- Authority
- CN
- China
- Prior art keywords
- semiconductor element
- lead
- wire
- chip set
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/787—Means for aligning
- H01L2224/78703—Mechanical holding means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.
Description
The present invention relates to the structure of semiconductor device, specifically, relate to the structure and the manufacture method thereof of the semiconductor device of Plastic Package.
In recent years, in plastic packaging semiconductor device, chip size is increasing, and between the encapsulation edge and the size of semiconductor element trend towards more and more littler.Although this is because the size of semiconductor element becomes increasing,, the package dimension of adorning it can not increase but by standardization.Therefore, in order to address such a problem, the plastic packaging semiconductor device of LOC type (lead-in wire is on the chip) structure that the open 6-105721 of Japan Patent is disclosed is used.
This LOC type structural plastic encapsulated semiconductor device is to constitute like this, make lead-in wire be bonded on the semiconductor component surfaces with insulating tape, by gold thread the gold thread coating that is plated in the lead-in wire end face is connected with gold goal on the semiconductor element electrode, in addition, they all seal with resin material.
But such situation for example, takes place: because the heat that produces when onboard (on a board) being installed can make the resin material cracking, cause function impaired in subject matter as this traditional plastic packaging semiconductor device sometimes.If resin material absorbs moisture and becomes tide when semiconductor device is kept in the air, moisture is subjected to thermal evaporation when then installing onboard, and consequent power causes cracking.The trend of insulating tape absorption moisture is particularly evident, makes insulating tape often ftracture on every side.In addition.As another problem, because insulating tape is arranged, the reducing of semiconductor device thickness is restricted.
The present invention makes in view of the above problems.Therefore, the purpose of this invention is to provide a kind of plastic packaging semiconductor device of ftractureing of can preventing, and make it attenuation, and its manufacture method is provided.
The invention is characterized in, also provide chip set except lead-in wire, only chip set is fixed on the semiconductor element, lead-in wire then is not fixed on the chip, and the electrode of semiconductor element is connected with lead-in wire.
Adopt this structure, because the special material that fixes them of no use between lead-in wire and the semiconductor component surfaces, so the combination thickness of lead-in wire and semiconductor element can attenuate.Thereby the thickness of entire semiconductor device can attenuate.In addition, insulating tape only is used for semiconductor element is bonded on the chip set, so the insulating tape area that will use is very little.Therefore, insulating tape intrinsic cracking prevented that thereby quality is improved.
Fig. 1 is a profile, and expression is by the structure at the relevant position of semiconductor device of Plastic Package of the present invention and the layout of lead-in wire;
Fig. 2 is a profile, and expression is by the structure at the relevant position of plastic packaging semiconductor device of first embodiment of the invention and the layout of chip set;
Fig. 3 is a top view, is illustrated in the plastic packaging semiconductor device by first embodiment of the invention in the manufacture process;
Fig. 4 is a profile, and expression is by the structure at the relevant position of semiconductor device of the Plastic Package of second embodiment of the invention and the layout of lead-in wire;
Fig. 5 is the profile by the layout of the plastic packaging semiconductor device of second embodiment of the invention and chip set;
Fig. 6 is a top view, is illustrated in the plastic packaging semiconductor device by second embodiment of the invention in the manufacture process;
Fig. 7 is a top view, is illustrated in the plastic packaging semiconductor device by third embodiment of the invention in the manufacture process;
Fig. 8 is the profile of A-A ' line in Fig. 7, and expression is by the structure of the plastic packaging semiconductor device essential part of third embodiment of the invention;
Fig. 9 is the profile of B-B ' line in Fig. 7, and expression is by the structure of the plastic packaging semiconductor device essential part of third embodiment of the invention;
Figure 10 A and 10B are the schematic diagrames by the manufacture process of the plastic packaging semiconductor device of third embodiment of the invention;
Figure 11 is a profile, and expression is by the structure of the plastic packaging semiconductor device essential part of fourth embodiment of the invention;
Figure 12 is the schematic diagram by the manufacture process of the plastic packaging semiconductor device of fourth embodiment of the invention;
Figure 13 is the schematic diagram by the manufacture process of the plastic packaging semiconductor device of fifth embodiment of the invention; And
Figure 14 is the schematic diagram by the manufacture process of the plastic packaging semiconductor device of sixth embodiment of the invention;
First embodiment
Fig. 1 and Fig. 2 are profiles, and expression is by the structure at the relevant position of plastic packaging semiconductor device of first embodiment of the invention.Fig. 1 is the figure that expression lead-in wire is arranged, and Fig. 2 is the figure that expression chip set (only draw one of them) is arranged.Fig. 3 is a top view, is illustrated in the plastic packaging semiconductor device by first embodiment of the invention in the manufacture process;
On the circuit formation face of semiconductor element 1, apply polyimides wafer coating 9.This semiconductor element 1 is contained on the lead frame 12 of the about 0.125mm of thickness, and the latter comprises lead-in wire 3 and chip set 10.Insulating tape 2 thick about 0.15mm insert between semiconductor element 1 and the chip set 10, and by means of this insulating tape 2, chip set 10 and polyimides wafer coating 9 are bondd and be fixed together.Chip set 10 (Fig. 2 is marked with digital 11 places) bending outside semiconductor element 1 edge is firm substantially what a thickness (about 0.15mm).On the contrary, lead-in wire 3 only contacts with each other with polyimides wafer coating 9, and unfixing.The bottom surface 10a (beyond the sweep 11) of chip set 10 and polyimides wafer coating 9 are basically on same plane.State when Fig. 3 represents that semiconductor element 1 is placed on the lead frame 12 with such method.
Then, the gold thread coating (not shown) of the end face that is plated in lead-in wire 3 is connected with gold goal 5 on the semiconductor element 1, they is sealed with resin material 7 with gold thread 6, will go between again 3 and chip set 10 cut off from lead frame 12.Then, as depicted in figs. 1 and 2, plastic packaging semiconductor device is promptly accused and is finished.
As mentioned above, in the structure according to the plastic packaging semiconductor device of first embodiment, lead-in wire 3 contacts any material that fixes them of no use between them with 9 of the polyimides wafer coatings on formation semiconductor element 1 surface.Just because of this, the combination thickness of lead-in wire 3 and semiconductor element 1 can attenuate.Therefore, the thickness of entire semiconductor device can attenuate.The insulating tape 2 that 1 usefulness of semiconductor device is bonded on the chip set 10 is fixing.Therefore, the area of insulating tape is quite little.So the moisture that insulating tape absorbs can reduce, thereby the phenomenon of cracking appears can avoid installing onboard the time.Therefore, quality is improved.
Second embodiment
Figure 4 and 5 all are profiles, and expression is by the structure at the relevant position of plastic packaging semiconductor device of second embodiment of the invention.Fig. 4 represents the layout that goes between.And Fig. 5 represents the layout of chip set (only draw one of them).Fig. 6 is a top view, is illustrated in the plastic packaging semiconductor device by second embodiment of the invention in the manufacture process.With reference to Fig. 4 to Fig. 6, identical or corresponding member uses the label identical with Fig. 1 to Fig. 3 to indicate.
On the circuit formation face of semiconductor element 1, be covered with polyimides wafer coating 9.Semiconductor element 1 is placed on the lead frame 12, and the latter comprises lead-in wire 3 and chip set 10.Lead-in wire 3 contacts with 9 of polyimides wafer coatings, does not fix.Lead-in wire 3 is (position of label 21 indications in Fig. 4) (towards semiconductor element 1) bending downwards outside semiconductor 1 border.The end face 3a (beyond the crooked position, in the encapsulating material) of each lead-in wire 3 and polyimides wafer coating 9 are basically on same plane.The position of each chip set 10 is to determine like this, makes its surface of end face 10b and polyimides wafer coating 9 basically on same plane, and its lateral boundaries terminal and semiconductor element 1 separates predetermined gap 5 (Fig. 5).In addition, paste insulating tape 2, between the end face of the end face of polyimides wafer coating 9 and chip set 10, and polyimides wafer coating 9 and chip set 10 are bondd and fix with this insulating tape 2.Fig. 6 represents with such method semiconductor element 1 to be placed on state on the lead frame 12.
Then, will be plated in the gold thread coating (not shown) of lead-in wire on 3 end faces with gold thread 6 and be connected with semiconductor element 1, usefulness resin material 7 seals them, and will go between 3 and chip set 10 cut off from lead frame 12.Then, as 4 and 5 described, plastic packaging semiconductor device is promptly accused and is finished.
As mentioned above, in the structure according to the plastic packaging semiconductor device of second embodiment, lead-in wire 3 just contacts any material that fixes them of no use between them with the polyimides wafer coating 9 that forms on semiconductor element 1 surface.Just because of this, the combination thickness of lead-in wire 3 and semiconductor element 1 can attenuate.Therefore, the thickness of entire semiconductor device can attenuate.In addition, because 1 of semiconductor device is fixing with insulating tape 2, the latter is across between polyimides wafer coating 9 and the chip set 10, so the area of insulating tape 2 is very little.So the moisture that insulating tape 2 absorbs can reduce, thereby the phenomenon of cracking appears can avoid installing onboard the time.Therefore, quality is improved.
The 3rd embodiment
Fig. 7 to 9 expression is by the structure of the plastic packaging semiconductor device of third embodiment of the invention.Fig. 7 is a top view, is illustrated in the plastic packaging semiconductor device by third embodiment of the invention in the manufacture process.Fig. 8 and 9 is profiles, the structure of expression relative section.Fig. 8 is the profile along Fig. 7 center line A-A '.Fig. 9 is the profile along Fig. 7 center line B-B '.With reference to Fig. 7 to Fig. 9, identical or corresponding member uses the label identical with Fig. 1 to Fig. 6 to indicate.
On the circuit formation face of semiconductor element 1, be covered with polyimides wafer coating 9.Chip set 10 usefulness insulating tapes 2 are bonded on the polyimides wafer coating 9.Basically forming chip set 10 and lead-in wire 3 on the same plane.As shown in Figure 8, chip set 10 usefulness insulating tapes 2 are bonded on the surface of semiconductor element 1.In addition, as shown in Figure 9, will be plated in the gold thread coating 4 of lead-in wire on 3 end faces with gold thread 6 and be connected with gold goal on the electrode (not shown) that is arranged on semiconductor element 1, will go between with this 3 is connected with the electrode of semiconductor element 1.It is 3 non-caked on semiconductor element 1 to go between, but keeps separately.That is to say, lead-in wire 3 be placed on semiconductor element 1 above, each other from a gap 31, resin 7 fillings that this gap 31 usefulness melt.
Like this, insulating tape 2 does not just appear at the part below the lead-in wire 3, and 2 of insulating tapes are used on the chip set 10.Just because of this, the consumption of insulating tape 2 can significantly reduce, thus the absorption of restriction moisture.In addition, because chip set 10 forms on same plane with lead-in wire 3, so can save the step of handling lead frame such as bending etc.
The manufacture method of the plastic packaging semiconductor device shown in Fig. 7 to 9 then, is described with reference to Figure 10 A and Figure 10 B.At first, the semiconductor element 1 of having gone up the chip set 10 of lead frame 12 with insulating tape 2 bonding is placed in the hot piece 13 shown in Figure 10 A.At this moment, in lead frame 12, lead-in wire 3 and chip set 10 and go between 3 in air basically at grade, leave the thickness of semiconductor element 1 firm what a insulating tape 2, and the latter is fixed on chip set 10 and the semiconductor element 1.
Then, shown in Figure 10 B, clamp lead-in wire 3 and semiconductor elements 1, lead-in wire 3 is contacted with semiconductor element 1 with the cable guide 14 that is positioned on the lead-in wire 3 and the upper surface of hot piece 13.After this, by means of the wire bonding method that utilizes gold thread 6 gold plate 4 of lead-in wire 3 is connected with gold goal 5 on the semiconductor element 1.Then, decontrol the former cable guide that fixes 14, lead-in wire 3 is got back to the position shown in Figure 10 A, and semiconductor element 1, lead-in wire 3, gold thread 6 and chip set 10 under this state (referring to Fig. 8 and 9) resin material 7 sealings.Use this method, not bending lead 3 or chip set 10 just can obtain to have only chip set 10 to be fixed on plastic packaging semiconductor device (referring to Fig. 7 to 9) on the semiconductor element 1.
The 4th embodiment
Figure 11 is a profile, and expression is by the structure of the plastic packaging semiconductor device relative section of fourth embodiment of the invention.Figure 12 represents the manufacture method of plastic packaging semiconductor device shown in Figure 11.With reference to Figure 11 and Figure 12, identical or corresponding member uses the label identical with Fig. 1 to Figure 10 to indicate.
In general, identical by the plastic packaging semiconductor device of fourth embodiment of the invention with the plastic packaging semiconductor device of above-mentioned the 3rd embodiment, but difference is following several aspect.That is the end 15 of lead-in wire 3 is bent upwards from the surface of semiconductor element 1 in the plastic packaging semiconductor device shown in Figure 11.Therefore, in manufacture process when cable guide 14 and hot piece 13 clamps lead-in wire 3 and semiconductor element 1, polyimides wafer coating 9 on the not direct contact semiconductor element 1 of the end of lead-in wire 3, the bottom surface of Wan Qu lead-in wire 3 ends 15 contacts with polyimides wafer coating 9.Just because of this, just can prevent to go between and 3 on semiconductor element 1, cause blemish.
The 5th embodiment
Figure 13 represents the manufacture method by the plastic packaging semiconductor device of fifth embodiment of the invention.With reference to Figure 13, identical or corresponding member uses the label identical with Fig. 1 to Figure 12 to indicate.Suppose, identical by the structure of the plastic packaging semiconductor device of this 5th embodiment of the present invention with the plastic packaging semiconductor device of above-mentioned the 3rd embodiment.
In the manufacture process of this plastic packaging semiconductor device of pressing this 5th embodiment of the present invention, utilization contains the cable guide 16 of electromagnet, do not make under lead-in wire 3 and the situation that the surface of semiconductor element 1 contact, the gold goal 5 on the gold thread coating 4 and semiconductor element 1 couples together on 3 going between.With reference to Figure 13, at first the semiconductor element 1 of having gone up chip set 10 with insulating tape 2 bonding is placed in the hot piece 13.At this moment carve, lead-in wire 3 leaves semiconductor element 1, the thickness that chip set 10 is bonded in the insulating tape 2 on the semiconductor element 1 of being separated by in air.
Then, the cable guide 16 that will contain electromagnet is placed on the end face of lead-in wire 3, and by means of the magnetic force of the cable guide 16 that contains electromagnet, lead-in wire 3 is fixed on the bottom surface of the cable guide 16 that contains electromagnet, and in this state, utilize the gold goal 5 on 6 pairs of lead-in wires 3 of gold thread and the semiconductor element 1 to carry out wire bond.Connect gold goal 5 and lead-in wire 3 with such method, just can prevent the blemish of semiconductor element 1 and the distortion of lead-in wire 3.
Manufacture method according to the 5th embodiment is suitable for above-mentioned plastic packaging semiconductor device according to the 4th embodiment equally.
The 6th embodiment
Figure 14 represents the manufacture method by the plastic packaging semiconductor device of sixth embodiment of the invention.With reference to Figure 14, identical or corresponding member uses the label identical with Fig. 1 to Figure 13 to indicate.Suppose, identical by the structure of this plastic packaging semiconductor device of this 6th embodiment of the present invention with the plastic packaging semiconductor device of the 3rd embodiment shown in above-mentioned Fig. 7 to 9.
In manufacture process, utilize the hot piece 17 that contains electromagnet that lead-in wire 3 is contacted with the surface of semiconductor element 1 by the plastic packaging semiconductor device of sixth embodiment of the invention.With reference to Figure 14, at first the semiconductor element 1 of having gone up chip set 10 with insulating tape 2 bonding is placed in the hot piece 17 that contains electromagnet.Then, make hot piece 17 work that contain electromagnet, and, lead-in wire 3 is pulled to the surface of semiconductor element 1, and contact with it by means of this magnetic force.In this state, utilize gold thread 6 to connect gold goal 5 and lead-in wire 3.Connect gold goal 5 and lead-in wire 3 with such method, just can stably be fixed up lead-in wire 3 without cable guide.
Manufacture method according to the 6th embodiment is suitable for above-mentioned plastic packaging semiconductor device according to the 4th embodiment shown in Figure 11 equally.
As mentioned above, according to plastic packaging semiconductor device of the present invention and manufacture method thereof, just can make entire semiconductor device thinner.In addition, the insulating tape of the usefulness that can prevent to bond the phenomenon of intrinsic generation cracking, thereby can improve the quality.
Claims (10)
1. semiconductor device is characterized in that comprising:
The semiconductor element that electrode is arranged in its surface;
The lead-in wire that is connected with described electrode;
Extend in the chip set on the semiconductor component surfaces; And
Insulating tape is arranged between chip set and the described semiconductor element, is used for chip set is bonded on the semiconductor element.
2. the semiconductor device that proposes of claim 1 is characterized in that:
Described chip set beyond the semiconductor element border, according to basically just the stroke of the thickness of what a insulating tape, to the bending of semiconductor element direction.
3. semiconductor device is characterized in that comprising:
The semiconductor element that electrode is arranged in its surface;
The lead-in wire that is connected with described electrode;
Chip set, its upper surface be positioned at beyond the semiconductor element edge, with the surface of semiconductor element basically on same plane; And
Insulating tape between chip set and described semiconductor element, is used for chip set is bonded on the semiconductor element, wherein,
Described lead-in wire outside the semiconductor element edge towards the bending of semiconductor element direction.
4. the semiconductor device that proposes of claim 1 is characterized in that:
Lead-in wire is connected with wire bonding method with semiconductor element.
5. semiconductor device is characterized in that comprising:
The semiconductor element that electrode is arranged in its surface;
Be positioned at the lead-in wire of the position that separates with semiconductor component surfaces;
Be bonded in the lip-deep chip set of semiconductor element; And
The lead that connects described electrode and described lead-in wire.
6. a method of making semiconductor device is characterized in that comprising the following steps:
Preparation has the lead-in wire that the semiconductor element and comprising of electrode forms basically and the lead frame of chip set in its surface on same plane;
Chip set is bonded on the surface of semiconductor element, lead-in wire is arranged on the position of leaving described surface on the semiconductor component surfaces again; And
Making under described lead-in wire and the situation that described semiconductor component surfaces contacts, described lead-in wire and described electrode are coupled together.
7. the method that proposes of claim 6 is characterized in that:
The endwise skew of described lead-in wire leaves the surface of semiconductor element.
8. the method that proposes of claim 6 is characterized in that:
Lead-in wire and electrode step of connecting are comprised with the hot piece that is positioned at the semiconductor element lower surface and the cable guide clamping semiconductor element and the lead-in wire that are positioned at the lead-in wire upper surface, lead-in wire is contacted with semiconductor element.
9. the method that proposes of claim 6 is characterized in that:
Lead-in wire and electrode step of connecting comprised making to go between with the hot piece that is positioned at the semiconductor element lower surface that contains electromagnet contact with semiconductor element.
10. a method of making semiconductor device is characterized in that comprising the following steps:
Preparation has the lead-in wire that the semiconductor element and comprising of electrode forms basically and the lead frame of chip set in its surface on same plane;
Chip set is bonded on the surface of semiconductor element, lead-in wire is arranged on the position of leaving described surface on the semiconductor component surfaces again; And
The cable guide that will contain electromagnet is placed on the upper surface of lead-in wire, and these lead-in wires are coupled together with described electrode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP114586/1996 | 1996-05-09 | ||
| JP8114586A JPH09326463A (en) | 1996-05-09 | 1996-05-09 | Resin-sealed semiconductor device |
| JP114586/96 | 1996-05-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1166053A true CN1166053A (en) | 1997-11-26 |
| CN1135609C CN1135609C (en) | 2004-01-21 |
Family
ID=14641569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB971111677A Expired - Fee Related CN1135609C (en) | 1996-05-09 | 1997-05-09 | Semiconductor device and method of its fabrication |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH09326463A (en) |
| CN (1) | CN1135609C (en) |
| TW (1) | TW408407B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100342510C (en) * | 2002-08-09 | 2007-10-10 | 住友电气工业株式会社 | Submount and semiconductor device |
| CN100435329C (en) * | 2003-06-23 | 2008-11-19 | 大动力公司 | Micro lead frame package and method to manufacture the micro lead frame package |
| CN101681897A (en) * | 2007-07-27 | 2010-03-24 | 飞兆半导体公司 | Dual side cooling integrated power device package and module and methods of manufacture |
| CN101553920B (en) * | 2006-10-31 | 2012-10-10 | 飞思卡尔半导体公司 | Methods and apparatus for a quad flat no-lead (QFN) package |
-
1996
- 1996-05-09 JP JP8114586A patent/JPH09326463A/en active Pending
-
1997
- 1997-05-03 TW TW086105897A patent/TW408407B/en not_active IP Right Cessation
- 1997-05-09 CN CNB971111677A patent/CN1135609C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100342510C (en) * | 2002-08-09 | 2007-10-10 | 住友电气工业株式会社 | Submount and semiconductor device |
| CN100435329C (en) * | 2003-06-23 | 2008-11-19 | 大动力公司 | Micro lead frame package and method to manufacture the micro lead frame package |
| CN101553920B (en) * | 2006-10-31 | 2012-10-10 | 飞思卡尔半导体公司 | Methods and apparatus for a quad flat no-lead (QFN) package |
| CN101681897A (en) * | 2007-07-27 | 2010-03-24 | 飞兆半导体公司 | Dual side cooling integrated power device package and module and methods of manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1135609C (en) | 2004-01-21 |
| JPH09326463A (en) | 1997-12-16 |
| TW408407B (en) | 2000-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1043828A (en) | The manufacture method of semiconductor device | |
| CN1204144A (en) | Method for making resin packaging semiconductor device | |
| CN1751390A (en) | Lead frame with included passive devices | |
| CN1290037A (en) | Semiconductor device | |
| JPH02201948A (en) | Package of semiconductor device | |
| CN1099131C (en) | Ball grid array semiconductor package | |
| CN1135609C (en) | Semiconductor device and method of its fabrication | |
| JPH10223819A (en) | Semiconductor device | |
| CN1092843C (en) | Package of semiconductor device with grooved intraconnection | |
| CN1234158C (en) | Manufacturing method of packaging base plate and its structure | |
| JP3424184B2 (en) | Resin-sealed semiconductor device | |
| CN1061174C (en) | Semiconductor packaging with transparent window and its producing method | |
| CN2684375Y (en) | Chip packaging structure | |
| CN1023675C (en) | Method for manufacture of semiconductor device | |
| KR100373891B1 (en) | Semiconductor device and method of its fabrication | |
| CN1119833C (en) | Packaged integrated circuit device | |
| KR100282414B1 (en) | bottom leaded-type VCA(Variable Chip-size Applicable) package | |
| US6324756B1 (en) | Method and system for sealing the edge of a PBGA package | |
| CN1181620A (en) | Method for wire bonding | |
| CN1198005A (en) | Semiconductor package and method of manufacturing the same | |
| JPS62296541A (en) | Plastic molded semiconductor device | |
| KR100251331B1 (en) | Lead frame and a semiconductor device using same | |
| CN2779610Y (en) | Lead shelf electric encapsulation substance | |
| KR0157890B1 (en) | Mounting structure of semiconductor package and method of mounting the same | |
| KR950000457Y1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: OKI SEMICONDUCTOR CO., LTD. Free format text: FORMER OWNER: OKI ELECTRIC INDUSTRY CO., LTD. Effective date: 20090508 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20090508 Address after: Tokyo, Japan, Japan Patentee after: OKI Semiconductor Co., Ltd. Address before: Tokyo port area, Japan Patentee before: Oki Electric Industry Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040121 Termination date: 20120509 |