TW408407B - Semiconductor device and method of its fabrication method - Google Patents

Semiconductor device and method of its fabrication method Download PDF

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Publication number
TW408407B
TW408407B TW086105897A TW86105897A TW408407B TW 408407 B TW408407 B TW 408407B TW 086105897 A TW086105897 A TW 086105897A TW 86105897 A TW86105897 A TW 86105897A TW 408407 B TW408407 B TW 408407B
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Taiwan
Prior art keywords
semiconductor component
guide pin
wafer holder
semiconductor
semiconductor device
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TW086105897A
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Chinese (zh)
Inventor
Nobuhito Oouchi
Hiroshi Kawano
Etsuo Yamada
Yasushi Shiraishi
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Oki Electric Ind Co Ltd
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Publication of TW408407B publication Critical patent/TW408407B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/787—Means for aligning
    • H01L2224/78703—Mechanical holding means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads (3) is disposed so as to extend over the surface of a semiconductor element (1). The chip support is bonded and fixed to the polyimide surface (9) of the semiconductor element (1) by means of an insulating tape. The leads (3) are brought into contact with the polyimide surface (9) of the semiconductor element (1) without being fixed. The leads (3) and the electrodes of the semiconductor element (1) are connected by means of gold wires (6), and these are packaged by a packaging material (7). Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.

Description

403407 1773PIF.D〇C/wliyW/005 A7 B7 經濟部中央標準局男工消費合作社印裝 五、發明説明（丨） 發明背景 本發明係關於半導體元件的結構，更仔細地說，係關於 一種塑膠封裝的半導體元件的結構及其製造方法。 近年來，由於晶片尺寸增大，塑膠封裝的半導體元件 中’封裝與半導體組件之間的間距也愈來愈小。這是因爲 雖然半導體組件變大了，包裝的封裝卻因爲標準化的緣故 無法增大。因此，爲了解決這種問題，人們開始採用諸如 日本6-105721號公告專利中所提出的晶片上導腳（Lead On Chip)結構。 具有這種晶片上導腳（Lead On Chip)結構的塑膠封裝 半導體元件中，導腳會透過絕緣帶接合到半導體組件的表 面，導腳表面塗佈金線電鍍層，半導體組件的電極上也形 成金球，再以金線將兩者連接起來，最後利用樹脂材料密 封起來。 但是，這種傳統的塑膠封裝半導體元件有一個主要的問 題，舉例來說，有時要黏著在板上而進行加熱時，樹脂材 料會產生皸裂，影響元件的功能。如果半導體元件保存在 空氣中，樹脂因爲吸收水氣而受潮，當黏著在板上時，這 些水氣會受熱而蒸發，汽化時所產生的力量就會引致皸 裂。絕緣帶特別容易吸收水氣，所以皸裂常常發生在絕緣 帶附近。此外，還有另外一個問題，既然包含了絕緣帶， 半導體元件的厚度就受到限制，無法縮小° 發明的簡要說明 先 聞 S 背 填 寫 本 裝 訂 本紙張尺度適用t國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央標隼局貝工消費合作社印製 4034G7 1773PIF.DOC/whyW/005 ΑΊ _____B7__ 五、發明説明（> ) 基於以上的問題，我們提出本發明。因此，本發明的目 的是提出一種可以避免皸裂、也可以製作得更薄的塑膠封 裝元件及其製造的方法。 本發明的特徵是晶片的支架位在導腳旁，只有晶片支架 附著在半導體組件上，導腳並不固定在半導體組件上，再 將半導體組件的電極和導腳連接起來。 有了這樣的設計，因爲導腳和半導體組件表面之間並沒 有特殊的材料，所以導腳與半導體組件組合之後的厚度就 可以縮小。整個元件的厚度也可以縮小。此外，因爲絕緣 帶只用在接合半導體組件和晶片支架，絕緣帶的面積可以 作得很小。因此可以避免絕緣帶所帶來的皸裂，提高元件 品質。 附圖的簡要說明 圖1的橫剖面圖說明，根據本發明安排導腳後，所得塑 膠封裝半導體元件的相關結構； 圖2的橫剖面圖說明，根據本發明第一實施例安排晶片 支架後，所得塑膠封裝半導體元件的相關結構； 圖3的上視圖說明，根據第一實施例製作過程中的塑膠 封裝半導體元件； 圖4的橫剖面圖說明，根據本發明第二實施例安排導腳 後，所得塑膠封裝半導體元件的相關結構； 圖5的橫剖面圖說明，根據本發明第二實施例安排晶片 支架後，所得塑膠封裝半導體元件的相關結構； I- - t i 11 ~~ 1 —訂 _111 (請先閲讀背&之注意^項再填寫本"> 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公嫠） 4G64G7 1773PIF.DOC/whyW/005 A/ B7 五、發明説明（今） 圖6的上視圖說明，根據第二實施例製作過程中的塑膠 封裝半導體元件； (請先聞讀沙 圓7的上視圖說明，根據第三實施例製作過程中的塑膠 封裝半導體元件； 圓β的媒却丨T5?圓ifVHH，i日植笛二苗fcfe/ratRCSirAfciV!拍日挪±_1 經濟部中央標嗥局員工消費合作社印製 408Ί07 1773PIF.DOC/whyW/005 A7 B7 五、發明説明（¥ ) 架）。圖3的上視圖則說明了根據第一實施例，製作塑膠封 裝半導體元件的過程。 在半導體組件1形成電路的表面上，先塗佈一層聚乙醯 胺的晶圓塗佈層9。承載這個半導體組件1的導線架12，厚 • v 約0.125公釐，包括導腳3和晶片支架10 β在晶片支架10與 半導體組件1之間會夾入一個絕緣帶2，厚約0.15公釐，藉 由這個絕緣帶2，晶片支架1〇和聚乙醯胺的晶圓塗佈層9會 接合固定在一起。晶片支架10位在半導體組件1側邊外的部 位（即圖2中標號11所代表的部位）會彎折，幅度約等於絕 緣帶2的厚度（約0,15公釐）。相對地，導腳3和聚乙醯胺 晶圓塗佈層9只是彼此接觸，並沒有固定在一起。晶片支架 10的底面10a (位在彎折部位Π之外）和聚乙醯胺晶圓塗佈 屏9的表面約在同一平面。從圖3·可以看出，按照這個方式 將半導體組件I安置在導線架12上的情形。 接著，導腳3的表面上的金線電鍍層（未畫出），和半 導體組件1上的金球5，會以金線6予以連接，再以樹脂材料 7密封起來，然後從導線架12上剪下導腳3和晶片支架10。 這時就完成了圖1和圖2所說明的塑膠封裝的半導體元件。 正如以上所述，在第一實施例的塑膠封裝半導體元件 中，導腳3和半導體組件1上的聚乙醯胺晶圓塗佈層9只是接 觸，並沒有任何材料夾在其間來加以固定。因此，導腳3與 半導體組件1組合之後的厚度可以縮小。整個元件的厚度也 可以縮小。半導體組件1只靠黏著在晶片支架10上的絕緣帶 2加以固定。這樣，絕緣帶2的面積可以很小，可以減少絕 <請先W讀背面之注$項再填寫本頁)403407 1773PIF.D0C / wliyW / 005 A7 B7 Printed by the Male Workers Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (丨) Background of the Invention The present invention relates to the structure of semiconductor components, more specifically, to a plastic Structure of packaged semiconductor element and manufacturing method thereof. In recent years, due to the increase in chip size, the space between the 'package' and the semiconductor component in plastic-encapsulated semiconductor components has become smaller and smaller. This is because although semiconductor components have become larger, the packaging package cannot be enlarged due to standardization. Therefore, in order to solve this problem, people have started to adopt a Lead On Chip structure such as that proposed in Japanese Patent Publication No. 6-105721. In a plastic-packaged semiconductor element having such a Lead On Chip structure, the lead pins are bonded to the surface of the semiconductor device through an insulating tape, the surface of the lead pins is coated with a gold wire plating layer, and the electrodes of the semiconductor device are also formed. Golden ball, then connect the two with gold wire, and finally sealed with resin material. However, this traditional plastic-packaged semiconductor device has a major problem. For example, when it is sometimes adhered to a board and heated, the resin material may crack and affect the function of the device. If the semiconductor device is stored in the air, the resin will be damp due to absorption of moisture. When adhered to the board, these moisture will be heated and evaporated, and the force generated during vaporization will cause cracking. Insulation tapes are particularly susceptible to moisture absorption, so cracking often occurs near the insulation tape. In addition, there is another problem. Since the thickness of the semiconductor element is limited due to the inclusion of an insulating tape, the brief description of the invention is firstly written on the back of this binding. The paper size is applicable to the national standard (CNS) A4 specification ( 210X297 mm) Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4034G7 1773PIF.DOC / whyW / 005 ΑΊ _____B7__ 5. Description of the invention (>) Based on the above problems, we propose the present invention. Therefore, an object of the present invention is to provide a plastic packaging element which can avoid cracking and can be made thinner, and a method for manufacturing the same. The feature of the invention is that the holder of the wafer is located beside the guide pin, only the wafer holder is attached to the semiconductor component, the guide pin is not fixed on the semiconductor component, and then the electrode and the guide leg of the semiconductor component are connected. With this design, because there is no special material between the guide pin and the surface of the semiconductor component, the thickness of the guide pin and the semiconductor component can be reduced. The thickness of the entire component can also be reduced. In addition, since the insulating tape is only used to join the semiconductor component and the wafer holder, the area of the insulating tape can be made small. Therefore, it is possible to avoid cracks caused by the insulating tape and improve component quality. Brief Description of the Drawings Fig. 1 is a cross-sectional view illustrating the related structure of the plastic-encapsulated semiconductor component obtained after the guide pins are arranged according to the present invention; Related structure of the obtained plastic-encapsulated semiconductor element; The top view of FIG. 3 illustrates the plastic-encapsulated semiconductor element during the manufacturing process according to the first embodiment; the cross-sectional view of FIG. 4 illustrates that after the guide pins are arranged according to the second embodiment of the present invention, Relevant structure of the obtained plastic-encapsulated semiconductor element; FIG. 5 is a cross-sectional view illustrating the related structure of the obtained plastic-encapsulated semiconductor element after arranging a chip holder according to the second embodiment of the present invention; I--ti 11 ~~ 1 —Order_111 (Please read the back & note ^ before filling in this " > This paper size applies to Chinese National Standard (CNS) Α4 specification (210X297) 嫠 4G64G7 1773PIF.DOC / whyW / 005 A / B7 V. Description of the invention (Today) The top view of FIG. 6 illustrates the plastic-encapsulated semiconductor component during the manufacturing process according to the second embodiment; (Please read the top view description of Sha Yuan 7 first, according to The third embodiment is a plastic packaged semiconductor component in the manufacturing process; the medium of the circle β is T5? The circle is ifVHH, i is planted in two flutes fcfe / ratRCSirAfciV! 408Ί07 1773PIF.DOC / whyW / 005 A7 B7 V. Description of the invention (¥) frame). The top view of FIG. 3 illustrates the process of making a plastic packaged semiconductor element according to the first embodiment. The surface of the circuit formed on the semiconductor component 1 First, a polyimide wafer coating layer 9 is applied. The lead frame 12 carrying this semiconductor component 1 has a thickness of about 0.125 mm and includes a guide pin 3 and a wafer support 10 β on the wafer support 10 and An insulating tape 2 is sandwiched between the semiconductor components 1 and has a thickness of about 0.15 mm. With this insulating tape 2, the wafer holder 10 and the wafer coating layer 9 of polyethylene are bonded and fixed together. The wafer holder The position of 10 bits outside the side of the semiconductor device 1 (ie, the part represented by reference numeral 11 in FIG. 2) is bent, and the width is approximately equal to the thickness of the insulating tape 2 (about 0,15 mm). In contrast, the guide pin 3 And the polyamide wafer coating layer 9 are only in contact with each other, They are not fixed together. The bottom surface 10a of the wafer holder 10 (located outside the bending portion Π) and the surface of the polyurethane wafer coating screen 9 are approximately on the same plane. As can be seen from FIG. 3, in this way, When the semiconductor device I is placed on the lead frame 12. Next, the gold wire plating layer (not shown) on the surface of the lead pin 3 and the gold ball 5 on the semiconductor device 1 are connected by the gold wire 6. Then, the resin material 7 is used for sealing, and then the lead pins 3 and the wafer holder 10 are cut from the lead frame 12. At this time, the plastic-encapsulated semiconductor element illustrated in FIGS. 1 and 2 is completed. As described above, in the plastic-encapsulated semiconductor element of the first embodiment, the guide pin 3 and the polyurethane wafer coating layer 9 on the semiconductor component 1 are only in contact with each other without any material sandwiched therebetween for fixing. Therefore, the thickness of the guide pin 3 after being combined with the semiconductor module 1 can be reduced. The thickness of the entire component can also be reduced. The semiconductor module 1 is fixed only by an insulating tape 2 adhered to the wafer holder 10. In this way, the area of the insulating tape 2 can be very small, which can reduce the absolute < please read the note on the back before filling this page)

X 本纸張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） A7 B7 408407 1773PIF.DOC/whyW/005 五、發明说明（Γ) 緣帶2所吸收的水氣，避免當黏著在板上時因加熱所產生的 皸裂，提高元件的品質。 第二實施例 圖4和圖5的橫剖面圖，說明根據本發明第二實施例所得 塑膠封裝半導體元件的相關結構。圖4說明了導腳的安排方 式，圖、5則說明的晶片支架的安排方式（圖中只畫出一個支 架）。圖6的上視圖則說明了根據第二實施例，製作塑膠封 裝半導體元件的過程。圖4至圖6中，與圖1至圖3相同的標 號代表相同或對應的構成部件。 在半導體組件1形成電路的表面上，先塗佈一層聚乙酿 胺的晶圓塗佈層9。承載這個半導體組件1的導線架12，包 括導腳3和^片支架10。導腳3和聚乙醯胺晶圓塗佈層9只是 彼此接觸，並沒有固定在一起。導腳3位在半導體組件1側 邊外的部位（即圖4中標號21所代表的部位）會往下彎折。 各導腳3的頂面3a (彎折部位21以外，但位在密封材料7以 內）和聚乙醯胺晶圓塗佈層9的表面約在同一平面。各晶u 支架10的頂面10b和聚乙醯胺晶圓塗佈層9的表面約在同 平面，而其尾端則離半導體組件1的側邊一個預定的距 (圖5)。此外，絕緣帶2會銜接聚乙醯胺晶圓塗佈層9的 面和晶片支架10的頂面，透過這層絕緣帶2使聚乙醯胺晶 塗佈層9與晶片支架10接合固定在一起。從圖6可以看出， 按照這個方式將半導體組件1安置在導線架12上的情形。 接著，導腳3的表面上的金線電鍍層（未畫出），和半 導體組件1上的金球5，會以金線6予以連接，再以樹脂材料 III I 裝 —-訂 1 I ^—1 1 線 - · {請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印繁 ftX This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 408407 1773PIF.DOC / whyW / 005 V. Description of the invention (Γ) Moisture absorbed by edge band 2 to avoid sticking to the board The cracks caused by the heating at the time of improving the quality of the component. Second Embodiment Figs. 4 and 5 are cross-sectional views illustrating a related structure of a plastic-packaged semiconductor device obtained according to a second embodiment of the present invention. Figure 4 illustrates the arrangement of the guide pins, and Figures 5 and 5 illustrate the arrangement of the wafer holder (only one bracket is shown in the figure). Fig. 6 is a top view illustrating a process of manufacturing a plastic packaged semiconductor device according to the second embodiment. In Figs. 4 to 6, the same reference numerals as those in Figs. 1 to 3 represent the same or corresponding components. On the surface of the semiconductor component 1 where the circuit is formed, a wafer coating layer 9 of polyethylene is first coated. The lead frame 12 carrying this semiconductor module 1 includes a guide pin 3 and a bracket 10. The guide pins 3 and the polyurethane wafer coating layer 9 are only in contact with each other and are not fixed together. The part of the guide pin 3 located outside the side of the semiconductor device 1 (ie, the part represented by reference numeral 21 in Fig. 4) is bent downward. The top surface 3a of each guide pin 3 (other than the bending portion 21, but located within the sealing material 7) and the surface of the polyimide wafer coating layer 9 are approximately on the same plane. The top surface 10b of each of the wafer holders 10 and the surface of the polyurethane wafer coating layer 9 are approximately in the same plane, and the trailing end thereof is a predetermined distance from the side of the semiconductor device 1 (Fig. 5). In addition, the insulating tape 2 will be connected to the surface of the polyurethane wafer coating layer 9 and the top surface of the wafer holder 10, and the polyethylene crystal coating layer 9 and the wafer holder 10 will be bonded and fixed through the insulating tape 2. together. It can be seen from FIG. 6 that the semiconductor module 1 is mounted on the lead frame 12 in this manner. Next, the gold wire plating layer (not shown) on the surface of the guide pin 3 and the gold ball 5 on the semiconductor component 1 will be connected with the gold wire 6, and then the resin material III I will be installed-order 1 I ^ —1 1 Line-· {Please read the notes on the back before filling out this page) Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1773PIF.DOC/whyWi A7 B7 經濟部中央標隼局負工消費合作社印繁 五、發明説明（‘〉 7密封起來，然後從導線架12上剪下導腳3和晶片支架10。 這時就完成了圖4和圖5所說明的塑膠封裝的半導體元件。 正如以上所述，在第二實施例的塑膠封裝半導體元件 中，導腳3和半導體組件1上的聚乙醯胺晶圓塗佈層9只是接 觸，並沒有任何材料夾在其間來加以固定。因此，導腳3與 半導體組件1組合之後的厚度可以縮小《*整個元件的厚度也 可以縮小。此外，半導體組件1只靠絕緣帶2使聚乙醯胺晶 圓塗佈層9與晶片支架1〇銜接起來而加以固定，絕緣帶的面 積可以很小，減少絕緣帶所吸收的水氣，避免當黏著在板 上時因加熱所產生的皸裂，所以能提高元件的品質。 第三實施例 圖7至圖9的橫剖面圖，說明根據本發明第三實施例所得 塑膠封裝半導體元件的相關結構。圖7是製作過程中之塑膠 封裝半導體元件的上視圖。圖8和圖9是相關結構的橫剖面 圖。圖8是循圖7中A-A’線剖開的橫剖面圖，圖9是循圖7中 B-B’線剖開的橫剖面圖。圖7至圖9中，與圖1至圖6相同的 標號代表相同或對應的構成部件。 在半導體組件1形成電路的表面上，先塗佈一層聚乙醯 胺的晶圓塗佈層9。再透過絕緣帶2使晶片支架10附著在這 層聚乙醯胺晶圓塗佈層9。晶片支架10與導腳3約在同一個 平面上。如圖8的說明，晶片支架10是以絕緣帶2接合到半 導體組件1的表面上。此外，如圖9，導腳3的表面上的金線 電鍍層和半導體組件1上的金球5 (未畫出），會以金線6予 以連接。導腳3並沒有接合到半導體組件1上，彼此相距一 9 本紙張尺度適用中國國家標率（CNS > A4規格（2丨OX”7公釐） ----------^------_訂 I-------.^ - 4 (請先Μ讀背面之注意事項再填寫本頁) A7 B7 408407 1773PIRDOC/whyW/005 五、發明説明（7) 個距離。也就是說，導腳3位在半導體組件1上方，相距一 個距離31，隨後這個距離31會塡滿密封的樹脂7。 這樣一來，導腳3下並沒有絕緣帶2，絕緣帶2只在晶片 支架10上》因此，絕緣帶2所用的份量就可以大幅地減少， 所吸收的水氣也很有限。此外，因爲晶片支架1〇和導腳3在 同一個平面，處理導線架12時，就可以省去彎折的步驟。 接下來，將透過圖10Α和圖10Β說明圖7至圖9之塑膠封 裝的半導體元件的製造方法。首先，將導線架上的晶片 支架10藉由絕緣帶2接合到半導體組件1上，然後再將半導 體組件1放在圖10Α中的加熱塊13中。這時導線架12內，導 ,腳3和晶片支架10約在同一個平面上，而導腳3在空氣中， 與半導體組件1相隔一個距離，正等於固定晶片支架10與半 導體組件1之絕緣帶2的厚度。 接下來照著圖10Β的說明，利用導腳3與加熱塊13的頂 面上方的一個導腳夾14，箝住導腳3與半導體組件1，使導 腳3與半導體組件1接觸。然後，導腳3上的金電鍍層4和半 導體組件1上的金球5就透過打線接合，以金線6連接起來。 這時，放開固定的導腳夾14，導腳3會回到圖1〇Α中的位 置，在這種狀態下（參照圖8和圖9)以樹脂材料7將半導體 組件1、導腳3 '金線6和晶片支架10都密封起來。照這樣製 作後，就可以得到一個塑膠封裝的半導體元件，其中只有 晶片支架10固定在半導體組件1上（參照圖7至圖9)，而且 也毋需彎折導腳3或晶片支架10。 第四實施例 -----------裝--------訂--.-----線 - - (请先閲请背面之注^Μη項再填寫本頁} 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家標率（CNS > A4規格（2!〇Χ297公釐） 經濟部中央標隼局貝工消費合作社印製 4084C7 1773PIF.DOC/whyW/005 A7 __B7 五、發明説明（ί) 圖π的橫剖面圖’說明根據本發明第四實施例所得塑膠 封裝半導體元件的相關結構。圖12則說明圖11之塑膠封裝 半導體元件的製造方法》圖11和圖12中，與圖1至圖10相 同的標號代表相同或對應的構成部件。 根據此第四實施例所製作的塑膠封裝半導體元件大抵與 上述第三實施例_\乍的塑膠封裝半導體元件相同，但有 下列的差別：也’圖11中所說明之塑膠封裝半導體 元f失虫的導腳3尾_^$遠離半導體組件1的表面彎折。因 此’當導腳夾14和力|^gl3在製造箝住導腳3與半導 體組件1時，導腳3的^不會與半件1上的聚乙醯胺 鬲圓塗佈層9直接接觸，而導腳3尾__|®面則會與聚乙醯 胺晶圓塗佈層9接觸。因此，就可避在半導體組件1 的表面上形成裂痕。 1S.» 第五實施例 圖13說明根據本發明第五實施例製造塑膠封裝半導體元 件的方法。圖13中，與圖1至圖12相同的標號代表相同或對 應的構成部件。我們假設根據這個第五實施例製造的塑膠 封裝半導體元件與根據上述第三實施例製造的塑膠封裝半 導體元件結構相同。 根據這個第五實施例製造這個塑膠封裝半導體元件的過 程中，導腳3的表面上的金線電鍍層4與半導體組件1上的金 球5連接時，利用了具有電磁鐵的導腳夾16 ’所以導腳3並 沒有接觸到半導體組件1的表面上。在圖13中’首先將透過 絕緣帶2附著了晶片支架10的半導體組件1放在加熱塊13 I— I 11 II —訂 I ^1 線 - 1 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標车（CNS) A4現格（2丨0X297公釐） 經濟部中央標準局貝工消費合作社印製 408407 1773PH7.DOC/whyW/005 A7 B7 五、發明説明（？） 裏。這時，導腳3位在空氣中，與半導體組件1相距一個距 離，等，於接合晶片支架10與半導體組件1的絕緣帶2的厚 度。 接下來，將具有電磁鐵的導腳夾16放在導腳3的頂面 上，並利用具有電磁鐵的導腳夾16的磁力使導腳3固定在導 腳夾16的底面上，然後在這樣的狀態下，以打線接合的方 式，使導腳3和半導體組件1上的金球5透過金線6接合起 來。照這種方式將金球5與導腳3連接起來，可以避免在半 導體組件1的表面上造成裂痕，導腳3也不致變形》 第五實施例中的製造方法，也可以用來製造上述第四個 實施例的塑膠封裝半導體元件》 第六實施例 圖14說明根據本發明第六實施例製造塑膠封裝半導體元 件的方法。圖14中，與圖1至圖13相同的標號代表相同或對 應的構成部件。我們假設根據這個第六實施例製造的塑膠 封裝半導體元件，與根據上述圖7至圖9的第三實施例製造 的塑膠封裝半導體元件結構相同。 根據這個第六實施例製造這個塑膠封裝半導體元件的過 程中，利用了具有電磁鐵的加熱塊17，使導腳3接觸到半導 體組件1的表面上。在圖14中，首先將透過絕緣帶2附著了 晶片支架10的半導體組件1放在加熱塊17裏。接著’具有電 磁鐵的加熱塊17開始運作，藉由這個磁力，將導腳3拉向半 導體組件1的表面，並與之接觸。然後在這樣的狀態下’以 打線接合的方式，使導腳3和半導體組件1上的金球5透過金 (請先Μ讀背面之注意事項再填寫本頁) -裝·This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 1773PIF.DOC / whyWi A7 B7 Printing and Production Cooperative of Consumers Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of invention ('> 7) The guide pins 3 and the wafer holder 10 are cut off from the frame 12. At this time, the plastic-encapsulated semiconductor device illustrated in Figs. 4 and 5 is completed. As described above, in the plastic-packaged semiconductor device of the second embodiment, the guide pins 3 is only in contact with the polyethylenimide wafer coating layer 9 on the semiconductor component 1 and there is no material sandwiched between them to fix it. Therefore, the thickness of the guide pin 3 after being combined with the semiconductor component 1 can be reduced by "* the entire component" The thickness of the semiconductor component 1 can also be reduced. In addition, the semiconductor component 1 can be fixed by connecting the polyurethane wafer coating layer 9 and the wafer holder 10 only by the insulating tape 2. The area of the insulating tape can be small, reducing the number of insulating tapes. Absorbed water vapor can avoid cracks caused by heating when sticking to the board, so the quality of the component can be improved. Third Embodiment FIG. 7 to FIG. 9 are cross-sectional views illustrating a third embodiment of the present invention. Relevant structure of the plastic-encapsulated semiconductor element obtained in the embodiment. Fig. 7 is a top view of the plastic-encapsulated semiconductor element in the manufacturing process. Figs. 8 and 9 are cross-sectional views of the relevant structure. Fig. 8 is taken along A-A 'in Fig. 7 9 is a cross-sectional view taken along the line BB ′ in FIG. 7. In FIGS. 7 to 9, the same reference numerals as those in FIGS. 1 to 6 represent the same or corresponding components. On the surface of the semiconductor component 1 where the circuit is formed, a layer of polyethylenimide wafer coating layer 9 is first coated. Then, the wafer holder 10 is adhered to this layer of polyimide wafer coating layer 9 through the insulating tape 2. The wafer holder 10 and the guide pin 3 are approximately on the same plane. As illustrated in FIG. 8, the wafer holder 10 is bonded to the surface of the semiconductor component 1 with an insulating tape 2. In addition, as shown in FIG. 9, the surface of the guide pin 3 is The gold wire plating layer and the gold ball 5 (not shown) on the semiconductor component 1 will be connected by the gold wire 6. The guide pins 3 are not bonded to the semiconductor component 1 and are separated from each other by 9 This paper size applies to China Standard rate (CNS > A4 specification (2 丨 OX "7mm) ---------- ^ ------_ Order I -------. ^- 4 (Please read the precautions on the back before filling this page) A7 B7 408407 1773PIRDOC / whyW / 005 V. Description of the invention (7) Distances. That is, the guide pins 3 are located above the semiconductor component 1 and are separated by a distance. 31, then the distance 31 will be filled with sealed resin 7. In this way, there is no insulating tape 2 under the guide pin 3, and the insulating tape 2 is only on the wafer holder 10. Therefore, the amount of the insulating tape 2 can be greatly Reduced, the absorbed moisture is also very limited. In addition, because the wafer holder 10 and the guide pin 3 are on the same plane, when the lead frame 12 is processed, the bending step can be omitted. Next, a method of manufacturing the plastic-encapsulated semiconductor element of FIGS. 7 to 9 will be described with reference to FIGS. 10A and 10B. First, the wafer holder 10 on the lead frame is bonded to the semiconductor module 1 through the insulating tape 2, and then the semiconductor module 1 is placed in the heating block 13 in Fig. 10A. At this time, in the lead frame 12, the guide pin 3 and the wafer holder 10 are on the same plane, and the guide pin 3 is in the air and separated from the semiconductor component 1 by a distance, which is equal to fixing the insulating tape of the wafer holder 10 and the semiconductor component 1. 2 thickness. Next, according to the description of FIG. 10B, the guide pin 3 and a guide clip 14 above the top surface of the heating block 13 are used to clamp the guide pin 3 and the semiconductor component 1 so that the guide pin 3 is in contact with the semiconductor component 1. Then, the gold plating layer 4 on the guide pin 3 and the gold ball 5 on the semiconductor component 1 are bonded by wire bonding, and are connected by the gold wire 6. At this time, the fixed guide clip 14 is released, and the guide pin 3 returns to the position shown in FIG. 10A. In this state (see FIGS. 8 and 9), the semiconductor component 1 and the guide pin 3 are made of a resin material 7. 'The gold wire 6 and the wafer holder 10 are sealed. After manufacturing in this manner, a plastic-encapsulated semiconductor element can be obtained, in which only the wafer holder 10 is fixed to the semiconductor module 1 (refer to FIGS. 7 to 9), and it is not necessary to bend the guide pins 3 or the wafer holder 10. The fourth embodiment ----------- install -------- order ----------- line--(please read the note ^ Mη item on the back before filling in this Page} The printed paper size of the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs applies to the national standard of China (CNS > A4 size (2 × 〇297 mm)) Printed by the Central Standards Bureau of the Ministry of Economy / whyW / 005 A7 __B7 V. Explanation of the invention (ί) A cross-sectional view of FIG. π illustrates the related structure of the plastic packaged semiconductor element obtained according to the fourth embodiment of the present invention. FIG. 12 illustrates the manufacturing of the plastic packaged semiconductor element of FIG. 11 Method> In FIGS. 11 and 12, the same reference numerals as those in FIGS. 1 to 10 represent the same or corresponding components. The plastic-encapsulated semiconductor device manufactured according to this fourth embodiment is almost the same as the third embodiment. The plastic packaged semiconductor components are the same, but with the following differences: Also, the plastic packaged semiconductor element f illustrated in FIG. 11 has 3 guide pins that are bent away from the surface of the semiconductor component 1. Therefore, when the guide pin clips 14 和 力 | ^ gl3 When manufacturing the clamp pin 3 and the semiconductor component 1, the ^ of the pin 3 will not It is in direct contact with the polyethylenimide round coating layer 9 on the half piece 1, and the __ | ® surface of the tail 3 of the guide pin is in contact with the polyethylenimide wafer coating layer 9. Therefore, it can be avoided A crack is formed on the surface of the semiconductor component 1. 1S. »Fifth Embodiment FIG. 13 illustrates a method for manufacturing a plastic-encapsulated semiconductor device according to a fifth embodiment of the present invention. In FIG. 13, the same reference numerals as those in FIGS. 1 to 12 represent the same or Corresponding constituent parts. We assume that the plastic-packaged semiconductor element manufactured according to this fifth embodiment has the same structure as the plastic-packaged semiconductor element manufactured according to the third embodiment described above. In the process of manufacturing this plastic-packaged semiconductor element according to this fifth embodiment When the gold wire plating layer 4 on the surface of the guide pin 3 is connected to the gold ball 5 on the semiconductor component 1, a guide pin clip 16 with an electromagnet is used, so the guide pin 3 does not contact the surface of the semiconductor component 1. In Figure 13, 'First place the semiconductor module 1 with the wafer holder 10 attached through the insulating tape 2 on the heating block 13 I—I 11 II—Order I ^ 1 Line-1 (Please read the precautions on the back before filling in this Page) Paper size is applicable to China National Standard Vehicle (CNS) A4 (2 丨 0X297 mm). Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 408407 1773PH7.DOC / whyW / 005 A7 B7 5. In the description of the invention (?). At this time, the guide pins 3 are located in the air, and a distance from the semiconductor component 1 is equal to the thickness of the insulating tape 2 joining the wafer holder 10 and the semiconductor component 1. Next, the guide pin clip 16 having the electromagnet is placed On the top surface of the guide pin 3, the guide pin 3 is fixed on the bottom surface of the guide pin clip 16 by the magnetic force of the guide pin clip 16 with an electromagnet. Then, in this state, the guide pin is connected by wire bonding. 3 and the gold ball 5 on the semiconductor component 1 are joined by a gold wire 6. By connecting the gold ball 5 and the guide pin 3 in this way, it is possible to avoid cracks on the surface of the semiconductor component 1 and the guide pin 3 is not deformed. The manufacturing method in the fifth embodiment can also be used to manufacture the first Four Embodiments of Plastic-Encapsulated Semiconductor Components> Sixth Embodiment FIG. 14 illustrates a method of manufacturing a plastic-packaged semiconductor component according to a sixth embodiment of the present invention. In Fig. 14, the same reference numerals as those in Figs. 1 to 13 represent the same or corresponding constituent parts. We assume that the plastic-packaged semiconductor element manufactured according to this sixth embodiment has the same structure as the plastic-packaged semiconductor element manufactured according to the third embodiment of Figs. 7 to 9 described above. In the process of manufacturing the plastic-encapsulated semiconductor element according to this sixth embodiment, a heating block 17 having an electromagnet is used to bring the guide pin 3 into contact with the surface of the semiconductor module 1. In FIG. 14, first, a semiconductor module 1 to which a wafer holder 10 is attached through an insulating tape 2 is placed in a heating block 17. Then, the heating block 17 having the electromagnet starts to operate, and by this magnetic force, the guide pin 3 is pulled toward the surface of the semiconductor component 1 and comes into contact with it. Then in this state, the wire 3 on the guide pin 3 and the semiconductor component 1 will pass through gold by wire bonding (please read the precautions on the back before filling in this page).

'-1T 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 40G407 A7 1773PIF.DOC/whyW/005 A/ B7 五、發明説明（厂） 線6接合起來。照這種方式將金球5與導腳3連接起來，毋需 用到導腳夾就能使導腳3固定得很好。 第六實施例中的製造方法，也可以用來製造上述圖11第 四個實施例的塑膠封裝半導體元件β 誠如以上的說明，根據本發明的半導體元件及其製造方 法，整個半導體元件可以製作得更薄。此外，接合的絕緣 帶所帶來的皸裂可以避免，品質也得以提高。 裝 訂 線 -- (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 本紙乐尺度適用中國國家標準（CNS ) Α4現格（2Ι0Χ297公釐）'-1T line This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 40G407 A7 1773PIF.DOC / whyW / 005 A / B7 V. Description of the invention (factory) Line 6 is joined together. In this way, the golden ball 5 is connected to the guide pin 3, and the guide pin 3 can be fixed well without using a guide pin clamp. The manufacturing method in the sixth embodiment can also be used to manufacture the plastic-packaged semiconductor element β in the fourth embodiment of FIG. 11 As described above, according to the semiconductor element and the manufacturing method of the present invention, the entire semiconductor element can be manufactured. Thinner. In addition, cracks caused by the bonded insulating tape can be avoided and the quality can be improved. Binding Line-(Please read the notes on the back before filling this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs This paper scale is applicable to the Chinese National Standard (CNS) A4 (2Ι0 × 297 mm)

Claims (1)

經濟部中央標牟局員工消費合作社印装 4084G7 A$ 1773PIF.D〇C/whyW/005 B8 OS D8 六、申請專利範圍 1.一種半導體元件，係包含： 一個半導體組件，其表面上具有電極； 數個導腳，與該電極相連： 一個晶片支架，延伸至該半導體組件表面；以及 一個絕緣帶，位在該晶片支架與半導體組件之間，用以將 該晶片支架黏著在半導體組件上。 2·根據申請專利範圍第1項的半導體元件，其中該晶片支架 位在半導體組件一個側邊外圍的部位朝半導體組件彎折， 其幅度約等於該絕緣帶的厚度。 3. —種半導體元件，係包含： 一個半導體組件，其表面上具有電極； 數個導腳，與該電極相連； 一個晶片支架，其頂面位在該半導體組件一個側邊之外， 約與該半導體元件的表面等平面；以及 一個絕緣帶，用來銜接該晶片支架與半導體組件，使該晶 片支架黏著在半導體組件上，其中 該導腳爲在該半導體組件側邊之外的部位係朝半導體組件 彎折。 4. 根據申請專利範圍第I項的半導體元件，其中該導腳和電 極是以打線接合連接的。 5. 種半導體元件，係包含： 一個半導體組件，其表面上具有電極； 數個導腳，位在該半導體組件表面上，並相距一個距離； 一個晶片支架，黏著在該半導體組件的表面；以及數個引 ___ 14 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------裝------^訂一^-----線 * (請先閲讀背面之注意事項再填寫本頁〕 經濟部t央標準扃員工消費合作社印製 408407 A8 1773PIF.DOC/whyW/005 B8 C8 D8 六、申請專利範圍 線，連接該電極與導腳。 6. —種半導體元件的製造方法，其步驟係包含： 預備一個半導體元件，一個表面上具有電極，並具有一個 導線架，其內包含約等平面的晶片支架和導腳； 將該晶片支架黏著在該半導體組件的表面上，並使該導腳 位在該半導體組件表面上，並相距一個距離；並且 使該導腳與該半導體組件的表面接觸，使導腳與該電極連 接。 7. 根據申請專利範圍第6項的方法，其中該導腳的尾端係朝 上彎折，遠離該半導體組件的表面。 8. 根據申請專利範圍第6項的方法，其中該連接導腳與電極 的步驟係包括利用一個位在該半導體組件底面的加熱塊， 和一個位在該導腳頂面上的導腳夾，將該半導體組件和導 腳箝住，使該導腳與該半導體組件接觸。 9. 根據申請專利範圍第6項的方法，其中該連接導腳與電極 的步驟係包括利用一個位在該半導體組件底面、含有電磁 鐵的加熱塊，使該導腳與該半導體組件接觸。 10. —種半導體元件的製造方法，其步驟係包含： 預備一個半導體元件，一個表面上具有電極，並具有一個 導線架，其內包含約等平面的晶片支架和導腳； 將該晶片支架黏著在該半導體組件的表面上，並使該導腳 位在該半導體組件表面上，並相距一個距離；並且 在該導腳頂面上加上一個含有電磁鐵的導腳夾，使導腳與 該電極連接。 15 ---------裝-------訂丨------線 • b (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4洗格（210X297公釐）Printed by the Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4084G7 A $ 1773PIF.D0C / whyW / 005 B8 OS D8 VI. Application for a patent 1. A semiconductor component, comprising: a semiconductor component with electrodes on its surface; A plurality of guide pins are connected to the electrode: a wafer holder extending to the surface of the semiconductor component; and an insulating tape located between the wafer holder and the semiconductor component to adhere the wafer holder to the semiconductor component. 2. The semiconductor device according to item 1 of the scope of the patent application, wherein the wafer holder is bent toward the semiconductor device at a position on the periphery of one side of the semiconductor device, and the width is approximately equal to the thickness of the insulating tape. 3. A semiconductor component comprising: a semiconductor component having an electrode on the surface; a plurality of guide pins connected to the electrode; a wafer holder whose top surface is located outside one side of the semiconductor component, about The surface of the semiconductor element is equiplanar; and an insulating tape is used to connect the wafer holder and the semiconductor component, so that the wafer holder is adhered to the semiconductor component, wherein the guide pin is facing away from the side of the semiconductor component. The semiconductor component is bent. 4. The semiconductor device according to item I of the application, wherein the lead and the electrode are connected by wire bonding. 5. A semiconductor device comprising: a semiconductor device having electrodes on a surface thereof; a plurality of guide pins positioned on the surface of the semiconductor device at a distance; a wafer holder adhered to the surface of the semiconductor device; and Several quotes ___ 14 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) --------- installation -------- ^ order one ^ ----- line * (Please read the precautions on the back before filling in this page.) Printed by 408407 A8 1773PIF.DOC / whyW / 005 B8 C8 D8 by the Central Standard of the Ministry of Economics and Employee Consumer Cooperatives 6. Apply for a patent line, connect this electrode with the guide pin. 6. A method for manufacturing a semiconductor device, the steps of which include: preparing a semiconductor device with an electrode on a surface and a lead frame containing a wafer holder and a guide pin of approximately equal plane; and adhering the wafer holder On the surface of the semiconductor component, the guide pin is positioned on the surface of the semiconductor component and spaced apart from each other; and the guide pin is in contact with the surface of the semiconductor component, so that the guide pin is connected to the electrode. The method according to item 6 of the patent application, wherein the tail end of the guide pin is bent upward and away from the surface of the semiconductor component. 8. The method according to item 6 of the patent application, wherein the connection between the guide pin and the electrode The steps include using a heating block located on the bottom surface of the semiconductor component and a guide clip on the top surface of the guide pin to clamp the semiconductor component and the guide pin so that the guide pin is in contact with the semiconductor component. 9. The method according to item 6 of the scope of patent application, wherein the step of connecting the guide pin and the electrode comprises using a heating block located on the bottom surface of the semiconductor component and containing an electromagnet to contact the guide pin with the semiconductor component. A method for manufacturing a semiconductor device, the steps of which include: preparing a semiconductor device with an electrode on a surface and a lead frame, which includes a wafer holder and a guide leg of about an equal plane; and the wafer holder is adhered to On the surface of the semiconductor component, with the guide pin on the surface of the semiconductor component, and at a distance from each other; and adding a A guide pin clip with an electromagnet is used to connect the guide pin to the electrode. 15 --------- Install --------- Order 丨 ------ Wire • b (Please read the back first Please fill in this page for the matters needing attention.) This paper size adopts Chinese National Standard (CNS) A4 (210X297mm)
TW086105897A 1996-05-09 1997-05-03 Semiconductor device and method of its fabrication method TW408407B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8114586A JPH09326463A (en) 1996-05-09 1996-05-09 Resin-sealed semiconductor device

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TW408407B true TW408407B (en) 2000-10-11

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Publication number Priority date Publication date Assignee Title
JP3882712B2 (en) * 2002-08-09 2007-02-21 住友電気工業株式会社 Submount and semiconductor device
US7253506B2 (en) * 2003-06-23 2007-08-07 Power-One, Inc. Micro lead frame package
US7663211B2 (en) * 2006-05-19 2010-02-16 Fairchild Semiconductor Corporation Dual side cooling integrated power device package and module with a clip attached to a leadframe in the package and the module and methods of manufacture
US7489026B2 (en) * 2006-10-31 2009-02-10 Freescale Semiconductor, Inc. Methods and apparatus for a Quad Flat No-Lead (QFN) package

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CN1166053A (en) 1997-11-26
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