200816419 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種使用導線架之晶片封裝構 造’特別係有關於一種多晶片模流平衡之封裝構造。 【先前技術】 按，在習知晶片封裝構造中用以承載晶片的元件稱 之為晶片載體，例如導線架、印刷電路板、陶瓷基板 或電路薄膜。其中使用導線架具有低成本與高抗濕性 的優點。然而在目前導線架基底的晶片封裝構造中， 儘可能希望多種不同厚度規格的晶片種類能共用同一 型式的導線架、封膠模具與封裝製程，然晶片的厚度 =化會影響封裝品質，可能引起嚴重翹曲與模流不平 衡的問題。尤其是選用無晶片承座的導線架，晶片是 直接貼附在導線架之單側或兩側引腳i，晶片更容易 受到模流不平衡的影響而位移、傾斜與填膠不密實引200816419 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure using a lead frame, which is particularly related to a package structure of a multi-wafer mold flow balance. [Prior Art] The component for carrying a wafer in a conventional wafer package construction is referred to as a wafer carrier such as a lead frame, a printed circuit board, a ceramic substrate or a circuit film. The use of the lead frame has the advantages of low cost and high moisture resistance. However, in the current wafer package structure of the lead frame substrate, it is desirable to have a plurality of different thickness specifications of the wafer type to share the same type of lead frame, sealing mold and packaging process, but the thickness of the wafer will affect the package quality, which may cause The problem of severe warpage and mold flow imbalance. In particular, the lead frame of the waferless holder is used, and the wafer is directly attached to the one side or the side of the lead frame i, and the wafer is more susceptible to the imbalance of the mold flow, and the displacement, the inclination and the filling are not dense.
其係鄰近於該些 ’一種習知晶片封裝構造1〇〇主要包含 個第一侧引腳H0與複數個第二側引腳 晶片130、複數個銲線140以及一封膠體 3弟一側引腳110係較長於該些第二側引腳 :對稱之長度。該積體電路晶片130係利用 160以黏接其背面於該第一側引腳11〇，且 1之主動面131係具有複數個銲墊132， 兩侧引腳110、120之内端111、121，另， 200816419 可藉由該些銲線140以電性連接該些銲墊132至該些兩侧引 腳110、120之内端111、121。該封膠體150係密封該些兩 側引腳110、120之内端111、121、該積體電路晶片13〇以 及該些銲線140。由於該積體電路晶片130依客戶提供來源 不同會有不同厚度，當該積體電路晶片130過於薄化時，該 封膠體150之底面152至該積體電路晶片13〇之距離（以供 下模流之形成）明顯大於該封膠體150之頂面15ι至該些第 一侧引腳110間之距離（以供上模流之形成）。因此，在該封 膠體150之形成過程，在導線架下方的下模流速度會大於在 ¥線架上方的上模流速度，如第2圖所示，下模流邊界1 5 4 不但超過上模流邊界153填滿導線架的下方，更會往上包覆 到導線架的上方，所造成的模流不平衡會導致該封膠體15〇 會有氣泡或縫隙的產生。此外，模流不平衡亦會產生上下注 膠壓力的不相等，被該些第一側引腳110固定之積體電 路曰曰片130易有偏斜位移甚至有引腳内端U1外露的 問題。再者，如第3圖所示，該封裝構造1〇〇之積體 電路晶片130越薄則抗翹曲能力越弱旅且在導線架 上下的注膠量有著不相等的差異，熟化該封膠體15〇 的固化收縮率會造成該封裝構造1〇〇之嚴重翹曲。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提 供一種多晶片模流平衡之封裝構造，利用虛晶片與積 體電路Μ片之黏貼可避免導線架之上下模流不平衡所 引起之晶片偏斜位移與封膠體内氣泡產生之問題，特 6 200816419 別適用於非對稱導線架之長側引腳黏晶作業。此外， 可以加強積體電路晶片之抗翹曲強度，以減少封裝構 造之龜曲度。 本發明之次一目的係在於提供一種多晶片模流平 衡之封裝構造，能加強非對稱導線架之長侧引腳之黏 晶支撐力。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種多晶片模流平衡之 封裝構造主要包含一導線架之複數個第一側引腳與複 數個第二侧引腳、一虛晶片、一積體電路晶片、複數 個銲線以及一封膠體。其中該些第一側引腳係較長於 該些第二侧引腳。該虛晶片係黏設於該些第一側引 腳。該積體電路晶片係具有一主動面與一背面，該背 面係黏没於該虛晶片，該主動面其中^一側邊形成有複 數個銲墊，其係鄰近該些第一侧引腳與該些第二侧引 腳之内端。該些銲線係電性連接該些銲墊至該些第一 側引腳與該些第二側引腳^該封膠體係密封該虛晶 片、該積體電路晶片、該些銲線以及該些第一側引腳 與該些第二侧引腳之一部位。在不同實施例中，該虛 晶片係可依照該積體電路晶片調整其尺寸大小’另可 應用於其它使用導線架之封裝構造，例如薄蜇小外形 封裴（TSOP)，一積體電路晶片係黏設於該些引腳上’ 而一虛晶片黏設於該積體電路晶片之背面。 本發明的目的及解決其技術問題還可採用以下技 7 200816419 術措施進一步實現。 在前述的封裝構造中，另包含一導線架之兩侧晶片承 座’該些第-侧引腳係排列在該兩側晶片承座之間，而該虛 晶片更黏設於該兩側晶片承座。 在前述的封裝構造中，另包含複數個黏晶膠帶，以黏 接該些第一侧引腳與該虛晶片。 在前述的封裝構造中，該封膠體係具有一頂面與一底 面，該頂面距離該些第一侧引腳之高度約略等於該底面距離 ® 該積體電路晶片之高度。 在所述的封裝構造中，該些銲墊係集中在該主動面之 單一側邊，其係為一字形單排排列或平行排交錯排列。 在前述的封裝構造中，該虛晶片之尺寸係不小於該積 體電路晶片。 【實施方式】 在本發明之第一具體實施例中，配合參閱第4至6 • 圖揭示一種多晶片模流平衡之封裝構造。 如第4圖所示，一種多晶片模流平衡之封裝構造 2 0 0主要包含一導線架之複數個第一側引腳2〗〇與複 數個第二側引腳220、一虛晶片23〇、一積體電路晶片 240、複數個銲線250以及一封膠體26〇。如第5圖所 示’該導線架之引腳長度係為非對稱，該些第一側引 腳2 1 0係較長於該些第二側引腳2 2 〇。 如第4及6圖所示，該虛晶片230係黏設於該些第 一側引腳210。該虛晶片230係為一種不具有電性傳 8 200816419 遞功能的半導體基板，即不設有積體電路之主動元 件’但其尺寸大小則與一般積體電路晶片相近。在本 實施例中，該虛晶片230之尺寸係不小於該積體電路 晶片240。該虛晶片230之厚度可以大於、小於或等 於該積體電路晶片240之厚度。在本實施例中，是利 用複數個黏晶膠帶2 8 0黏接該些第一側引腳2 1 0與該 虛晶片230。其中，該些第一黏晶膠帶280係為細長 條狀。 # 該積體電路晶片240係具有一主動面24 1與一背面 2 42，在該主動面241係製作有各式積體電路元件，如 記憶體、微處理器、微控制器或邏輯元件等等，該主 動面241其中一側邊形成有複數個銲墊243。該積體 電路晶片 240之背面242係黏設於該虛晶片230，並 使該些銲墊243係鄰近該些第一側引腳210之内端211 與該些第二側引腳220之内端221。在本實施例中， ^ 該些銲墊243係集中在該主動面241之單一側邊，其 係為一字形單排排列或平行排交錯排列。利用打線形 成之該些銲線250電性連接該些銲墊243至該些第一 側引腳2 1 0之内端2 1 1與電性連接至該些第二側引腳 220之内端221。 再如第4圖所示，該封膠體260係密封該虛晶片 230、該積體電路晶片240、該些銲線250以及該些第 一侧引腳2 1 0與該些第二側引腳220之一部位。該封 膠體260係具有一頂面261與一底面262，並以轉移 200816419 模注的方式形成。因此，藉 稽由該虛晶片230之設置， 該封膠體260之項面261距離 雖该些弟一側引腳2 1 0之 高度約略等於該封膠體26〇 低面262距離該積體電 路晶片2 4 〇主動面2 4 1之古疮 Ah, 阿又’敗*達到導線架上下的 模流平衡，如第7圖所 ^ ^ 相叙於第2圖，形成該封 膠體26G之㈣中，在該些第—則腳21G上方之上 ㈣邊界263與在該些第1引腳川下方之下模流 邊界264兩者注膠流動速度接近，達到上下模流之較 佳理想化。故能避免晶片偏斜位移甚至有引腳内端外 露之問題’同時防止封膠體内氣泡產生。 匕卜如第6圖所示，在某一程度上，該虛晶片 230可以視為—種半導體材質之晶片承座，可以加強 該積體電路曰曰# 24〇之抗翹曲強度。並且，該虛晶片 〇八該積體電路晶片240之間為零或微弱的内應 力，配合該虛晶片230黏貼在複數個第一側引腳210, 有政降，低了該封農構造200之翹曲度（如第8圖所示）。 如第5及6圖所示，較佳地，該封裝構造2〇〇可另 包3導線架之兩側晶片承座270，該些第一側引腳 21 〇係排列在該兩侧晶片承座270之間。除了黏附在 該些第一侧引腳2 1 〇，該虛晶片23 〇更黏設於該兩側 晶片承座270，加強非對稱導線架之長侧引腳之黏晶 支撐力，防止該積體電路晶片24〇受到形成該封膠體 2 60之注膠壓力影響而造成傾斜或位移。 如第9圖所示，本發明之第二實施例另揭示/多晶片損 10 200816419It is adjacent to the 'a conventional chip package structure 1 〇〇 mainly comprising a first side pin H0 and a plurality of second side pin wafers 130, a plurality of bonding wires 140 and a colloid 3 side The foot 110 is longer than the second side pins: symmetrical length. The integrated circuit chip 130 is used to bond the back surface of the first side lead 11 利用, and the active surface 131 of the first surface has a plurality of pads 132, and the inner ends 111 of the two sides of the pins 110 and 120. 121, in addition, 200816419, the solder pads 132 can be electrically connected to the inner ends 111, 121 of the two side pins 110, 120 by the bonding wires 140. The encapsulant 150 seals the inner ends 111, 121 of the two side pins 110, 120, the integrated circuit wafer 13 and the bonding wires 140. Since the integrated circuit chip 130 has different thickness depending on the source provided by the customer, when the integrated circuit wafer 130 is too thin, the bottom surface 152 of the sealing body 150 is at a distance from the integrated circuit chip 13 (for the next The formation of the mold flow is significantly larger than the distance between the top surface 15 of the encapsulant 150 and the first side pins 110 (for the formation of the upper mold flow). Therefore, in the formation process of the sealant 150, the lower mold flow velocity under the lead frame is greater than the upper mold flow velocity above the wire frame. As shown in Fig. 2, the lower die flow boundary 1 5 4 is not only higher than The mold flow boundary 153 fills the lower side of the lead frame and is evenly wrapped over the lead frame. The resulting mold flow imbalance causes bubbles or gaps in the sealant 15 to be generated. In addition, the mold imbalance is also caused by the unequal pressure of the upper and lower injection pressures, and the integrated circuit chip 130 fixed by the first side pins 110 is prone to skew displacement or even the exposed inner end U1. . Furthermore, as shown in FIG. 3, the thinner the integrated circuit wafer 130 of the package structure is, the weaker the warpage resistance is, and the difference in the amount of glue injected above and below the lead frame is unequal, and the seal is cured. The cure shrinkage of the colloid 15 会 causes a severe warpage of the package structure. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a multi-wafer mold flow balancing package structure, which can avoid the imbalance of the upper mold flow on the lead frame by using the dummy wafer and the integrated circuit chip. The problem caused by the skew displacement of the wafer and the generation of bubbles in the sealant is not applicable to the long side pin bonding operation of the asymmetric lead frame. In addition, the warpage resistance of the integrated circuit wafer can be enhanced to reduce the tortuosity of the package structure. A second object of the present invention is to provide a package structure for multi-wafer mold flow balancing that enhances the adhesion of the long side pins of the asymmetric lead frame. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-wafer mold flow balanced package structure mainly includes a plurality of first side pins and a plurality of second side pins of a lead frame, a dummy chip, an integrated circuit chip, a plurality of bonding wires, and A gel. The first side pins are longer than the second side pins. The dummy chip is attached to the first side pins. The integrated circuit chip has an active surface and a back surface, and the back surface is adhered to the dummy wafer. The active surface has a plurality of pads formed on one side thereof adjacent to the first side pins. The inner ends of the second side pins. The bonding wires are electrically connected to the first side pins and the second side pins. The sealing system seals the dummy wafer, the integrated circuit wafer, the bonding wires, and the Some of the first side pins and one of the second side pins. In various embodiments, the virtual wafer can be sized according to the integrated circuit wafer. 'Other applicable to other package configurations using a lead frame, such as a thin outline package (TSOP), an integrated circuit chip. Attached to the pins' and a dummy wafer is attached to the back of the integrated circuit chip. The object of the present invention and solving the technical problems thereof can be further realized by the following techniques. In the above package structure, the wafer holders on both sides of the lead frame are further disposed between the two side wafer holders, and the dummy wafer is further adhered to the two sides of the wafer. Seat. In the foregoing package structure, a plurality of adhesive tapes are additionally included to bond the first side pins and the dummy wafer. In the foregoing package construction, the encapsulation system has a top surface and a bottom surface, the height of the top surface from the first side pins being approximately equal to the height of the bottom surface of the integrated circuit chip. In the package construction, the pads are concentrated on one side of the active surface, which are arranged in a single row or in parallel rows. In the aforementioned package configuration, the size of the dummy wafer is not less than that of the integrated circuit wafer. [Embodiment] In a first embodiment of the present invention, reference is made to Figs. 4 to 6 to disclose a package structure of a multi-wafer mold flow balance. As shown in FIG. 4, a multi-chip mode-balanced package structure 200 mainly includes a plurality of first side pins 2 and a plurality of second side pins 220 and a dummy chip 23 of a lead frame. An integrated circuit wafer 240, a plurality of bonding wires 250, and a colloid 26 〇. As shown in Fig. 5, the lead length of the lead frame is asymmetrical, and the first side pins 2 10 0 are longer than the second side pins 2 2 〇. As shown in Figures 4 and 6, the dummy wafer 230 is adhered to the first side pins 210. The virtual wafer 230 is a semiconductor substrate that does not have the function of electrical transmission, that is, an active device that does not have an integrated circuit, but has a size similar to that of a general integrated circuit chip. In the present embodiment, the dummy wafer 230 is not smaller than the integrated circuit wafer 240. The thickness of the dummy wafer 230 can be greater than, less than, or equal to the thickness of the integrated circuit wafer 240. In this embodiment, the first side pins 2 10 and the dummy wafer 230 are bonded by a plurality of die bonding tapes 280. The first adhesive tapes 280 are elongated and strip-shaped. # The integrated circuit wafer 240 has an active surface 24 1 and a back surface 2 . 42 . The active surface 241 is formed with various integrated circuit components such as a memory, a microprocessor, a microcontroller or a logic component. And the active surface 241 is formed with a plurality of pads 243 on one side thereof. The back surface 242 of the integrated circuit chip 240 is adhered to the dummy chip 230, and the pads 243 are adjacent to the inner end 211 of the first side pins 210 and the second side pins 220. End 221. In this embodiment, the pads 243 are concentrated on a single side of the active surface 241, which are arranged in a single row or in a parallel row. The bonding wires 250 formed by the bonding wires are electrically connected to the inner pads 2 1 1 of the first side pins 2 1 0 and the inner ends of the second side pins 220 electrically connected to the first side pins 2 1 0 221. As shown in FIG. 4, the encapsulant 260 seals the dummy wafer 230, the integrated circuit wafer 240, the bonding wires 250, and the first side pins 2 1 0 and the second side pins. One part of 220. The sealant 260 has a top surface 261 and a bottom surface 262 and is formed by transferring 200816419. Therefore, by the arrangement of the dummy wafer 230, the height of the face 261 of the encapsulant 260 is approximately equal to the height of the lower side of the encapsulant 26 from the lower side of the encapsulant 26 to the integrated circuit chip. 2 4 〇 active surface 2 4 1 of the ancient sore Ah, A and 'failed* to achieve the mold flow balance above and below the lead frame, as shown in Fig. 7 ^ ^ in the second picture, forming the sealant 26G (four), It is preferable to achieve a flow rate of injection of the upper and lower mold streams at the upper (four) boundary 263 above the first leg 21G and the mold flow boundary 264 below the first pin. Therefore, it is possible to avoid the skew displacement of the wafer or even the problem of the exposed end of the pin, while preventing the generation of bubbles in the sealant. As shown in Fig. 6, to some extent, the dummy wafer 230 can be regarded as a wafer holder of a semiconductor material, which can enhance the warpage resistance of the integrated circuit. Moreover, the virtual wafer has zero or weak internal stress between the integrated circuit wafers 240, and the dummy wafer 230 is adhered to the plurality of first side pins 210, which has a political drop and lowers the agricultural structure 200. Warpage (as shown in Figure 8). As shown in FIGS. 5 and 6, the package structure 2 is preferably provided with two wafer holders 270 on both sides of the lead frame. The first side pins 21 are arranged on the two sides of the wafer carrier. Between 270. In addition to being adhered to the first side pins 2 1 〇, the dummy wafer 23 is further adhered to the two side wafer holders 270, and the adhesion support force of the long side pins of the asymmetric lead frame is strengthened to prevent the product. The bulk circuit chip 24 is subjected to tilting or displacement due to the injection pressure of the sealant 2 60. As shown in FIG. 9, the second embodiment of the present invention further discloses/multi-wafer loss 10 200816419
流平衡之封裝構造，主要元件係與第—實施例相同。該封 裝構造主要包含-導線架之複數個第-側引腳210與 複數個第二側引腳22G、—虛晶片23ga、—積體電路 晶^ 24〇A、複數個銲線250以及一封膠體26〇，重覆 圖5虎之70件不再重複贅述。其中該虛晶片23〇a之厚度係可 依該積體電路晶片240A之厚度變化作調整，當該積體電路 晶片240A是較薄的晶片，則選用較厚的虛晶片23〇a，藉以 使得該封膠體260之該頂面261距離該些第一側引腳21〇 之咼度約略等於該底面2 62距離該積體電路晶片A 之焉度’以達到導線架上下模流平衡。 在本發明之第三具體實施例中，揭示另一種封裝類 型之多晶片模流平衡之封裝構造。如第1 〇圖所示，一 種封裝構造300係為薄型小外形封裝（TS〇p)類型，其 係主要包含一導線架之複數個引腳31〇、一積體電路 晶片3 2 0、一虛晶片3 3 0、複數個銲線340以及一封膠 體 350。 該積體電路晶片320係具有一主動面321與一背面 322，該主動面321上係形成有複數個銲塾323。在本 實施例中，該些銲墊323係集中在該主動面321之一 中央區域，其係為單排排列或多排排列。可藉由複數 個黏晶膠帶360黏設該主動面321至該些引腳310之 下方，並使該些銲墊323鄰近該些引腳310之内端 31卜並以該些銲線340係電性連接該些銲塾323至該 些引腳310之内端311。 11 200816419 此外，該虛晶片3 3 0係黏設於該積體電路晶 之該背面322，藉此增強該積體電路晶片320 曲強度與促進該封膠體350在該些引腳310上 平衡。在本實施例中，該虛晶片3 3 〇之尺寸應 該積體電路晶片320。該封膠體350係密封該 3 30、該積體電路晶片320、該些銲線340以及 腳310之一部位。該封膠體350係具有一頂面 一底面3 5 2，該頂面3 5 1距離該些引腳3 1 0之 # 略等於該底面3 5 2距離該虛晶片3 3 0之高度， 架上下的模流平衡可以避免晶片偏斜位移甚至 310内端311外露之問題並可同時防止封膠體 氣泡產生。 以上所述，僅是本發明的較佳實施例而已， 本發明作任何形式上的限制，雖然本發明已以 施例揭露如上，然而並非用以限定本發明，任 本項技術者，在不脫離本發明之技術範圍内， 任何簡單修改、等效性變化與修飾，均仍屬於 的技術範圍内。 【圖式簡單說明】 第1圖：習知晶片封裝構造之截面示意圖。 第2圖：繪示習知晶片封裝構造在一封膠體形成 導線架上下模流不平衡之頂面示意圖 第3圖：繪示習知晶片封裝構造在一封膠體形 中，因上下膠體體積差異造成之封裝 片320 之抗翹 下模流 不小於 虛晶片 該些引 351與 高度約 故導線 有引腳 3 50内 並非對 較佳實 何熟悉 所作的 本發明 過程中 〇 成過程 體翹曲 12 200816419 示意圖。 第4圖：依據本發明之第一具體實施例，一種多晶片模 流平衡之封裝構造之截面示意圖。 第5圖：依據本發明之第一具體實施例，該封裝構造之 封膠區域内導線架之示意圖。 第6圖：依據本發明之第一具體實施例，該封裝構造之 另一截面示意圖。 第7圖：依據本發明之第一具體實施例，繪示該晶片 # 封裝構造在一封膠體形成過程中導線架上下 模流平衡之頂面示意圖。 第8圖：依據本發明之第一具體實施例，繪示該晶片 封裝構造在一封膠體形成過程中，因上下膠體 平衡，造成翹曲程度降低之頂面與側面示意 圖。 第9圖：依據本發明之第二具體實施例，另一種多晶 片模流平衡之封裝構造之截面示意圖。 第1 0圖··依據本發明之第三具體實施例，另一種多晶 片模流平衡之封裝構造之截面示意圖。 【主要元件符號說明】 100晶片封裝構造 1Γ0 第一側引腳 111内端 120 第二側引腳 121内端 130積體電路晶片 131主動面 132 銲墊 13 200816419The flow-balanced package structure has the same main components as the first embodiment. The package structure mainly comprises a plurality of first-side pins 210 and a plurality of second side pins 22G of the lead frame, a dummy chip 23ga, an integrated circuit crystal 24A, a plurality of bonding wires 250, and a The colloid is 26〇, and the repeated 70 pieces of the tiger in Figure 5 are not repeated. The thickness of the dummy wafer 23〇a can be adjusted according to the thickness variation of the integrated circuit wafer 240A. When the integrated circuit wafer 240A is a thinner wafer, a thicker dummy wafer 23〇a is selected, thereby The top surface 261 of the encapsulant 260 is approximately equal to the width of the bottom surface 2 62 from the bottom surface of the integrated circuit chip A to achieve the upper and lower mold flow balance of the lead frame. In a third embodiment of the invention, another package type multi-wafer mold flow balanced package construction is disclosed. As shown in FIG. 1 , a package structure 300 is a thin small outline package (TS〇p) type, which mainly includes a plurality of pins 31 of a lead frame, and an integrated circuit chip 3 2 0, one. A dummy wafer 333, a plurality of bonding wires 340, and a colloid 350. The integrated circuit chip 320 has an active surface 321 and a back surface 322. The active surface 321 is formed with a plurality of solder pads 323. In the present embodiment, the pads 323 are concentrated in a central region of the active surface 321 in a single row or in a plurality of rows. The active surface 321 can be adhered to the underside of the pins 310 by a plurality of adhesive tapes 360, and the pads 323 are adjacent to the inner ends 31 of the pins 310 and are connected by the bonding wires 340. The solder pads 323 are electrically connected to the inner ends 311 of the pins 310. 1110416419 In addition, the dummy chip 303 is adhered to the back surface 322 of the integrated circuit crystal, thereby enhancing the flexural strength of the integrated circuit wafer 320 and promoting the balance of the encapsulant 350 on the pins 310. In the present embodiment, the size of the dummy wafer 3 3 is the integrated circuit chip 320. The encapsulant 350 seals the portion of the integrated circuit wafer 320, the bonding wires 340, and the legs 310. The sealing body 350 has a top surface and a bottom surface 325, and the top surface 315 is a distance from the pins 3 1 0 which is slightly equal to the height of the bottom surface 3 5 2 from the virtual wafer 3 3 0. The mold flow balance can avoid the problem of wafer skew displacement and even 310 inner end 311 exposure and can prevent the formation of sealant bubbles. The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above. However, the present invention has been disclosed by way of example, but is not intended to limit the present invention. Within the technical scope of the present invention, any simple modifications, equivalent changes and modifications are still within the technical scope. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional chip package structure. Figure 2: Schematic diagram showing the top surface of the conventional chip package structure in the upper and lower mold flow imbalance of a lead-formed lead frame. Figure 3: The conventional chip package structure is shown in a colloidal shape due to the difference in volume between the upper and lower colloids. The resulting anti-warping mode flow of the encapsulating sheet 320 is not less than that of the dummy wafer. The lead 351 and the height of the lead wire have pins 3 50. The method of the invention is not warped. 200816419 Schematic. Figure 4 is a cross-sectional view showing a package structure of a multi-wafer mold flow balance in accordance with a first embodiment of the present invention. Figure 5 is a schematic illustration of a leadframe in the encapsulation region of the package construction in accordance with a first embodiment of the present invention. Figure 6 is another cross-sectional view of the package construction in accordance with a first embodiment of the present invention. Figure 7 is a top plan view showing the upper and lower mold flow balance of the lead frame in the formation process of the wafer # package structure according to the first embodiment of the present invention. Fig. 8 is a schematic view showing the top surface and the side surface of the wafer package structure in which the degree of warpage is reduced due to the balance of the upper and lower colloids in the process of forming a gel in accordance with the first embodiment of the present invention. Figure 9 is a cross-sectional view showing another package structure of a multi-plate mold flow balance in accordance with a second embodiment of the present invention. Fig. 10 is a schematic cross-sectional view showing another package structure of a multi-plate mold flow balance according to a third embodiment of the present invention. [Main component symbol description] 100 chip package structure 1Γ0 first side pin 111 inner end 120 second side pin 121 inner end 130 integrated circuit chip 131 active surface 132 solder pad 13 200816419
140銲線 1 5 0封膠體 1 5 1頂面 1 5 3上模流邊界 1 5 4下模流邊界 160黏晶膠帶 2 00多晶片模流平衡之封裝構造 210 第一侧引腳 21 1内端 220 第二側引腳 221 内端 230虛晶片 230A虛晶片 240積體電路晶片 240A積體電路晶片 242 背面 243 銲墊 2 5 0銲線 260封膠體 261 頂面 263上模流邊界 264下模流邊界 270兩側晶片承座 3 00多晶片模流平衡之封裝構造 310 引腳 311 内端 320積體電路晶片 3 22背面 323銲墊 330虛晶片 340銲線 3 5 0封膠體 3 5 1 頂面 360黏晶膠帶 1 5 2底面 241 主動面 262底面 280黏晶膠帶 321 主動面 352底面 14140 bond wire 1 50 sealant 1 5 1 top surface 1 5 3 upper mold flow boundary 1 5 4 lower mold flow boundary 160 adhesive crystal tape 2 00 multi-chip mold flow balance package structure 210 first side pin 21 1 End 220 Second Side Pin 221 Inner End 230 Virtual Wafer 230A Virtual Wafer 240 Integrated Circuit Wafer 240A Integrated Circuit Wafer 242 Back Side 243 Pad 2 5 0 Bond Wire 260 Sealant 261 Top Surface 263 Upper Mold Flow Boundary 264 Lower Die Flow Boundary 270 Both Sides of Wafer Bearings 300 00 Multi-chip Mold Flow Balanced Package Construction 310 Pin 311 Inner End 320 Integrated Circuit Wafer 3 22 Back 323 Pad 330 Virtual Wafer 340 Bonding Wire 3 5 0 Sealing Body 3 5 1 Top Face 360 adhesive tape 1 5 2 bottom surface 241 active surface 262 bottom surface 280 adhesive tape 321 active surface 352 bottom surface 14