TWI325619B - Multi-chip package to optimize mold-flow balance - Google Patents

Multi-chip package to optimize mold-flow balance Download PDF

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Publication number
TWI325619B
TWI325619B TW95135648A TW95135648A TWI325619B TW I325619 B TWI325619 B TW I325619B TW 95135648 A TW95135648 A TW 95135648A TW 95135648 A TW95135648 A TW 95135648A TW I325619 B TWI325619 B TW I325619B
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TW
Taiwan
Prior art keywords
wafer
chip
pins
integrated circuit
package structure
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TW95135648A
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Chinese (zh)
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TW200816419A (en
Inventor
Wen Jeng Fan
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Powertech Technology Inc
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Priority to TW95135648A priority Critical patent/TWI325619B/en
Publication of TW200816419A publication Critical patent/TW200816419A/en
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Publication of TWI325619B publication Critical patent/TWI325619B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Disclosed is a multi-chip package to optimize mold-flow balance, which mainly includes a plurality of leads of a leadframe having asymmetric length at two sides, a dummy chip, an IC chip, a plurality of bonding wires, and a molding compound. The dummy chip is attached to some of the leads having longer length at one side. Backside of the IC chip is adhered to the dummy chip. Formed on one of sides of the active surface of the IC chip are a plurality of bonding pads, which are adjacent the inner portions of the leads after chip attachment. The molding compound encapsulates the dummy chip, the IC chip, the bonding wires, and parts of the leads. The interposition of the dummy chip between the long-side lead and the IC chip will avoid mold-flow unbalance to cause the displacement or incline of the IC chip and lessen package warpage. Furthermore, the package can be adapted for various package fashions, TSOP for example.

Description

1325619 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種使用導線架之晶片封裝構 造，特別係有關於一種多晶片模流平衡之封裝構造。 【先前技術】 按，在習知晶片封裝構造中用以承載晶片的元件稱 之為晶片載體，例如導線架、印刷電路板、陶究基板 或電路薄膜。其中使用導線架具有低成本與高抗濕性 的優點。然而在目前導線架基底的晶片封裝構造中， 儘可能希望多種不同厚度規格的晶片種類能共用同— 型式的導線架、封膠模具與封裝製程，然晶片的厚度 變化會影響封裝品質’可能引起嚴重鍾曲與模流不平 衡的問題。尤其是選用無晶片承座的導線架，晶片是 直接貼附在導線架之單側或兩側引聊上，晶片更容易 受到模流不平衡的影響而位移、傾斜與填謬不密實弓丨 起氣泡或縫隙。 如第1圖所示，一種習知晶片封裝構造100主要包含 一導線架之複數個第一側引腳1 i 0與複數個第二側引腳 120、一積體電路晶片130、複數個銲線14〇以及一封膠體 150。其中’該些第一側引腳11〇係較長於該些第二側引腳 120,而呈兩側不對稱之長度。該積體電路晶片13〇係利用 複數個黏晶膠帶160以黏接其背面於該第一側引腳u〇，且 該積體電路晶片130之主動面131係具有複數個銲墊132， 其係鄰近於該些兩側引腳110、12〇之内端ιη、121，另， 1325619 可藉由該些銲線140以電性連接該些銲墊132至該些兩側引 腳110、120之内端111、121。該封膠體i 5〇係密封該些兩 側引腳UH20之内端1U、121、該積體電路晶片^^以 及該些銲線140。由於該積體電路晶片13〇依客戶提供來源 不同會有不同厚度，當該積體電路晶片13〇過於薄化時該 封膠體15〇之底面152至該積體電路晶片13〇之距離（以= 下模流之形成）明顯大於該封膠體15〇之頂面151至該些第 一側引腳110間之距離（以供上模流之形成）。因此在該封 膠體150之形成過程’在導線架下方的下模流速度會大於在 導線架上方的上模流速度，如第2圖所示，下模流邊界154 不但超過上模流邊界153填滿導線架的下方，更會往上包覆 到導線架的上方，所造成的模流不平衡會導致該封膠體15〇 會有氣泡或縫隙的產生。此外，模流不平衡亦會產生上下注 膠壓力的不相等，被該些第一側引腳110固定之積體電 B曰片130易有偏斜位移甚至有引腳内端in外露的 1題再者，如第3圖所示，該封裝構造1〇〇之積體 電路晶片13 〇越薄則抗翹曲能力越弱，並且在導線架 上下的注膠量有著不相等的差異，熟化該封膠體15〇 的固化收縮率會造成該封裝構造100之嚴重翹曲。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提 供一種多晶片模流平衡之封裝構造，利用虛晶片與積 體電路晶片之黏貼可避免導線架之上下模流不平衡所 起之B曰片偏斜位移與封膠體内氣泡產生之問題，特 6 1325619 別適用於非對稱導線架之長側引腳黏晶作業。此外， 可以加強積體電路晶片之抗翹曲強度，以減少封裝構 造之想曲度。 本發明之次一目的係在於提供一種多晶片模流平 衡之封裝構造，能加強非對稱導線架之長側引腳之黏 晶支撐力。 本發明的目的及解決其技術問題是採用以下技術 方案來實現的。依據本發明，一種多晶片模流平衡之 封裝構造主要包含一導線架之複數個第一側引腳與複 數個第二側引腳、一虛晶片、一積體電路晶片、複數 個銲線以及一封膠體。其中該些第一側引腳係較長於 該些第二側引腳。該虛晶片係黏設於該些第一側引 腳。該積體電路晶片係具有一主動面與一背面，該背 面係黏設於該虛晶片，該主動面其中一側邊形成有複 數個銲墊，其係鄰近該些第一側引腳與該些第二側引 腳之内端。該些銲線係電性連接該些銲墊至該些第一 側引腳與該些第二側引腳。該封膠體係密封該虛晶 片、該積體電路晶片、該些銲線以及該些第一側引腳 與該些第二侧引腳之一部位。在不同實施例中，該虛 晶片係可依照該積體電路晶片調整其尺寸大小，另可 應用於其它使用導線架之封裝構造，例如薄型小外形 封裴（TSOP)，一積體電路晶片係黏設於該些引腳上， 而一虛晶片黏設於該積體電路晶片之背面。 本發明的目的及解決其技術問題還可採用以下技 7 1325(519 t • 術措施進一步實現。 在前述的封裝構造中，另包含一導線架之兩側晶片承 座’ §玄些第一側引腳係排列在該兩侧晶片承座之間，而該虛 晶片更黏設於該兩側晶片承座。 在刖述的封裝構造中，另包含複數個黏晶膠帶，以黏 ^ 接該些第一側引腳與該虛晶片。 - 在前述的封裝構造中，該封膠體係具有一頂面與一底 面，該頂面距離該些第一側引腳之高度約略等於該底面距離 鲁 該積體電路晶片之高度。 在前述的封裝構造中，該些銲墊係集中在該主動面之 單一側邊，其係為一字形單排排列或平行排交錯排列。 在則述的封裝構造中，該虛晶片之尺寸係不小於該積 體電路晶片。 【實施方式】 在本發明之第一具體實施例中，配合參閱第4至6 • 圖揭示一種多晶片模流平衡之封裝構造。 如第4圖所示，一種多晶片模流平衡之封裝構造 - 200主要包含一導線架之複數個第一側引腳210與複 . 數個第二側引腳220、一虛晶片230、一積體電路晶片 240、複數個銲線250以及一封膠體26〇。如第5圖所 示，該導線架之引腳長度係為非對稱，該些第一側弓丨 腳2 1 0係較長於該些第二側引腳2 2 〇。 如第4及6圖所示’該虛晶片230係黏設於該些第 一側引腳2 1 0。該虛晶片2 3 0係為—種不具有電性傳 8 1325619 • 遞功能的半導體基板，即不設有積體電路之主動元 件，但其尺寸大小則與一般積體電路晶片相近。在本 實施例中，該虛晶片2 3 0之尺寸係不小於該積體電路 晶片240。該虛晶片230之厚度可以大於、小於或等 於該積體電路晶片240之厚度。在本實施例中，是利 - 用複數個黏晶膠帶2 8 0黏接該些第一側引腳2 1 0與該 . 虛晶片230。其中，該些第一黏晶膠帶280係為細長 條狀。 # 該積體電路晶片240係具有一主動面241與一背面 242，在該主動面241係製作有各式積體電路元件，如 記憶體、微處理器、微控制器或邏輯元件等等，該主 動面241其中一側邊形成有複數個銲墊243。該積體 電路晶片240之背面242係黏設於該虛晶片230，並 使該些銲墊2 4 3係鄰近該些第一側引腳2 1 0之内端2 1 1 與該些第二側引腳220之内端22 1。在本實施例中， 該些銲墊243係集中在該主動面241之單一側邊，其 ® 係為一字形單排排列或平行排交錯排列。利用打線形 . 成之該些銲線250電性連接該些銲墊243至該些第一 側引腳2 1 0之内端2 1 1與電性連接至該些第二側引腳 220之内端221。 再如第 4圖所示，該封膠體260係密封該虛晶片 230、該積體電路晶片240、該些銲線250以及該些第 一側引腳2 1 0與該些第二側引腳220之一部位。該封 膠體260係具有一頂面261與一底面262，並以轉移 9 1325619 模注的方式形成。因此，藉由該虛晶片2 3 0之設置 該封膠體260之頂面261距離該些第一側引腳210 高度約略等於該封膠體260之底面262距離該積體 路晶片240主動面241之高度，能達到導線架上下 模流平衡，如第7圖所示，相較於第2圖，形成該 膠體260之過程中，在該些第一侧引腳210上方之 模流邊界2 6 3與在該些第一側引腳2 1 0下方之下模 邊界2 6 4兩者注膠流動速度接近，達到上下模流之 佳理想化。故能避免晶片偏斜位移甚至有引腳内端 露之問題，同時防止封膠體内氣泡產生。 此外，如第 6圖所示，在某一程度上，該虛晶 230可以視為一種半導體材質之晶片承座，可以加 該積體電路晶片240之抗勉曲強度。並且5該虛晶 230與該積體電路晶片 240之間為零或微弱的内 力，配合該虛晶片2 3 0黏貼在複數個第一側引腳2 1 有效降低了該封裝構造200之翹曲度（如第8圖所示 如第5及6圖所示，較佳地，該封裝構造200可 包含一導線架之兩側晶片承座 2 7 0，該些第一側引 2 1 0係排列在該兩侧晶片承座2 7 0之間。除了黏附 該些第一側引腳2 1 0，該虛晶片2 3 0更黏設於該兩 晶片承座 270，加強非對稱導線架之長側引腳之黏 支撐力，防止該積體電路晶片240受到形成該封膠 260之注膠壓力影響而造成傾斜或位移。 如第9圖所示，本發明之第二實施例另揭示一多晶片 之 電 的 封 上 流 較 外 片 強 片 應 )， )° 另 腳 在 側 晶 體 模 10 1325619 . 流平衡之封裝構造，主要元件係與第一實施例相同。該封 裝構造主要包含一導線架之複數個第一側引腳21〇與 複數個第二側f丨腳220、一虛晶片23〇A、一積體電路 晶片240A、複數個銲線25〇以及一封膠體26〇，重覆 圖號之元件不再重複贅述。其中該虛晶片23〇A之厚度係可 ' 依該積體電路晶片240A之厚度變化作調整，當該積體電路 晶片240A是較薄的晶片，則選用較厚的虛晶片23〇A，藉以 使付該封膠體260之該頂面261距離該些第一側引腳21〇 鲁 之高度約略等於該底面262距離該積體電路晶片24〇A 之高度，以達到導線架上下模流平衡。 在本發明之第三具體實施例中，揭示另一種封裝類 型之多晶片模流平衡之封裝構造。如第1〇圖所示，一 種封裝構造300係為薄型小外形封裝（TSOP)類型，其 係主要包含一導線架之複數個引腳310、一積體電路 晶片320、一虛晶片3 3 0、複數個銲線34〇以及一封膠 體 350 » 該積體電路明片320係具有_主動面321與一背面 322’該主動面321上係形成有複數個銲墊323。在本 實施例中，該些銲墊323係集中在該主動面321之一 中央區域’其係為單排排列或多排排列。可藉由複數 個黏晶膠帶360黏設該主動面321至該些引腳310之 下方，並伏該些銲塾323鄰近該些引腳310之内端 311。並以該些b線340係電性連接該些銲塾323至該 些引腳31〇之内端311。 11 1325619 此外，該虛晶片33 0係黏設於該積體電路晶片320 之該背面322，藉此增強該積體電路晶片320之抗翹 曲強度與促進該封膠體350在該些引腳310上下模流 平衡。在本實施例中，該虛晶片3 3 0之尺寸應不小於 該積體電路晶片320«該封膠體350係密封該虛晶片 33 0、該積體電路晶片320、該些銲線340以及該些引 腳310之一部位。該封膠體350係具有一頂面351與 一底面352，該頂面351距離該些引腳310之高度約 略等於該底面352距離該虛晶片330之高度，故導線 架上下的模流平衡可以避免晶片偏斜位移甚至有引腳 310内端311外露之問題並可同時防止封膠體350内 氣泡產生。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 施例揭露如上，然而並非用以限定本發明，任何熟悉 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 的技術範圍内。 【圖式簡單說明】 第1圖··習知晶片封裝構造之戴面示意圖》 第2圖：繪示習知晶片封裝構造在一封膠體形成過程中 導線架上下模流不平衡之頂面示意圖。 第3圖·繪不習知晶片封裝構造在一封膠體形成過程 中，因上下膠體體積差異造成之封裝體翹曲 12 1325619 • 示意圖。 第4圖：依據本發明之第一具體實施例，一種多晶片模 流平衡之封裝構造之截面示意圖。 第5圖：依據本發明之第一具體實施例，該封裝構造之 封膠區域内導線架之示意圖。 ^ 第6圖：依據本發明之第一具體實施例，該封裝構造之 . 另一截面示意圖。 第7圖：依據本發明之第一具體實施例，繪示該晶片 # 封裝構造在一封膠體形成過程中導線架上下 模流平衡之頂面示意圖β 第8圖：依據本發明之第一具體實施例，繪示該晶片 封裝構造在一封膠體形成過程中，因上下膠體 平衡，造成麵曲程度降低之頂面與側面示意 圖。 第9圖：依據本發明之第二具體實施例，另一種多晶 | 片模流平衡之封裝構造之截面示意圖。 第1 0圖：依據本發明之第三具體實施例，另一種多晶 .. 片模流平衡之封裝構造之截面示意圖。 【主要元件符號說明】 100晶片封裝構造 110 第一側引腳 111内端 120 第二側引腳 121内端 130積體電路晶片 131主動面 1 32銲墊 13 1325619 1 4 0銲線 150封膠體 151頂面 1 5 3上模流邊界 1 5 4下模流邊界 160黏晶膠帶 200多晶片模流平衡之封裝構造 2 1 0 第一側引腳 2 1 1 内端 220 第二側引腳 221内端 2 3 0虛晶片 230Α虛晶片 240積體電路晶片 240Α積體電路晶片 242 背面 243 銲墊 2 5 0銲線 260封膠體 261頂面 263上模流邊界 264下模流邊界 270 兩側晶片承座 3 00多晶片模流平衡之封裝構造 310 引腳 311 内端 320積體電路晶片 3 2 2 背面 3 23銲墊 3 3 0 虛晶片 3 4 0銲線 350 封膠體 351 頂面 3 6 0黏晶膠帶 1 5 2底面 241 主動面 2 6 2底面 280黏晶膠帶 321 主動面 3 52底面 141325619 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer package structure using a lead frame, and more particularly to a package structure for multi-wafer mold flow balancing. [Prior Art] The component for carrying a wafer in a conventional wafer package construction is referred to as a wafer carrier such as a lead frame, a printed circuit board, a ceramic substrate or a circuit film. The use of the lead frame has the advantages of low cost and high moisture resistance. However, in the current wafer package structure of the lead frame substrate, it is desirable to have a plurality of different thickness specifications of the wafer type to share the same type of lead frame, sealing mold and packaging process, but the thickness variation of the wafer may affect the package quality 'may cause Serious clock and mold imbalance problems. In particular, the lead frame of the wafer-free socket is selected, and the wafer is directly attached to the one side or the two sides of the lead frame, and the wafer is more susceptible to the imbalance of the mold flow, and the displacement, inclination and filling are not dense. Bubbles or gaps. As shown in FIG. 1 , a conventional chip package structure 100 mainly includes a plurality of first side pins 1 i 0 and a plurality of second side pins 120 of a lead frame, an integrated circuit chip 130, and a plurality of solders. Line 14 and a gel 150. The first side pins 11 are longer than the second side pins 120 and have a length that is asymmetric on both sides. The integrated circuit chip 13 is formed by bonding a plurality of die bonding tapes 160 to the back side of the first side pin u, and the active surface 131 of the integrated circuit chip 130 has a plurality of pads 132. The inner ends i1 and 121 of the two side pins 110 and 12 are adjacent to the two sides of the pins 110 and 12, and the 1323519 is electrically connected to the pads 132 to the two side pins 110 and 120 by the bonding wires 140. The inner ends 111, 121. The encapsulant i 5 is used to seal the inner ends 1U, 121 of the two side pins UH20, the integrated circuit wafer, and the bonding wires 140. Since the integrated circuit chip 13 has different thickness depending on the source provided by the customer, when the integrated circuit chip 13 is too thinned, the bottom surface 152 of the sealing body 15 is at a distance from the integrated circuit chip 13 = formation of the lower mold flow) is significantly larger than the distance between the top surface 151 of the sealant 15 至 to the first side pins 110 (for the formation of the upper mold flow). Therefore, in the formation process of the encapsulant 150, the lower mold flow velocity under the lead frame is greater than the upper mold flow velocity above the lead frame. As shown in Fig. 2, the lower mold flow boundary 154 not only exceeds the upper mold flow boundary 153. Filling the underside of the lead frame will cover the top of the lead frame, and the resulting imbalance of the mold flow will cause bubbles or gaps in the sealant 15 . In addition, the mold imbalance is also caused by the unequal pressure of the upper and lower injection pressures, and the integrated electric B-plate 130 fixed by the first side pins 110 is easy to have a skew displacement or even the inner end of the lead is exposed. Further, as shown in FIG. 3, the thinner the integrated circuit chip 13 of the package structure, the weaker the warpage resistance, and the unequal difference in the amount of glue injected above and below the lead frame is ripened. The cure shrinkage of the encapsulant 15 turns causes severe warpage of the package construction 100. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a multi-wafer mold flow balancing package structure, which utilizes the adhesion of a dummy wafer and an integrated circuit chip to avoid the imbalance of the lower mold flow above the lead frame. The B-plate deflection displacement and the problem of bubble generation in the sealant, special 6 1325619 is not suitable for the long-side pin bonding operation of the asymmetric lead frame. In addition, the warpage resistance of the integrated circuit chip can be enhanced to reduce the degree of wrestling of the package structure. A second object of the present invention is to provide a package structure for multi-wafer mold flow balancing that enhances the adhesion of the long side pins of the asymmetric lead frame. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-wafer mold flow balanced package structure mainly includes a plurality of first side pins and a plurality of second side pins of a lead frame, a dummy chip, an integrated circuit chip, a plurality of bonding wires, and A gel. The first side pins are longer than the second side pins. The dummy chip is attached to the first side pins. The integrated circuit chip has an active surface and a back surface, and the back surface is adhered to the dummy wafer. One side of the active surface is formed with a plurality of pads adjacent to the first side pins and the The inner ends of the second side pins. The bonding wires are electrically connected to the pads to the first side pins and the second side pins. The encapsulation system seals the dummy wafer, the integrated circuit wafer, the bonding wires, and one of the first side pins and the second side pins. In various embodiments, the virtual chip can be sized according to the integrated circuit chip, and can be applied to other package structures using a lead frame, such as a thin small outline package (TSOP), an integrated circuit chip system. The electrodes are adhered to the pins, and a dummy wafer is attached to the back of the integrated circuit chip. The object of the present invention and solving the technical problems thereof can also be further implemented by the following technique: 513 t. In the foregoing package structure, another wafer holder on both sides of the lead frame is included. The pin is arranged between the two side wafer holders, and the dummy wafer is further adhered to the two side wafer holders. In the package structure described above, a plurality of adhesive crystal tapes are further included to adhere the The first side pin and the dummy chip. - In the foregoing package structure, the encapsulation system has a top surface and a bottom surface, the height of the top surface from the first side pins is approximately equal to the bottom surface distance The height of the integrated circuit chip. In the above package structure, the pads are concentrated on a single side of the active surface, which are arranged in a single-line arrangement or a parallel arrangement in parallel. The size of the virtual wafer is not less than that of the integrated circuit wafer. [Embodiment] In the first embodiment of the present invention, a package structure of multi-wafer mold flow balance is disclosed with reference to FIGS. 4 to 6 . As shown in Figure 4, A multi-wafer mold-flow balanced package structure-200 mainly includes a plurality of first side pins 210 and a plurality of second side pins 220, a dummy wafer 230, an integrated circuit wafer 240, and a plurality of lead frames a bonding wire 250 and a glue body 26〇. As shown in FIG. 5, the lead length of the lead frame is asymmetrical, and the first side arches 2 1 0 are longer than the second side leads. The foot 2 2 〇. As shown in Figures 4 and 6, the virtual wafer 230 is adhered to the first side pins 2 1 0. The virtual wafer 2 3 0 is a type that does not have electrical transmission 8 1325619 • A functional semiconductor substrate, that is, an active component that does not have an integrated circuit, but whose size is similar to that of a general integrated circuit wafer. In this embodiment, the size of the dummy wafer 230 is not less than the product. The thickness of the dummy wafer 230 can be greater than, less than, or equal to the thickness of the integrated circuit wafer 240. In this embodiment, the first is bonded to the first plurality of adhesive tapes. The side pins 2 1 0 and the virtual wafer 230. The first adhesive tapes 280 are elongated strips. The body circuit chip 240 has an active surface 241 and a back surface 242, and the active surface 241 is formed with various integrated circuit components such as a memory, a microprocessor, a microcontroller or a logic component, etc., the active surface A plurality of pads 243 are formed on one side of the 241. The back surface 242 of the integrated circuit wafer 240 is adhered to the dummy wafer 230, and the pads 2 4 3 are adjacent to the first side pins 2 The inner end 2 1 1 of the first side and the inner end 22 1 of the second side lead 220. In the embodiment, the solder pads 243 are concentrated on a single side of the active surface 241, and the A line is arranged in a single row or in a parallel row. The wire bonding wires 245 are electrically connected to the inner pads 2 1 1 of the first side pins 2 1 0 and electrically connected to the second side pins 220. Inner end 221. As shown in FIG. 4, the encapsulant 260 seals the dummy wafer 230, the integrated circuit wafer 240, the bonding wires 250, and the first side pins 2 1 0 and the second side pins. One part of 220. The encapsulant 260 has a top surface 261 and a bottom surface 262 and is formed by molding 9 1325619. Therefore, the top surface 261 of the encapsulant 260 is disposed such that the height of the first side pins 210 is approximately equal to the bottom surface 262 of the encapsulant 260 from the active surface 241 of the integrated circuit wafer 240. The height can reach the upper and lower mold flow balance of the lead frame. As shown in Fig. 7, compared with Fig. 2, during the formation of the colloid 260, the mold flow boundary above the first side pins 210 is 6 3 3 The injection flow velocity is close to the lower mold boundary 2 6 4 below the first side pin 2 1 0, and the ideal upper and lower mold flow is idealized. Therefore, it is possible to avoid the skew displacement of the wafer or even the problem of the inner end of the pin, and to prevent the generation of bubbles in the seal body. Further, as shown in Fig. 6, to some extent, the dummy crystal 230 can be regarded as a wafer holder of a semiconductor material, and the flexural strength of the integrated circuit wafer 240 can be applied. And a zero or weak internal force between the dummy crystal 230 and the integrated circuit wafer 240, and the dummy wafer 203 is adhered to the plurality of first side pins 2 1 to effectively reduce the warpage of the package structure 200. For example, as shown in FIG. 8 , as shown in FIGS. 5 and 6 , the package structure 200 may include a wafer holder 2 700 on both sides of the lead frame, and the first side leads 2 1 0 Arranged between the two side wafer holders 210. In addition to adhering the first side pins 210, the dummy wafers 203 are further adhered to the two wafer holders 270 to strengthen the asymmetric lead frame. The adhesive support force of the long side pin prevents the integrated circuit wafer 240 from being tilted or displaced by the injection pressure of the sealant 260. As shown in Fig. 9, the second embodiment of the present invention further discloses a The multi-wafer electrical sealing flow should be the same as the outer strong film, and the other foot is in the side crystal mode 10 1325619. The flow-balanced package structure, the main components are the same as the first embodiment. The package structure mainly includes a plurality of first side pins 21 〇 and a plurality of second side f 220 220 of a lead frame, a dummy wafer 23 〇 A, an integrated circuit wafer 240A, a plurality of bonding wires 25 〇, and A colloid is 26〇, and the components of the repeated figure are not repeated. The thickness of the dummy wafer 23A can be adjusted according to the thickness variation of the integrated circuit wafer 240A. When the integrated circuit wafer 240A is a thinner wafer, a thicker dummy wafer 23A is selected. The height of the top surface 261 of the encapsulant 260 from the first side pins 21 is approximately equal to the height of the bottom surface 262 from the integrated circuit wafer 24A to achieve the upper and lower mold flow balance of the lead frame. In a third embodiment of the invention, another package type multi-wafer mold flow balanced package construction is disclosed. As shown in FIG. 1 , a package structure 300 is a thin small outline package (TSOP) type, which mainly includes a plurality of leads 310 of a lead frame, an integrated circuit chip 320, and a dummy chip 3 3 0 . The plurality of bonding wires 34 〇 and a colloid 350 » the integrated circuit chip 320 has a _ active surface 321 and a back surface 322 ′. The active surface 321 is formed with a plurality of pads 323 . In the present embodiment, the pads 323 are concentrated in a central region of the active surface 321 which is arranged in a single row or in a plurality of rows. The active surface 321 can be attached to the underside of the pins 310 by a plurality of adhesive tapes 360, and the solder pads 323 are adjacent to the inner ends 311 of the pins 310. The b-wires 340 are electrically connected to the inner ends 311 of the pins 31. 11 1325619 In addition, the dummy wafer 330 is adhered to the back surface 322 of the integrated circuit wafer 320, thereby enhancing the warpage resistance of the integrated circuit wafer 320 and promoting the sealant 350 at the pins 310. The upper and lower mold flow balance. In this embodiment, the size of the dummy wafer 330 is not less than the integrated circuit wafer 320. The encapsulant 350 seals the dummy wafer 330, the integrated circuit wafer 320, the bonding wires 340, and the One of the pins 310. The sealing body 350 has a top surface 351 and a bottom surface 352. The height of the top surface 351 from the pins 310 is approximately equal to the height of the bottom surface 352 from the dummy wafer 330. Therefore, the mold flow balance between the upper and lower sides of the lead frame can be avoided. The wafer skew displacement has even the problem of exposure of the inner end 311 of the pin 310 and can simultaneously prevent bubble generation in the encapsulant 350. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention. [Simplified Schematic Description] Fig. 1 is a schematic view of a conventional wafer package structure. Fig. 2 is a schematic view showing the top surface of the conventional die package structure in which the upper and lower mold flows are unbalanced during the formation of a gel. . Fig. 3 is a schematic diagram of the package warp caused by the difference in volume between the upper and lower colloids during the formation of a colloid. 12 1325619 • Schematic. Figure 4 is a cross-sectional view showing a package structure of a multi-wafer mold flow balance in accordance with a first embodiment of the present invention. Figure 5 is a schematic illustration of a leadframe in the encapsulation region of the package construction in accordance with a first embodiment of the present invention. ^ Figure 6: Another cross-sectional view of the package construction in accordance with a first embodiment of the present invention. FIG. 7 is a top plan view showing the balance of the upper and lower mold flows of the lead frame in the process of forming a colloid in accordance with the first embodiment of the present invention. FIG. 8 is a first embodiment of the present invention. In the embodiment, the top view and the side view of the wafer package structure in which the upper and lower colloids are balanced due to the balance of the upper and lower colloids is illustrated. Figure 9 is a cross-sectional view showing another package structure of a polycrystalline plate flow balance according to a second embodiment of the present invention. Fig. 10 is a schematic cross-sectional view showing another package structure in accordance with a third embodiment of the present invention. [Main component symbol description] 100 chip package structure 110 first side pin 111 inner end 120 second side pin 121 inner end 130 integrated circuit chip 131 active surface 1 32 pad 13 1325619 1 4 0 wire 150 capping body 151 top surface 1 5 3 upper mold flow boundary 1 5 4 lower mold flow boundary 160 adhesive crystal tape 200 multi-chip mold flow balance package structure 2 1 0 first side pin 2 1 1 inner end 220 second side pin 221 Inner end 203 virtual wafer 230 Α virtual wafer 240 integrated circuit wafer 240 slab circuit 242 back 243 pad 2 5 0 bonding wire 260 encapsulant 261 top surface 263 upper mold boundary 264 lower mold flow boundary 270 both sides of the wafer Package structure of more than 300-chip wafer flow balance 310 Pin 311 Inner end 320 Integrated circuit chip 3 2 2 Back 3 23 Solder pad 3 3 0 Virtual wafer 3 4 0 Wire bond 350 Sealant 351 Top surface 3 6 0 Adhesive tape 1 5 2 bottom surface 241 active surface 2 6 2 bottom surface 280 adhesive tape 321 active surface 3 52 bottom surface 14

Claims (1)

L325619 十、申請專利範圍： 一種多晶片模流平衡之封裝構造，包含： 導線架之複數個第一側引腳與複數個第 中該些第-侧引腳係較長於該些第二側引腳；腳，其 一虛晶片，其係黏設於該些第一側引腳； 稩瓶电裕晶片 係黏設於該虛晶片，$ t 1 、 ，鉸背面 座a曰片，該主動面其中一側邊L325619 X. Patent Application Range: A multi-chip mold flow balanced package structure, comprising: a plurality of first side pins of a lead frame and a plurality of the first ones of the first side pins are longer than the second side leads a foot, a virtual wafer, which is adhered to the first side pins; a battery is attached to the virtual chip, $ t 1 , a hinged back seat a, the active surface One side 銲墊，盆係她姑 凡句復數個 /、係鄰近該些第一侧引腳與該歧第-伽Μ _ . 端； X —乐一侧弓丨腳之内 側引腳與 複數個銲線，其電性連接該些銲墊至該些 該些第二側引腳；以及 封勝體《係密封該虛晶片、該積體電路晶片、該些 銲線以及該些第—侧引腳與該些第二側引腳之一部位； 其中該些第“侧引腳與該些第二侧引腳之被密封部位為 無沉置水平配置，並且該封膠體係具有一頂面矣一底 面該虛a曰片提供一厚度以使該頂面距離該些第一側引 腳之高度等於該底面距離該積體電路晶片之高度。 2、如申4專利範圍帛i項所述之多晶片模流平衡之封裝構 造，另包含一導線架之兩側晶片承座，該些第一側引腳 係排列在該兩側晶片承座之間，而該虛晶片更黏設於該 兩側晶片承座。 如申請專利範圍第1項所述之多晶片模流平衡之封裝構 造，另包含複數個黏晶膠帶，以黏接該些第一侧引腳與 該虛晶片。 15 4、 如申請專利範圍帛i項所述之多晶片模流平衡之封裝構 邊，其中該些銲塾係集中在該主動面之單一侧邊，其係 為一字形單排排列或平行排交錯排列。 5、 如申請專利範圍帛1項所述之多晶片模流平衡之封裝構 造’其中該虛晶片之尺寸係不小於該積體電路晶片。 6、 一種多晶片模流平衡之封裝構造，包含： /導線架之複數個引腳； /積體電路晶片，其係具有一主動面與一背面，該主動 面係黏設於該些引腳，該主動面上係形成有複數個銲 墊，其係鄰近該些引腳之内端； 一虛晶片’其係黏設於該積體電路晶片之該背面； 複數個鲜線’其電性連接該些銲墊至該些引腳；以及 一封膠體，其係密封該虛晶片、該積體電路晶片、該些 銲線以及該些引腳之一部位；其中該些引腳之被密封部 位為無沉置水平配置，並且該封膠體係具有一頂面與一 底面’該虛晶片提供一厚度以使該頂面距離該些引腳之 尚度等於該底面距離該虛晶片之高度。 7、 如申請專利範圍第6項所述之多晶片模流平衡之封裝構 造’另包含複數個黏晶膠帶，以黏接該些引腳與該積體 電路晶片》 8、 如申請專利範圍第6項所述之多晶片模流平衡之封裝構 造’其中該些銲墊係集中在該主動面之一中央區域，.其 係為單排排列或多排排列。 9、 如申請專利範圍第ό項所述之多晶片模流平衡之封裝構 1.325619 造’其中該虚晶片之尺寸係不小於該積體電路晶片。The pad, the basin is a number of her / a number of adjacent to the first side of the pin and the gamma - _ _ . end; X - Le side of the bow and the inner pin and a plurality of wire Electrically connecting the pads to the second side pins; and sealing the body to seal the dummy wafer, the integrated circuit wafer, the bonding wires, and the first side pins One of the second side pins; wherein the first side pin and the second side pin are sealed in a non-sinking horizontal configuration, and the sealing system has a top surface and a bottom surface The dummy a chip is provided with a thickness such that the height of the top surface from the first side pins is equal to the height of the bottom surface from the integrated circuit chip. 2. The multi-wafer module as described in claim 4 The flow-balanced package structure further includes a wafer holder on both sides of the lead frame, the first side pins are arranged between the two side wafer holders, and the dummy wafer is further adhered to the two sides of the wafer carrier The package structure of the multi-wafer mold flow balance described in claim 1 of the patent application, further comprising a plurality of sticks a tape for bonding the first side pins and the dummy wafer. 15 4. The multi-wafer mold flow balancing package edge according to claim 帛i, wherein the soldering systems are concentrated on the active The single side of the surface is arranged in a single row or in a parallel row. 5. The multi-chip mold flow balancing package structure as described in claim 1 wherein the size of the virtual wafer is not less than The integrated circuit chip 6. A multi-chip mold flow balanced package structure comprising: / a plurality of leads of a lead frame; / an integrated circuit chip having an active surface and a back surface, the active surface is adhesive Provided on the pins, the active surface is formed with a plurality of pads adjacent to the inner ends of the pins; a dummy wafer is attached to the back surface of the integrated circuit chip; a fresh wire 'electrically connecting the pads to the pins; and a gel that seals the dummy wafer, the integrated circuit chip, the bonding wires, and one of the pins; The sealed parts of these pins are no sinking level And the sealing system has a top surface and a bottom surface. The virtual wafer provides a thickness such that the top surface is spaced from the pins by a height equal to the height of the bottom surface from the virtual wafer. 7. The multi-wafer mold flow balancing package structure described in item 6 further includes a plurality of die-bonding tapes for bonding the pins and the integrated circuit chip. 8. As described in claim 6 The package structure of the wafer mold flow balance, wherein the pads are concentrated in a central region of the active surface, which is arranged in a single row or in a plurality of rows. 9. The multi-chip described in the scope of the patent application. The mold flow balanced package structure 1.325619 is formed in which the size of the dummy wafer is not less than the integrated circuit chip. 17 132561917 1325619 154154 1818
TW95135648A 2006-09-26 2006-09-26 Multi-chip package to optimize mold-flow balance TWI325619B (en)

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