TW495889B - A method for forming a package body of a window BGA package - Google Patents

A method for forming a package body of a window BGA package Download PDF

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Publication number
TW495889B
TW495889B TW090113426A TW90113426A TW495889B TW 495889 B TW495889 B TW 495889B TW 090113426 A TW090113426 A TW 090113426A TW 90113426 A TW90113426 A TW 90113426A TW 495889 B TW495889 B TW 495889B
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TW
Taiwan
Prior art keywords
circuit substrate
wafer
window
mold
forming
Prior art date
Application number
TW090113426A
Other languages
Chinese (zh)
Inventor
Ya-Fen Lin
Shiaw-Ming Chao
Huei-Chiau Lee
Cho-Liang Chung
Original Assignee
Chipmos Technologies Inc
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Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW090113426A priority Critical patent/TW495889B/en
Application granted granted Critical
Publication of TW495889B publication Critical patent/TW495889B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to a method for forming a package body of a window BGA package, the window BGA package includes a circuit substrate, a chip, a plurality of bonding wires and a plurality of solder balls. After wire-bonding, the assembly of the chip and the circuit substrate puts in an upper mold and a lower mold. The lower mold has an air-extracting hole for a tight contact of the lower mold and the circuit substrate of the window BGA package.

Description

495889 五、發明說明（1) 【發明領域】 本發明係有關於一種窗口 BGA封裝結構之封膠體形成 方法。 【先前技術】 目前在習知半導體封裝結構中，其中一種窗口 BG A封 裝結構〔Window Bal 1 Grid Array package〕係以一具有 窗口之電路基板承載並電性傳輸一晶片，該電路基板並形 成有複數個矩陣排列之焊球，如第1圖所示，該習知窗口 BGA封裝結構1〇〇内含有一電路基板12〇、一晶片i3〇及複數 個焊球150，該電路基板120具有一上表面123、一下表面 124及至少一窗口125 ;該晶片130係以黏膠131固定於上述 之電路基板120之上表面123，且以焊線140電性連接該晶 片130及電路基板120，再於壓模封膠後焊接複數個焊球 150於該電路基板120之下表面124。 如第2圖所示，當焊線丨4〇電性連接晶片13〇及電路基 板120後，便於上模具11〇及下模具U1中進行壓模封裝， 其上模具具有一注膠口 16〇，用以注入封膠體17〇包覆晶片 130四周及密封上述之窗口 125，該下模具U1具有一通氣 孔1 6 1，當封膠體1 7 〇注入上模具丨丨〇且於晶背進行壓模 蛉，部分封膠體170會從下模具ln之通氣161孔排出。 然而此種窗口BGA封裝結構之封膠體形成方法，於壓 模時晶片130背部必須以上模具11〇直接加壓，以務使電路 基板120及下模具Hi緊密接觸，以防止電路基板12〇之下 表面127受到溢膠污染，但卻有因晶片背部裸露，無封膠 495889 五、發明說明（2) 體1 7 0保護而有容易受損之缺點。 在美國專利第6, 1 77, 723號「積體雷故& & ， 製鞋中，签q国& 封裝及其麼模 ^程」巾第3圖為該積體電路封裝、结構之截 為該積體電路封裝έ士禮左愿禮狀能夕&、 適用於廢㈣：： 俯視圖，而第5圖為 週用於壓模過程中之上模具及下模具之立體圖。 路柄如第3曰=’該積體電路封裝結構200包含-多層電 2板、一曰曰片230、複數個焊線24〇及複數個焊球；該多層 電路板係屬於印刷電路基板（PCB)，其具有第一層電路基 ，220、而第一層電路基板221、第三層電路基板，第 二層電路基板221、第三層電路基板222係建構於第一層電 路基板220上:該第一層電路基板22〇形成有一凹槽226及 上開口225，第二層電路基板221係由第一導通柱28〇電性 連接第一焊球250，與第二層電路基板221連接之第三層電 路基板222係以黏膠231固定一晶片230，該晶片230係電性 連接複數個焊線240，並於已形成焊線24〇之晶片230及多 層電路板於壓模封膠後，於第一層電路基板22〇之上表面 223焊接上複數個第二焊球2 51，第一層電路基板2 20之下 表面224焊接上複數個第三焊球252，並以第二導通柱281 電性連接該上述之複數個第二焊球251及複數個第三焊球 252。 如第4圖所示，將已形成焊線2 40之晶片230及多層電 路板置入一上模具210及一下模具211中進行壓模封膠，該 上模具210具有複數個注膠口 260、上模具通氣孔261及滑 槽262 (第5圖所示），當上模具21〇於滑槽262注膠時，流動495889 V. Description of the invention (1) [Field of the invention] The present invention relates to a method for forming a sealant for a window BGA package structure. [Previous Technology] Currently, in a conventional semiconductor package structure, a window BG A package structure [Window Bal 1 Grid Array package] is carried on a circuit substrate with a window and electrically transmits a chip. The circuit substrate is formed with A plurality of solder balls arranged in a matrix, as shown in FIG. 1, the conventional window BGA package structure 1000 includes a circuit substrate 120, a wafer i30, and a plurality of solder balls 150. The circuit substrate 120 has a The upper surface 123, the lower surface 124, and at least one window 125; the chip 130 is fixed on the upper surface 123 of the circuit substrate 120 with an adhesive 131, and the chip 130 and the circuit substrate 120 are electrically connected by a bonding wire 140, and then A plurality of solder balls 150 are soldered to the lower surface 124 of the circuit substrate 120 after the mold is sealed. As shown in FIG. 2, when the bonding wire 410 is electrically connected to the wafer 13 and the circuit substrate 120, it is convenient for compression molding in the upper mold 11 and the lower mold U1, and the upper mold has a glue injection port 16. It is used to inject the sealing compound 170 to cover the periphery of the wafer 130 and seal the above-mentioned window 125. The lower mold U1 has a vent hole 161. When the sealing compound 170 is injected into the upper mold and the die is pressed on the crystal back Alas, part of the sealing compound 170 will be discharged from the vent 161 hole of the lower mold ln. However, in this method of forming a sealant for a window BGA package structure, the back of the wafer 130 must be directly pressurized above the mold 110 during compression molding, so that the circuit substrate 120 and the lower mold Hi are in close contact to prevent the circuit substrate 120 from being under. The surface 127 is contaminated by overflowing glue, but it has the disadvantage of being easily damaged because the back of the wafer is exposed and there is no sealant 495889. 5. Description of the invention (2) The body is protected by 170. In U.S. Patent No. 6, 1 77, 723, "Integrated Thunder & & Footwear, signing the country & package and its module process" Figure 3 shows the package circuit and structure of the integrated circuit The cut-off is the integrated circuit package 士士 礼 左 愿 礼 状 能 能 &, applicable to waste :: Top view, and Figure 5 is a perspective view of the upper and lower molds used in the compression process. The handle of the road is as follows: 'The integrated circuit packaging structure 200 includes-a multi-layer electrical board, a 230 chip, a plurality of bonding wires 240, and a plurality of solder balls; the multilayer circuit board belongs to a printed circuit board ( PCB), which has a first-layer circuit substrate 220, and a first-layer circuit substrate 221, a third-layer circuit substrate, a second-layer circuit substrate 221, and a third-layer circuit substrate 222 are constructed on the first-layer circuit substrate 220 The first layer of the circuit substrate 22 is formed with a groove 226 and an upper opening 225. The second layer of the circuit substrate 221 is electrically connected to the first solder ball 250 by the first conductive post 28 and is connected to the second layer of the circuit substrate 221. The third layer of the circuit substrate 222 is fixed with a chip 230 with an adhesive 231. The chip 230 is electrically connected to a plurality of bonding wires 240, and is sealed on the die 230 and the multilayer circuit board with the bonding wire 240 formed by a die. Then, a plurality of second solder balls 2 51 are soldered on the upper surface 223 of the first layer of the circuit substrate 22 and a plurality of third solder balls 252 are soldered on the lower surface 224 of the first layer of the circuit substrate 2 20. The conducting post 281 is electrically connected to the plurality of second solder balls 251 and the plurality of third solder balls. Ball 252. As shown in FIG. 4, the wafer 230 and the multilayer circuit board on which the bonding wires 2 40 have been formed are placed in an upper mold 210 and a lower mold 211 for compression molding, and the upper mold 210 has a plurality of glue injection ports 260, The upper mold vent hole 261 and the sliding groove 262 (shown in FIG. 5), when the upper mold 21 is filled with glue in the sliding groove 262, it flows.

495889 五、發明說明（3) 體27〇會經由注移口 260流進凹槽226及上㈤口m處 η”η之，而注入之部分少量封膠體27〇會於壓模時從上 換具210之上模具通翁β ^ ψ ώ ；\通乳孔261及下杈具之下模具通氣孔263 古該多層電路基板及晶片23〇於模具内 之密合度不夠L並層電路基板與晶片23° 〇2〇 ^ ^ ^ ^ 並办易在第一層電路基板220上表面 223有溢膠情況發生之缺點。 【發明目的及概要】 ^ί發明之主要目的在於提供一種窗口BGA封裝結構之 膠時進行抽氣使:LGA曰封裝結構於模具内塵模封 接合更緊密，有效而裸日日之情況下電路基板與模具 質不的防止溢膠情形發生，避免造成焊接品 表面及至少一窗口，主二从扣 卜 ^ ^ ^ ^ 其上表面係用以放置晶片，一曰Κ ， 位於該電路基板之上表面， 曰曰 述之晶片及電路基板，複數 、、、二囪口連.接上 表面，用以外部電性連接及一封膠體；蛋路基板之下 其封膠體形成方法包含以下步驟·· a、 ^供具有傳導性之電路美 定晶片； 电峪基板，用以傳導電性及固 b、 將晶片固定於電路基板上表面； c、 電性連接晶片及電路基板；並且 第6頁 五、發明說明（4) 01 ϊ ί ϊ ί ϊ 1曰片與電路基板之組合構造置入 υ下杈具中進行壓模，其中上模具有一注 ^米以注入流動之封膠體，且下模具有一抽 ϊ更為膠時同時進行抽氣，使封膠體之密合 【發明詳細說明】495889 V. Description of the invention (3) The body 27o will flow into the groove 226 and the upper part of the upper mouth m through the injection port 260, and a small amount of the encapsulated body 27 will be changed from the upper part when the mold is pressed. Above the mold 210, the through hole β ^ ψ; \ Through the milk hole 261 and the lower mold vent hole 263, the multilayer circuit substrate and wafer 23 are not tight enough in the mold, and the circuit substrate and the wafer are layered. 23 ° 〇2〇 ^^ ^ ^ It is easy to do the shortcomings of glue overflow on the upper surface 223 of the first layer of circuit substrate 220. [Objective and Summary of the Invention] The main purpose of the invention is to provide a window BGA package structure. Extraction during the bonding process: LGA said that the package structure is tighter in the mold and dust in the mold, and the circuit board and the mold are prevented from overflowing under the condition of bareness, which prevents the surface of the soldered product and at least one The window, the main two slave buckle ^ ^ ^ ^ Its upper surface is used to place a wafer, a K, located on the upper surface of the circuit substrate, said the wafer and the circuit substrate, a plurality of ,,, and two stacks connected. Connect to the surface for external electrical connection and an adhesive ; The method for forming the sealing gel under the egg circuit substrate includes the following steps: a, ^ for the circuit with a conductive wafer; electrical substrate; used to conduct electricity and fix b; fix the wafer to the upper surface of the circuit substrate C. Electrically connect the chip and the circuit substrate; and Page 6 V. Description of the invention (4) 01 ϊ ί ϊ ί ϊ 1 The combined structure of the film and the circuit substrate is placed in a lower mold for compression molding, in which The mold has a note of ^ meters to inject the flowing sealing gel, and the lower mold has a pumping pinch to simultaneously pump air to make the sealing gel close. [Detailed description of the invention]

2j閱所附圖式’本發明將列舉以下之實施例說明： 及7圖所不係為本發明之第一具體一 口 BGA封裝結構之封膠體形成方法，其中"圖為該窗口齒 BGA封裝結構在壓模狀態之截面圖，而第7圖為該窗口肫八 封裝結構之截面圖，其結構詳述如后： 尽如第7圖所示，本發明係為一種在壓模模具上加設抽 氣孔361之設計，其窗口BGA封裝結構3〇〇包含有一電路基 板320，一晶片330，複數個焊線34〇及焊球35〇，其中該電 路基板 320 係為一種 FR-4、Cyanate ester (BT 材料）、2j read the attached drawings' The present invention will enumerate the following embodiment description: and Figure 7 is not a method for forming a sealant gel of the first specific one-piece BGA packaging structure of the present invention, in which " the picture shows the window tooth BGA package A cross-sectional view of the structure in the stamping state, and FIG. 7 is a cross-sectional view of the package structure of the window, the detailed description of the structure is as follows: As shown in FIG. 7, the present invention is a kind of The design of the suction hole 361, the window BGA package structure 300 includes a circuit substrate 320, a wafer 330, a plurality of bonding wires 34 and solder balls 35, wherein the circuit substrate 320 is a FR-4, Cyanate ester (BT material),

Aramid環氧或陶瓷電路基板，具有一上表面323、一下表 面324及至少一窗口 325〔 window〕，上表面323係以黏膠 3 31固定晶片3 3 0 ;複數個烊線3 4 0，係經由窗口 3 2 5電性連 接上述之晶片330及電路基板320，且於電性連接該晶片 330與電路基板320組合構造後，置入上模具31〇下模具311 中進行壓模封膠，在壓模封膠後將複數顆焊球35()，焊接 於該電路基板320之下表面324，用以外部電性連接。 如第6圖所示，將已形成電性連接焊線34〇之電路基板 320與晶片330之組合構造放置於上模具31〇及下模具311中An Aramid epoxy or ceramic circuit substrate has an upper surface 323, a lower surface 324, and at least one window 325 [window]. The upper surface 323 is fixed to the wafer 3 3 by an adhesive 3 31; a plurality of reed wires 3 4 0, The wafer 330 and the circuit substrate 320 are electrically connected through the window 3 2 5. After the combined structure of the wafer 330 and the circuit substrate 320 is electrically connected, the upper mold 31 and the lower mold 311 are placed in the mold for sealing and sealing. After the mold is sealed, a plurality of solder balls 35 () are soldered to the lower surface 324 of the circuit substrate 320 for external electrical connection. As shown in FIG. 6, the combined structure of the circuit substrate 320 and the wafer 330 on which the electrical connection wire 34 has been formed is placed in the upper mold 31 and the lower mold 311.

第7頁 495889 五、發明說明（5) 進行壓模’其中上模具31〇有一注膠口 36〇〔 gate〕供封膠 體370注入模穴，且上模具310與在電路基板320上表面323 之晶片330具有一適當間距，供封膠體37〇 〔encapsulant〕填充密封晶片330，以防止晶片330背部 裸露於外而受到損傷，而下模具311具有一抽氣孔361，當 封膠體370由上模具31〇之注膠口36〇注入模穴〔（：&。1^〕 時，下模具311之抽氣孔361便同時進行抽氣，在電路基板 320下表面324之窗口 325處形成一吸力，以增加電路基板 320之下表面324與下模具311間之密合度，防止電路基板 下表面324產生溢膠之情況發生，污染電路 基板320之下表面324，造成電路基板32〇之下表面3 , 接焊球3 5 0時電性接觸不良。 者為 範圍 圍。 故本發明之保護範圍當視後 準’任何熟知此項技藝者， 内所作之任何變化與修改， 附之申請專利範圍所界定 在不脫離本發明之精神和 均屬於本發明之保護範Page 7 495889 V. Description of the invention (5) Performing the compression molding, wherein the upper mold 31 〇 has an injection port 36 〇 [gate] for sealing gel 370 to be injected into the cavity, and the upper mold 310 and the upper surface 323 of the circuit substrate 320 The wafer 330 has a proper distance for the encapsulant 37 to fill the sealed wafer 330 to prevent the back of the wafer 330 from being exposed and damaged, and the lower mold 311 has an exhaust hole 361. When the encapsulant 370 passes from the upper mold 31 When the injection port 36 of 〇 is injected into the cavity [(: & .1 ^]), the suction holes 361 of the lower mold 311 are simultaneously pumped, and a suction force is formed at the window 325 of the lower surface 324 of the circuit board 320. Increase the closeness between the lower surface 324 of the circuit substrate 320 and the lower mold 311 to prevent the occurrence of glue overflow on the lower surface 324 of the circuit substrate, and contaminate the lower surface 324 of the circuit substrate 320, resulting in the lower surface 3 of the circuit substrate 32. The solder ball has a poor electrical contact at 3500. The scope is the scope of the invention. Therefore, the scope of protection of the present invention shall be determined after any changes and modifications made by any person familiar with the art, as defined by the scope of the attached patent. Without departing from the spirit and scope of the present invention,

圖式簡單說明 【圖式說明 第4圖 第5圖 第6圖 第7圖 =用窗口BGA封裝結構之截面圖； 習用窗口BGA封裝結構在壓模狀態之截面圖； 依，國專利第6，1 77,723號「積體電路封裝及其 壓模製程」，一積體電路封裝結構之截面圖； 專利第6，1 77,723號「積體電路封裝及其壓 模製裎」’一積體電路封裝結構在壓模狀態之截 面圖；美國專利第6，1 77,723號「積體電路封裝及其壓 模製程」，適用於壓模過程中之上模具及下模具 之立體圖； ' 在本發明之第一具體實施例中， 結構在壓模狀態之截面圖；及 在本發明之第一具體實施例中， 結構之截面圖。 窗口 BGA封裝 窗口 BGA封裝 【圖號說明】 1〇〇窗口 BGA封裝結構 下模具 面 124下表面 1 31黏膠 1 6 1通氣孔 495889 圖式簡單說明 170 封膠體 20 0積體電路封裝結構 21 0上模具 2 11下模具 220第一層電路基板221第二層電路基板 222第三層電路基板223上表面 224下表面 225上開口 226 凹槽 230晶片 240 焊線 2 5 0 第一焊球 2 6 0 注膠口 2 6 3下模具通氣孔 270 封膠體 280 第一導通柱 300 31 0上模具 3 2 0 電路基板 325 窗口 3 3 0晶片 窗口 BGA封裝結構 2 3 1黏膠 2 5 1第二焊球 2 6 1 上模具通氣孔 281第二導通柱 311下模具 323 上表面 3 31黏膠 252 262 第三焊球 滑槽Brief description of the drawings [Illustration of the drawings Figure 4 Figure 5 Figure 6 Figure 7 = Cross-sectional view of the window BGA packaging structure; Cross-sectional view of the conventional window BGA packaging structure in the stamped state; according to the national patent No. 6, No. 1 77,723 "Integrated Circuit Packaging and Its Compression Molding Process", a cross-sectional view of an integrated circuit packaging structure; Patent No. 6,1 77,723 "Integrated Circuit Packaging and Its Compression Molding 裎" 'Integrated Circuit Packaging Sectional view of the structure in the stamping state; US Patent No. 6,1 77,723 "Integrated Circuit Packaging and Its Stamping Process", which is applicable to the perspective view of the upper and lower molds during the stamping process; In a specific embodiment, a cross-sectional view of a structure in a stamped state; and in a first specific embodiment of the present invention, a cross-sectional view of a structure. Window BGA package Window BGA package [Illustration of drawing number] 100 Window BGA package structure Under mold surface 124 Lower surface 1 31 Adhesive 1 6 1 Vent hole 495889 Simple illustration of 170 Sealant 20 0 Integrated circuit package structure 21 0 Upper mold 2 11 Lower mold 220 First layer circuit substrate 221 Second layer circuit substrate 222 Third layer circuit substrate 223 Upper surface 224 Lower surface 225 Opening 226 Groove 230 Wafer 240 Welding wire 2 5 0 First solder ball 2 6 0 Glue injection port 2 6 3 Lower mold vent hole 270 Sealant 280 First lead post 300 31 0 Upper mold 3 2 0 Circuit board 325 Window 3 3 0 Wafer window BGA package structure 2 3 1 Adhesive 2 5 1 Second solder Ball 2 6 1 Upper mold vent hole 281 Second conduction post 311 Lower mold 323 Upper surface 3 31 Adhesive 252 262 Third solder ball chute

324 下表面324 lower surface

340 焊線 350 焊球 3 6 0 注膠口 3 61 抽氣孔 370 封膠體340 Welding wire 350 Welding ball 3 6 0 Filling port 3 61 Vent hole 370 Sealing gel

第10頁 iP. 10 i

Claims (1)

六、申請專利範圍 【申請專利範圍】 1私:種窗口BGA封裝結構之封膠體形成方法，該窗口BGA ^裝結構包含有··一電路基板，具有一上表面、一下表 位^至少一窗口 ，其上表面係用以放置晶片，一晶片， ^該電路基板之上表面，複數個焊線，經由窗口連接 之=之晶片及電路基板，複數顆焊球，位於該電路基板 下表面，用以外部電性連接及一封膠體； 其封膠體形成方法包含以下步驟： a、 提供具有傳導性之電路基板，用以傳導電性及固 疋晶片； b、 將晶片固定於電路基板上表面； c d ma 圖 電性連接晶片及電路基板；並且 將已形成焊線之晶片與電路基板之組合構造置入 上模具與下模具中進行壓模，其中上模具有一注 ，口 ’用以注入流動之封膠體，且下模具有一抽 氣孔，當注膠時同時進行抽氣，使封膠體之密合 度更為緊密。 封t申請專利範圍第1項中所述之窗口BGA封裝結構之 有二體形成方法，其中在4步驟中，該上模具與晶片具 —間距以供封膠體密封晶片。6. Scope of patent application [Scope of patent application] 1 Private: A method for forming a sealant gel of a window BGA packaging structure, the window BGA mounting structure includes a circuit substrate with an upper surface and a lower epitope ^ at least one window The upper surface is used to place a wafer, a wafer, the upper surface of the circuit substrate, a plurality of bonding wires, the wafer and the circuit substrate connected via a window, and a plurality of solder balls on the lower surface of the circuit substrate. An external electrical connection and a gel are provided. The method for forming a sealing gel includes the following steps: a. Providing a conductive circuit substrate for conducting electricity and fixing the wafer; b. Fixing the wafer on the upper surface of the circuit substrate; cd ma Figure electrically connects the wafer and the circuit substrate; and the combined structure of the wafer and the circuit substrate on which the bonding wire has been formed is placed in the upper mold and the lower mold for compression molding, wherein the upper mold has a note, and the mouth is used to inject the flowing Sealing colloid, and the bottom mold has a suction hole, which is pumped at the same time when the glue is injected, so that the tightness of the sealing colloid is closer. There is a two-body forming method for the window BGA package structure described in the first patent scope of the application, wherein in the four steps, the upper mold and the wafer are spaced apart for the sealing gel to seal the wafer. 第11頁Page 11
TW090113426A 2001-05-28 2001-05-28 A method for forming a package body of a window BGA package TW495889B (en)

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