TWI237366B - Thermal-enhance package and manufacturing method thereof - Google Patents

Thermal-enhance package and manufacturing method thereof Download PDF

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Publication number
TWI237366B
TWI237366B TW93103552A TW93103552A TWI237366B TW I237366 B TWI237366 B TW I237366B TW 93103552 A TW93103552 A TW 93103552A TW 93103552 A TW93103552 A TW 93103552A TW I237366 B TWI237366 B TW I237366B
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Taiwan
Prior art keywords
carrier board
board unit
package
patent application
heat dissipation
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TW93103552A
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Chinese (zh)
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TW200527631A (en
Inventor
Yaw-Yuh Yang
Ting-Rung Cheng
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Advanced Semiconductor Eng
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Publication of TW200527631A publication Critical patent/TW200527631A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A thermal-enhance semiconductor package mainly comprises a semiconductor chip, a carrier unit, a plurality of electrically conductive wires, an encapsulation unit and a thermal paste layer. The semiconductor chip is disposed on the carrier unit and electrically connected thereto through said electrically conductive wires. Said thermal paste is disposed on the surface of the encapsulation unit. In such manner, the heat generated from the semiconductor chip will be transmitted to outside faster. Besides, the invention also provides a method for manufacturing the thermal-enhance semiconductor package as mentioned above.

Description

12373661237366

五、發明說明（1) (―)、【發明所屬之技術領域】 本發明係關於_ -種封膠單元表面上口 封裝體，特別是有關於 及其製造方法。 11有政熱膠層之加強散熱型封裝體V. Description of the invention (1) (-), [Technical field to which the invention belongs] The present invention relates to a kind of surface-sealing package of a sealing unit, and more particularly to a method for manufacturing the same. 11Enhanced heat dissipation type package with thermal adhesive layer

^ ά近年來，隨著電子技術的日新月里，雷+嘉σ I χ έ 向輕、Μ、te ， 于4月兵電子產品無不朝 用。為因應此一趨：趨：設f」以提供更便利舒適的使 電路連接的封裝έ士構士 ^遵半導體晶片以及提供外部 構也同樣需要輕薄短小化。^ ά In recent years, with the advancement of electronic technology, Lei + Jia σ I χ 向 to light, M, te, in April, all electronic products have been used. To cope with this trend: the trend: set f "to provide more convenient and comfortable packaging connections for circuit connections. Compliance with semiconductor chips and the provision of external structures also require thinner, shorter and lighter.

Arr/ U構裝的領域中，球格陣列封裝(Ba" Grid 地電感及低雷、、择Λ 的封裝形式，因其具有低接 .^ ；；、f源電感及多接腳數等優點，故適合於高密度 ί f二球陣列封裝係以BT(Bismaleiraide-Triazine)或 =胺(P〇lyimide)為主要材質之載板來承載晶片，並j 由導電性良好之金線電性連接晶片與載板。載板的一面具 有排列成陣列型態錫球（so丨der ba丨丨），其係用以將整個 裝結構體電性連接至外界電路（如印刷電路板）。 、 薄型球格陣列封裝（Low&Thin BGA)為一種晶片尺寸封 裝（chip scale package, CSP)，其球距小、厚度薄。習 知的薄型球格陣列封裝製程包含下列步驟：首先，如圖1所 示，提供一載板1，此載板1包含數個載板單元n，其係以 陣列的方式排列。每一載板單元1丨包含一晶片承座丨丨2，及 環繞於晶片承座112外圈之手指114( finger)。接著，如圖2In the field of Arr / U structure, ball grid array package (Ba " Grid ground inductance and low thunder, and Λ package form, because of its low connection. ^ ;; f-source inductance and multi-pin number and other advantages Therefore, it is suitable for high-density two-ball array packaging. It uses BT (Bismaleiraide-Triazine) or = amine (Polyimide) as the main material to carry the chip, and j is electrically connected by a conductive gold wire. Chip and carrier board. One side of the carrier board has arrayed solder balls (so 丨 der ba 丨 丨), which are used to electrically connect the entire assembly structure to external circuits (such as printed circuit boards). Low & Thin BGA is a chip scale package (CSP) with small ball pitch and thin thickness. The conventional thin ball grid array packaging process includes the following steps: First, as shown in Figure 1 As shown, a carrier board 1 is provided. The carrier board 1 includes a plurality of carrier board units n, which are arranged in an array. Each carrier board unit 1 includes a wafer holder 2 and surrounds the wafer holder. Finger 114 (finger) of 112 outer circle. Then, as shown in Figure 2

第6頁 1237366 五、發明說明（2) 所示’利用銀膠（silver paste)將數個晶片21分別貼人 每-載板單元Η中的晶片承座上(未標示於圖中），並：： 黏晶製程後固化銀膝。然、後以金線23進行打線 = 晶片2i以及載板單元U之手指（未標示於圖中）。打= 後’載板11以及貼在其上之晶片21係利用陣列封模方2成 (matnx molding process)以封膠體24 包覆。接著 _ 射或油墨於封裝體之上表面打上識別標記(mark)。最= 灯封膠後穩定固化（post curing)以及以切割刀切 (singulation)，而完成整個封裝製程（如圖3所示平顆 由於晶片於運行時會產生高熱，故為增加薄 列封裝之散熱速率，可於其表面加設一散熱片。一般而車 言’如圖4A及4B所示’於前述進行陣列封膜 大尺寸散熱片3同時置於進行封膜的模具 ^ ^ 熱片3係包含複數個散熱片單元31，且每m政 別對應於每一载板單元11。將散熱片3與晶片2卜^ = 膜，以使封膠體24連同散熱片3進行 面係曝露在封膠體24的外面。承上所述，於封膠固化^ 後，=如，示之具有散熱片之薄型球格陣列封Λ模 構。最後，連同散熱片3及載板^行切割步驟，^形裝成; 圖6所不之具有散熱片之薄型球格封裝結構。 .ί:私t ί的薄型球格封裝結構仍存在些缺點，例 以會因支撑點之不足，而導：：：利用其兩邊支樓著’所 致…形，無法LG;散熱片因承受自身重力，以 1237366Page 6 1237366 V. Description of the invention (2) 'Using silver paste, several wafers 21 are respectively placed on the wafer holders in each carrier board unit (not shown in the figure), and ：: Silver knee is cured after the sticking process. Then, wire with gold wire 23 = the finger of the chip 2i and the carrier unit U (not shown in the figure). The "back" carrier plate 11 and the wafer 21 pasted thereon are covered with an encapsulant 24 using a matnx molding process. Then _ or mark the upper surface of the package with an ink or ink. Most = Stable curing after lamp sealing (singulation) and singulation to complete the entire packaging process (as shown in Figure 3, flat wafers will generate high heat during operation, so it is necessary to increase The heat dissipation rate can be provided with a heat sink on the surface. Generally speaking, the words “as shown in FIGS. 4A and 4B” are used to seal the large-size heat sink 3 that is arrayed at the same time and placed in the mold for sealing ^ ^ 3 The system includes a plurality of heat sink units 31, and each m corresponds to each carrier board unit 11. The heat sink 3 and the wafer 2 are thin films, so that the sealing compound 24 and the heat sink 3 are exposed to the surface. The outer surface of the colloid 24. As mentioned above, after the sealant is cured ^, as shown in the thin ball grid array seal Λ with heat sink. Finally, the cutting step is performed with the heat sink 3 and the carrier plate ^ The thin ball grid packaging structure with a heat sink is not shown in Figure 6. ί: private t The thin ball grid packaging structure still has some shortcomings. For example, due to the lack of support points, it leads ::: Utilize the shape of the branches on both sides of it ... can not be LG; the heat sink is subject to its own gravity By 1237366

(三）、【發明内容] 有鑑於上述課題，本發明之目的提供 封裝體及其製造方法，直能扃太祜田私备p力強政熱型 ,^ ^ ^ . 其此在不使用散熱片之情況下，難 由封膠表面之散熱膠層來提高封裝體的散熱性，以 ^ 體内之晶片運作時，所產生的熱能夠順利 ^破 因散熱膠層係為一薄膜狀，故可縮小封裝體2體 緣疋為了達成上述目的，本發明係提供提供一種 強散熱型封裝^，其主要包含__半㈣晶片、—載板單加 7L、稷數條導電線、一封膠單元及一散熱膠層。半導體曰 片係设置於該載板單元上且藉由導電線與載板單元電性= 接。另外、封膠單元係包覆晶片、導電線及載板上表面. 散熱膠=塗佈於封膠單元之表面，以使半導體晶片產生的 熱旎夠藉由散熱膠層更快速地傳導至外界。 本發明亦提供一種加強散熱型封裝體之製造方法，其 包括下列步驟：提供一陣列型載板，其包含複數個載板單 兀’。將複數個半導體晶片分別藉由導電線電性連接至每_ 載板單70 ;以一塑料包覆該等半導體晶片及該陣列型散熱 片，以形成一陣列式封膠體；塗佈散熱膠層於陣列式封膠 體之表面；及對該陣列式封膠體進行一切割程序，以形成(III) [Content of the invention] In view of the above-mentioned problems, the object of the present invention is to provide a package and a manufacturing method thereof, which are capable of directly heating and cooling, ^ ^ ^. No heat dissipation is used here. In the case of a sheet, it is difficult to improve the heat dissipation of the package by the heat-dissipating adhesive layer on the surface of the sealant. When the chip operates in the body, the heat generated can be smoothly broken. The heat-dissipating adhesive layer is a thin film, so The package body 2 can be reduced. In order to achieve the above-mentioned object, the present invention provides a heat-dissipating package ^, which mainly includes a __half chip, a carrier board plus 7L, a plurality of conductive wires, and an adhesive. The unit and a layer of thermal adhesive. The semiconductor chip is disposed on the carrier board unit and is electrically connected to the carrier board unit through a conductive wire. In addition, the sealant unit covers the surface of the wafer, conductive wires, and carrier board. Thermal radiation adhesive = coated on the surface of the sealant unit, so that the heat generated by the semiconductor wafer can be more quickly conducted to the outside through the heat radiation adhesive layer. . The present invention also provides a method for manufacturing a heat-dissipating package, which includes the following steps: providing an array type carrier board including a plurality of carrier board units. A plurality of semiconductor wafers are electrically connected to each carrier board 70 by conductive wires; the semiconductor wafers and the array-type heat sink are covered with a plastic to form an array sealing compound; a heat-dissipating adhesive layer is applied On the surface of the array type sealant; and performing a cutting process on the array type sealant to form

第8頁 1237366 五、發明說明（4) 複數個封裝單元。 承上所述’本發明係利用封膠表面之散熱膠層來提高 封裝體的散熱性，以提升封裝體之散熱效果；再者，因散熱 膠層係為一薄膜狀，故可縮小封裝體之整體厚度。 (四）、【實施方式】 以下將參照相關圖式，以說明本發明較佳實施例之加 強散熱型封裝體。 圖7 A係揭示本發明第一較佳實施例之加強散熱型封裝 體’其主要包含一載板單元51、一半導體晶片6 1、複數條 導電線63、一封膠單元64及一散熱膠層71。該載板單元51 具有一上表面512及一下表面514，該半導體晶片61係設置 於該載板單元51之上表面512且與該載板單元51電性連接。 又’散熱膠層71係直接設置於該封膠單元β4之表面641上， 故此使半導體晶片6 1產生的熱能夠快速地傳導至外界。其 中’該散！膠層71可由液態薄膜膠經烘烤而固化形成，或 為一散熱膠f或薄臈直接貼附於封膠單元64之表面641。此 外，如圖7B所示，係揭示本發明第二較佳實施例之加強散 熱型封裝體，其中，該半導體晶片61亦可藉由導電凸塊68 以覆晶接合方式與該載板單元5 1電性連接。再者，咳載板 單元51之下表面514更可形成有複數個導電元件67(=鲜球） ，用以與外界電性連接。 承上所述，該載板單元5 1亦可為一導線架（1 e a d frame)形式，即該加強散熱型封裝體可為一無外彳丨腳封fPage 8 1237366 V. Description of the invention (4) A plurality of packaging units. According to the above description, the present invention uses the heat-dissipating adhesive layer on the surface of the sealing compound to improve the heat dissipation of the package, so as to improve the heat-dissipating effect of the package. Furthermore, because the heat-dissipating adhesive layer is a thin film, the package can be reduced. Its overall thickness. (4) [Embodiment] The following will describe the enhanced heat dissipation package of the preferred embodiment of the present invention with reference to related drawings. FIG. 7A is a reinforced heat-dissipating package according to the first preferred embodiment of the present invention, which mainly includes a carrier board unit 51, a semiconductor wafer 61, a plurality of conductive wires 63, a glue unit 64, and a heat-dissipating glue. Layer 71. The carrier board unit 51 has an upper surface 512 and a lower surface 514. The semiconductor wafer 61 is disposed on the upper surface 512 of the carrier board unit 51 and is electrically connected to the carrier board unit 51. Furthermore, the heat-dissipating adhesive layer 71 is directly disposed on the surface 641 of the sealing unit β4, so that the heat generated by the semiconductor wafer 61 can be quickly conducted to the outside. Among them, ‘Caution! The adhesive layer 71 can be formed by baking and solidifying the liquid film adhesive, or it can be directly attached to the surface 641 of the sealing unit 64 by a heat-dissipating adhesive f or thin film. In addition, as shown in FIG. 7B, the heat dissipation enhanced package of the second preferred embodiment of the present invention is disclosed, wherein the semiconductor wafer 61 can also be connected to the carrier board unit 5 in a flip-chip bonding manner through a conductive bump 68. 1 Electrical connection. Furthermore, a plurality of conductive elements 67 (= fresh balls) may be formed on the lower surface 514 of the cough carrier plate unit 51 to be electrically connected to the outside. According to the above description, the carrier board unit 51 can also be in the form of a lead frame (1 e a d frame), that is, the enhanced heat dissipation package can be an outer casing without foot seal f.

1237366 五、發明說明（5) 體（如QFN形式；如圖8A及8B所示，係分別為本發明第三 四較佳實施例之加強散熱型封裝體）。值得注意的是— 8A及8B中各元件之參考符號係分別與圖7八及78中之 之參考符號相對應。 70 f 接著，如圖9所示，說明本發明之加強散熱型封裝體之 製造方法。 請參照圖9及圖1〇Α、10B至圖15。首先，在步驟” 提供一陣列型載板5，其包含複數個载板單元51(如圖1〇所 不）；接著，於步驟92中，將複數個半導體晶片61分別 連接至每一載板單元51 (如以覆晶接合連接或以打線接人之 方式（如圖11所示）；再者’在步驟93中，以一封膠單元“ 包覆該等半導體晶片61以形成一陣列式封膠體66(如圖⑴斤 不）；之後，在步驟94中，於陣列式封膠體之表面設置一 熱膠層71(如圖13所示）；最後，在步驟95中，對該陣列 封膠體進行一切割程序，以形成複數個封裝單元（如圖^ 不）。此外，當載板為一矩陣式載板時，亦可依上述流程 行封裝步驟。值得注意的是，圖10、UA、UB、12至15中 件之參考符號係分別與圖7A中之各元件之參考符號相 對應。 由於，該封裝體係藉封膠表面之散熱膠層來提高封 體的散熱性，以提升封裝體之散熱效果；再者，因散埶膠 為一薄膜狀，故可縮小封裝體之整體厚度。 ^ ” 於本實施例之詳細說明中所提出之^體的實施例僅為 了易於說明本發明之技術内容，而並非將本發明狹義地限1237366 V. Description of the invention (5) body (such as QFN form; as shown in Figs. 8A and 8B, they are the enhanced heat dissipation package of the third and fourth preferred embodiments of the present invention). It is worth noting that—the reference symbols of each component in 8A and 8B correspond to the reference symbols in Figures 7 and 78, respectively. 70f Next, as shown in FIG. 9, a method for manufacturing the heat-dissipating package of the present invention will be described. Please refer to FIG. 9 and FIGS. 10A, 10B to 15. First, in step ", an array-type carrier board 5 is provided, which includes a plurality of carrier board units 51 (as shown in Fig. 10). Next, in step 92, a plurality of semiconductor wafers 61 are connected to each carrier board respectively. Unit 51 (such as a flip-chip bonding connection or a wire connection to a person (as shown in FIG. 11); further 'in step 93, the semiconductor wafers 61 are covered with a glue unit to form an array type Then, in step 94, a hot glue layer 71 (as shown in FIG. 13) is provided on the surface of the array-type sealant. Finally, in step 95, the array is sealed. The colloid undergoes a cutting process to form a plurality of packaging units (see Figure ^ No). In addition, when the carrier board is a matrix carrier board, the packaging steps can also be performed according to the above process. It is worth noting that Figure 10, UA The reference symbols of UB, UB, 12 to 15 correspond to the reference symbols of each component in Figure 7A. Because the packaging system uses the heat-dissipating adhesive layer on the surface of the sealant to improve the heat dissipation of the package to enhance the package The heat dissipation effect of the body; It can reduce the overall thickness of the package. ^ "Are explained in detail in the present embodiment of the forth embodiment thereof ^ ease of illustration only technical contents of the present invention, rather than limit the invention narrowly

第10頁 1237366 五、發明說明（6) 制於該實施例，因此，在不超出本發明之精神及以下申請 專利範圍之情況，可作種種變化實施。Page 10 1237366 V. Description of the invention (6) It is based on this embodiment. Therefore, various changes can be implemented without departing from the spirit of the invention and the scope of the following patent applications.

H 1237366 圖式簡單說明 (五）、【圖式之簡單說明】 圖1至圖3為一示意圖，顯示習知薄型球格陣列封裝體 之製造步驟。 圖4A、圖5至圖6為一示意圖，顯示習知具有散熱片單 元之加強散熱型封裝體之製造步驟。 圖4 B為一示意圖，顯示習知之陣列型散熱片結構。 圖7A為一示意圖，顯示本發明第一較佳實施例之加強 散熱型封裝體。 圖7B為一示意圖，顯示本發明第二較佳實施例之加強 散熱型封裝體。 圖8 A為一示意圖，顯示本發明第三較佳實施例之加強 散熱型封裝體。 圖8B為一示意圖，顯示本發明第四較佳實施例之加強 散熱型封裝體。 圖9為一流程圖，顯示本發明較佳實施例加強散熱型封 裝體之製造方法的流程。 圖10A、圖10B、圖10C至圖14為一示意圖，顯示本發明 第一較佳實施例之加強散熱型封裝體之製造步驟。 【元件符號說明】 11 載板 11 載板單元 112 晶片承座 114 手指H 1237366 Brief Description of Drawings (5), [Simple Description of Drawings] Figures 1 to 3 are schematic views showing the manufacturing steps of a conventional thin ball grid array package. Fig. 4A, Fig. 5 to Fig. 6 are schematic diagrams showing manufacturing steps of a conventional heat-dissipating package having a heat sink unit. FIG. 4B is a schematic diagram showing a conventional array type heat sink structure. FIG. 7A is a schematic diagram showing a heat dissipation enhanced package of the first preferred embodiment of the present invention. FIG. 7B is a schematic view showing a reinforced heat dissipation package according to a second preferred embodiment of the present invention. FIG. 8A is a schematic view showing a reinforced heat dissipation package according to a third preferred embodiment of the present invention. FIG. 8B is a schematic diagram showing a reinforced heat dissipation package according to a fourth preferred embodiment of the present invention. FIG. 9 is a flowchart showing a flow of a method for manufacturing a heat-dissipating package according to a preferred embodiment of the present invention. FIG. 10A, FIG. 10B, FIG. 10C to FIG. 14 are schematic diagrams showing the manufacturing steps of the enhanced heat dissipation package of the first preferred embodiment of the present invention. [Description of component symbols] 11 carrier board 11 carrier board unit 112 wafer holder 114 fingers

1237366 圖式簡單說明 23 24 3 31 4 5 51 512 514 61 63 64 641 66 67 68 71 8 91 92 93 94 95 21 半導體晶片 金線 封膠體 散熱片 散熱片單元 模具 載板 載板單元 載板單元上表面 載板單元下表面 半導體晶片 導電線 封膠單元 封膠單元表面 陣列式封膠體 導電元件（銲球） 凸塊 散熱膠層 模具 提供一陣列型載板’其包含複數個載板單元 設置複數個半導體晶片於載板單元上並電 灌注塑料以形成陣列式封膠體 連接之 膠層：陣列式封膠體之表面 對陣列式封膠體進行-切割程序，以形成複數個1237366 Brief description of the drawings 23 24 3 31 4 5 51 512 514 61 63 64 641 66 67 68 71 8 91 92 93 94 95 21 Surface carrier board unit Lower surface Semiconductor wafer Conductive wire sealant unit Sealant unit Surface array type Sealant body conductive element (solder ball) The bump heat-dissipating layer mold provides an array carrier board 'It contains a plurality of carrier board units and a plurality of The semiconductor wafer is on the carrier board unit and is electrically infused with plastic to form the glue layer of the array type sealant. The array sealant is subjected to a cutting process on the surface of the array type sealant to form a plurality of sealants.

苐13頁 1237366苐 Page 13 1237366

第14頁Page 14

Claims (1)

1237366 六、申請專利範圍 — 1 · 一種加強散熱型封裝體，包含： 一載板單元，該載板單元具有一上表面及一下表面； 一半導體晶片，該半導體晶片係設置於該載板單元之上表 面並且與該載板單元電性連接； 一封膠單元，該封膠單元係包覆該載板單元之該上表面及 該半導體晶片；及 一散熱膠層，該散熱膠層係設置於該封膠之一表面上。 2 ·如申請專利範圍第1項所述之加強散熱型封裝體，其中更 包含複數個導電元件設置於該載板單元之下表面。 3 ·如申請專利範圍第2項所述之加強散熱型封裝體，其中該 導電元件係為銲球。 、μ 4 ·如申請專利範圍第1項所述之加強散熱型封裝體，其中該 半導體晶片更包含一主動面及一 2面，該半導體晶片係以 其背面面向該載板單元之上表面设置，該半導體晶片之主 動面係與該載板單元電性速接。 5 ·如申請專利範圍第4項所述之加強散熱型封裝體，更包含 複數條導電線，其係用以與該半導體晶片主動面電性連 接。 6·如申請專利範圍第1項所述之加強散熱型封裝體，其中該1237366 6. Scope of patent application — 1 · A heat-dissipating package includes: a carrier board unit having an upper surface and a lower surface; a semiconductor wafer which is disposed on the carrier board unit The upper surface is electrically connected to the carrier board unit; a glue unit, the glue sealing unit covers the upper surface of the carrier board unit and the semiconductor wafer; and a heat dissipation glue layer, the heat dissipation glue layer is disposed on the One of the sealants is on the surface. 2 · The enhanced heat dissipation package as described in item 1 of the patent application scope, further comprising a plurality of conductive elements disposed on a lower surface of the carrier board unit. 3. The enhanced heat-dissipating package as described in item 2 of the patent application scope, wherein the conductive element is a solder ball. , Μ 4 · The enhanced heat dissipation package as described in the first item of the patent application scope, wherein the semiconductor wafer further includes an active surface and a two surface, and the semiconductor wafer is arranged with its back surface facing the upper surface of the carrier board unit. The active surface of the semiconductor wafer is electrically connected to the carrier board unit. 5. The enhanced heat dissipation package as described in item 4 of the scope of the patent application, further comprising a plurality of conductive wires, which are used to electrically connect with the active surface of the semiconductor wafer. 6. The enhanced heat dissipation package as described in item 1 of the patent application scope, wherein 1237366 — " --.--.-. 1 ―" 六、申請專利範圍 半導體晶片係以覆晶接合方式與其該載板單元之上表面連 接。 7 ·如申請專利範圍第6項所述之加強散熱型封裝體，其中更 包含複數個導電凸塊係連接該載板單元與該半導體晶片。 8 ·如申請專利範圍第1項所述之加強散熱型封裝體，其中該 载板單元係為一導線架。 9 ·如申請專利範圍第8項所述之加強散熱型封裝體，其中該 導線架為一無外引腳形式。 1 〇 · —種加強散熱型封裝體之製造方法，包含·· 提供一陣列型載板，其包含複數個載板單元，該載板單元 具有一上表面及一下表面； 將複數個半導體晶片分別電性連接至每一載板單元； 以一塑料包覆該等半導體晶片及該陣列型載板之該上表 面’以形成一陣列式封膠體； 設置一散熱膠層於該陣列式封膠體之一表面；及 對該陣列式封膠體進行一切割程序，以形成複數個封装 元。 々早 1 1 ·如申請專利範圍第1 0項所述之加強散熱型封裝體之製1 方法，其中更包含複數個導電元件設置於該載板單元之下k1237366 — " --.--.-. 1 ― " VI. Patent Application Scope The semiconductor wafer is connected to the upper surface of the carrier board unit by flip chip bonding. 7. The enhanced heat dissipation package as described in item 6 of the patent application scope, further comprising a plurality of conductive bumps connected between the carrier board unit and the semiconductor wafer. 8. The enhanced heat dissipation package as described in the first item of the patent application scope, wherein the carrier board unit is a lead frame. 9. The enhanced heat dissipation package as described in item 8 of the scope of patent application, wherein the lead frame is in the form of an outer pin. 1 〇—A method for manufacturing a heat-dissipating package includes: providing an array carrier board including a plurality of carrier board units, the carrier board unit having an upper surface and a lower surface; and a plurality of semiconductor wafers respectively Electrically connected to each carrier board unit; covering the semiconductor wafers and the upper surface of the array-type carrier board with a plastic to form an array-type sealant; providing a heat-dissipating layer on the array-type sealant A surface; and performing a cutting process on the array-type sealant to form a plurality of packaging elements. 々 早 1 1 · The method 1 for manufacturing a reinforced heat-dissipating package as described in item 10 of the scope of patent application, which further includes a plurality of conductive elements disposed below the carrier board unit k 第16頁Page 16 12373661237366 第17頁Page 17
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